1 /* 2 * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PSCI_PRIVATE_H 8 #define PSCI_PRIVATE_H 9 10 #include <stdbool.h> 11 12 #include <arch.h> 13 #include <arch_helpers.h> 14 #include <common/bl_common.h> 15 #include <lib/bakery_lock.h> 16 #include <lib/el3_runtime/cpu_data.h> 17 #include <lib/psci/psci.h> 18 #include <lib/spinlock.h> 19 20 /* 21 * The PSCI capability which are provided by the generic code but does not 22 * depend on the platform or spd capabilities. 23 */ 24 #define PSCI_GENERIC_CAP \ 25 (define_psci_cap(PSCI_VERSION) | \ 26 define_psci_cap(PSCI_AFFINITY_INFO_AARCH64) | \ 27 define_psci_cap(PSCI_FEATURES)) 28 29 /* 30 * The PSCI capabilities mask for 64 bit functions. 31 */ 32 #define PSCI_CAP_64BIT_MASK \ 33 (define_psci_cap(PSCI_CPU_SUSPEND_AARCH64) | \ 34 define_psci_cap(PSCI_CPU_ON_AARCH64) | \ 35 define_psci_cap(PSCI_AFFINITY_INFO_AARCH64) | \ 36 define_psci_cap(PSCI_MIG_AARCH64) | \ 37 define_psci_cap(PSCI_MIG_INFO_UP_CPU_AARCH64) | \ 38 define_psci_cap(PSCI_NODE_HW_STATE_AARCH64) | \ 39 define_psci_cap(PSCI_SYSTEM_SUSPEND_AARCH64) | \ 40 define_psci_cap(PSCI_STAT_RESIDENCY_AARCH64) | \ 41 define_psci_cap(PSCI_STAT_COUNT_AARCH64) | \ 42 define_psci_cap(PSCI_SYSTEM_RESET2_AARCH64) | \ 43 define_psci_cap(PSCI_MEM_CHK_RANGE_AARCH64)) 44 45 /* Internally PSCI uses a uint16_t for various cpu indexes so 46 * define a limit to number of CPUs that can be initialised. 47 */ 48 #define PSCI_MAX_CPUS_INDEX 0xFFFFU 49 50 /* Invalid parent */ 51 #define PSCI_PARENT_NODE_INVALID 0xFFFFFFFFU 52 53 /* 54 * Helper functions to get/set the fields of PSCI per-cpu data. 55 */ 56 static inline void psci_set_aff_info_state(aff_info_state_t aff_state) 57 { 58 set_cpu_data(psci_svc_cpu_data.aff_info_state, aff_state); 59 } 60 61 static inline aff_info_state_t psci_get_aff_info_state(void) 62 { 63 return get_cpu_data(psci_svc_cpu_data.aff_info_state); 64 } 65 66 static inline aff_info_state_t psci_get_aff_info_state_by_idx(unsigned int idx) 67 { 68 return get_cpu_data_by_index(idx, 69 psci_svc_cpu_data.aff_info_state); 70 } 71 72 static inline void psci_set_aff_info_state_by_idx(unsigned int idx, 73 aff_info_state_t aff_state) 74 { 75 set_cpu_data_by_index(idx, 76 psci_svc_cpu_data.aff_info_state, aff_state); 77 } 78 79 static inline unsigned int psci_get_suspend_pwrlvl(void) 80 { 81 return get_cpu_data(psci_svc_cpu_data.target_pwrlvl); 82 } 83 84 static inline void psci_set_suspend_pwrlvl(unsigned int target_lvl) 85 { 86 set_cpu_data(psci_svc_cpu_data.target_pwrlvl, target_lvl); 87 } 88 89 static inline void psci_set_cpu_local_state(plat_local_state_t state) 90 { 91 set_cpu_data(psci_svc_cpu_data.local_state, state); 92 } 93 94 static inline plat_local_state_t psci_get_cpu_local_state(void) 95 { 96 return get_cpu_data(psci_svc_cpu_data.local_state); 97 } 98 99 static inline plat_local_state_t psci_get_cpu_local_state_by_idx( 100 unsigned int idx) 101 { 102 return get_cpu_data_by_index(idx, 103 psci_svc_cpu_data.local_state); 104 } 105 106 /* Helper function to identify a CPU standby request in PSCI Suspend call */ 107 static inline bool is_cpu_standby_req(unsigned int is_power_down_state, 108 unsigned int retn_lvl) 109 { 110 return (is_power_down_state == 0U) && (retn_lvl == 0U); 111 } 112 113 /******************************************************************************* 114 * The following two data structures implement the power domain tree. The tree 115 * is used to track the state of all the nodes i.e. power domain instances 116 * described by the platform. The tree consists of nodes that describe CPU power 117 * domains i.e. leaf nodes and all other power domains which are parents of a 118 * CPU power domain i.e. non-leaf nodes. 119 ******************************************************************************/ 120 typedef struct non_cpu_pwr_domain_node { 121 /* 122 * Index of the first CPU power domain node level 0 which has this node 123 * as its parent. 124 */ 125 unsigned int cpu_start_idx; 126 127 /* 128 * Number of CPU power domains which are siblings of the domain indexed 129 * by 'cpu_start_idx' i.e. all the domains in the range 'cpu_start_idx 130 * -> cpu_start_idx + ncpus' have this node as their parent. 131 */ 132 unsigned int ncpus; 133 134 /* 135 * Index of the parent power domain node. 136 * TODO: Figure out whether to whether using pointer is more efficient. 137 */ 138 unsigned int parent_node; 139 140 plat_local_state_t local_state; 141 142 unsigned char level; 143 144 /* For indexing the psci_lock array*/ 145 uint16_t lock_index; 146 } non_cpu_pd_node_t; 147 148 typedef struct cpu_pwr_domain_node { 149 u_register_t mpidr; 150 151 /* 152 * Index of the parent power domain node. 153 * TODO: Figure out whether to whether using pointer is more efficient. 154 */ 155 unsigned int parent_node; 156 157 /* 158 * A CPU power domain does not require state coordination like its 159 * parent power domains. Hence this node does not include a bakery 160 * lock. A spinlock is required by the CPU_ON handler to prevent a race 161 * when multiple CPUs try to turn ON the same target CPU. 162 */ 163 spinlock_t cpu_lock; 164 } cpu_pd_node_t; 165 166 #if PSCI_OS_INIT_MODE 167 /******************************************************************************* 168 * The supported power state coordination modes that can be used in CPU_SUSPEND. 169 ******************************************************************************/ 170 typedef enum suspend_mode { 171 PLAT_COORD = 0, 172 OS_INIT = 1 173 } suspend_mode_t; 174 #endif 175 176 /******************************************************************************* 177 * The following are helpers and declarations of locks. 178 ******************************************************************************/ 179 #if HW_ASSISTED_COHERENCY 180 /* 181 * On systems where participant CPUs are cache-coherent, we can use spinlocks 182 * instead of bakery locks. 183 */ 184 #define DEFINE_PSCI_LOCK(_name) spinlock_t _name 185 #define DECLARE_PSCI_LOCK(_name) extern DEFINE_PSCI_LOCK(_name) 186 187 /* One lock is required per non-CPU power domain node */ 188 DECLARE_PSCI_LOCK(psci_locks[PSCI_NUM_NON_CPU_PWR_DOMAINS]); 189 190 /* 191 * On systems with hardware-assisted coherency, make PSCI cache operations NOP, 192 * as PSCI participants are cache-coherent, and there's no need for explicit 193 * cache maintenance operations or barriers to coordinate their state. 194 */ 195 static inline void psci_flush_dcache_range(uintptr_t __unused addr, 196 size_t __unused size) 197 { 198 /* Empty */ 199 } 200 201 #define psci_flush_cpu_data(member) 202 #define psci_inv_cpu_data(member) 203 204 static inline void psci_dsbish(void) 205 { 206 /* Empty */ 207 } 208 209 static inline void psci_lock_get(non_cpu_pd_node_t *non_cpu_pd_node) 210 { 211 spin_lock(&psci_locks[non_cpu_pd_node->lock_index]); 212 } 213 214 static inline void psci_lock_release(non_cpu_pd_node_t *non_cpu_pd_node) 215 { 216 spin_unlock(&psci_locks[non_cpu_pd_node->lock_index]); 217 } 218 219 #else /* if HW_ASSISTED_COHERENCY == 0 */ 220 /* 221 * Use bakery locks for state coordination as not all PSCI participants are 222 * cache coherent. 223 */ 224 #define DEFINE_PSCI_LOCK(_name) DEFINE_BAKERY_LOCK(_name) 225 #define DECLARE_PSCI_LOCK(_name) DECLARE_BAKERY_LOCK(_name) 226 227 /* One lock is required per non-CPU power domain node */ 228 DECLARE_PSCI_LOCK(psci_locks[PSCI_NUM_NON_CPU_PWR_DOMAINS]); 229 230 /* 231 * If not all PSCI participants are cache-coherent, perform cache maintenance 232 * and issue barriers wherever required to coordinate state. 233 */ 234 static inline void psci_flush_dcache_range(uintptr_t addr, size_t size) 235 { 236 flush_dcache_range(addr, size); 237 } 238 239 #define psci_flush_cpu_data(member) flush_cpu_data(member) 240 #define psci_inv_cpu_data(member) inv_cpu_data(member) 241 242 static inline void psci_dsbish(void) 243 { 244 dsbish(); 245 } 246 247 static inline void psci_lock_get(non_cpu_pd_node_t *non_cpu_pd_node) 248 { 249 bakery_lock_get(&psci_locks[non_cpu_pd_node->lock_index]); 250 } 251 252 static inline void psci_lock_release(non_cpu_pd_node_t *non_cpu_pd_node) 253 { 254 bakery_lock_release(&psci_locks[non_cpu_pd_node->lock_index]); 255 } 256 257 #endif /* HW_ASSISTED_COHERENCY */ 258 259 static inline void psci_lock_init(non_cpu_pd_node_t *non_cpu_pd_node, 260 uint16_t idx) 261 { 262 non_cpu_pd_node[idx].lock_index = idx; 263 } 264 265 /******************************************************************************* 266 * Data prototypes 267 ******************************************************************************/ 268 extern const plat_psci_ops_t *psci_plat_pm_ops; 269 extern non_cpu_pd_node_t psci_non_cpu_pd_nodes[PSCI_NUM_NON_CPU_PWR_DOMAINS]; 270 extern cpu_pd_node_t psci_cpu_pd_nodes[PLATFORM_CORE_COUNT]; 271 extern unsigned int psci_caps; 272 extern unsigned int psci_plat_core_count; 273 #if PSCI_OS_INIT_MODE 274 extern suspend_mode_t psci_suspend_mode; 275 #endif 276 277 /******************************************************************************* 278 * SPD's power management hooks registered with PSCI 279 ******************************************************************************/ 280 extern const spd_pm_ops_t *psci_spd_pm; 281 282 /******************************************************************************* 283 * Function prototypes 284 ******************************************************************************/ 285 /* Private exported functions from psci_common.c */ 286 int psci_validate_power_state(unsigned int power_state, 287 psci_power_state_t *state_info); 288 void psci_query_sys_suspend_pwrstate(psci_power_state_t *state_info); 289 void psci_init_req_local_pwr_states(void); 290 #if PSCI_OS_INIT_MODE 291 void psci_update_req_local_pwr_states(unsigned int end_pwrlvl, 292 unsigned int cpu_idx, 293 psci_power_state_t *state_info, 294 plat_local_state_t *prev); 295 void psci_restore_req_local_pwr_states(unsigned int cpu_idx, 296 plat_local_state_t *prev); 297 #endif 298 void psci_get_target_local_pwr_states(unsigned int cpu_idx, unsigned int end_pwrlvl, 299 psci_power_state_t *target_state); 300 void psci_set_target_local_pwr_states(unsigned int cpu_idx, unsigned int end_pwrlvl, 301 const psci_power_state_t *target_state); 302 int psci_validate_entry_point(entry_point_info_t *ep, 303 uintptr_t entrypoint, u_register_t context_id); 304 void psci_get_parent_pwr_domain_nodes(unsigned int cpu_idx, 305 unsigned int end_lvl, 306 unsigned int *node_index); 307 void psci_do_state_coordination(unsigned int cpu_idx, unsigned int end_pwrlvl, 308 psci_power_state_t *state_info); 309 #if PSCI_OS_INIT_MODE 310 int psci_validate_state_coordination(unsigned int cpu_idx, unsigned int end_pwrlvl, 311 psci_power_state_t *state_info); 312 #endif 313 void psci_acquire_pwr_domain_locks(unsigned int end_pwrlvl, 314 const unsigned int *parent_nodes); 315 void psci_release_pwr_domain_locks(unsigned int end_pwrlvl, 316 const unsigned int *parent_nodes); 317 int psci_validate_suspend_req(const psci_power_state_t *state_info, 318 unsigned int is_power_down_state); 319 unsigned int psci_find_max_off_lvl(const psci_power_state_t *state_info); 320 unsigned int psci_find_target_suspend_lvl(const psci_power_state_t *state_info); 321 void psci_set_pwr_domains_to_run(unsigned int cpu_idx, unsigned int end_pwrlvl); 322 void psci_print_power_domain_map(void); 323 bool psci_is_last_on_cpu(unsigned int my_idx); 324 int psci_spd_migrate_info(u_register_t *mpidr); 325 326 /* 327 * CPU power down is directly called only when HW_ASSISTED_COHERENCY is 328 * available. Otherwise, this needs post-call stack maintenance, which is 329 * handled in assembly. 330 */ 331 void prepare_cpu_pwr_dwn(unsigned int power_level); 332 333 /* This function applies various CPU errata during power down. */ 334 void apply_cpu_pwr_dwn_errata(void); 335 336 /* Private exported functions from psci_on.c */ 337 int psci_cpu_on_start(u_register_t target_cpu, 338 const entry_point_info_t *ep); 339 340 void psci_cpu_on_finish(unsigned int cpu_idx, const psci_power_state_t *state_info); 341 342 /* Private exported functions from psci_off.c */ 343 int psci_do_cpu_off(unsigned int end_pwrlvl); 344 345 /* Private exported functions from psci_suspend.c */ 346 int psci_cpu_suspend_start(unsigned int idx, 347 const entry_point_info_t *ep, 348 unsigned int end_pwrlvl, 349 psci_power_state_t *state_info, 350 unsigned int is_power_down_state); 351 352 void psci_cpu_suspend_to_powerdown_finish(unsigned int cpu_idx, unsigned int max_off_lvl, const psci_power_state_t *state_info); 353 354 /* Private exported functions from psci_helpers.S */ 355 void psci_do_pwrdown_cache_maintenance(unsigned int pwr_level); 356 void psci_do_pwrup_cache_maintenance(void); 357 358 /* Private exported functions from psci_system_off.c */ 359 void __dead2 psci_system_off(void); 360 void __dead2 psci_system_reset(void); 361 u_register_t psci_system_reset2(uint32_t reset_type, u_register_t cookie); 362 363 /* Private exported functions from psci_stat.c */ 364 void psci_stats_update_pwr_down(unsigned int cpu_idx, unsigned int end_pwrlvl, 365 const psci_power_state_t *state_info); 366 void psci_stats_update_pwr_up(unsigned int cpu_idx, unsigned int end_pwrlvl, 367 const psci_power_state_t *state_info); 368 u_register_t psci_stat_residency(u_register_t target_cpu, 369 unsigned int power_state); 370 u_register_t psci_stat_count(u_register_t target_cpu, 371 unsigned int power_state); 372 373 /* Private exported functions from psci_mem_protect.c */ 374 u_register_t psci_mem_protect(unsigned int enable); 375 u_register_t psci_mem_chk_range(uintptr_t base, u_register_t length); 376 377 #endif /* PSCI_PRIVATE_H */ 378