1 /* 2 * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <assert.h> 10 #include <bl_common.h> 11 #include <context_mgmt.h> 12 #include <debug.h> 13 #include <platform.h> 14 #include <stddef.h> 15 #include "psci_private.h" 16 17 /******************************************************************************* 18 * This function checks whether a cpu which has been requested to be turned on 19 * is OFF to begin with. 20 ******************************************************************************/ 21 static int cpu_on_validate_state(aff_info_state_t aff_state) 22 { 23 if (aff_state == AFF_STATE_ON) 24 return PSCI_E_ALREADY_ON; 25 26 if (aff_state == AFF_STATE_ON_PENDING) 27 return PSCI_E_ON_PENDING; 28 29 assert(aff_state == AFF_STATE_OFF); 30 return PSCI_E_SUCCESS; 31 } 32 33 /******************************************************************************* 34 * Generic handler which is called to physically power on a cpu identified by 35 * its mpidr. It performs the generic, architectural, platform setup and state 36 * management to power on the target cpu e.g. it will ensure that 37 * enough information is stashed for it to resume execution in the non-secure 38 * security state. 39 * 40 * The state of all the relevant power domains are changed after calling the 41 * platform handler as it can return error. 42 ******************************************************************************/ 43 int psci_cpu_on_start(u_register_t target_cpu, 44 entry_point_info_t *ep) 45 { 46 int rc; 47 unsigned int target_idx = plat_core_pos_by_mpidr(target_cpu); 48 aff_info_state_t target_aff_state; 49 50 /* Calling function must supply valid input arguments */ 51 assert((int) target_idx >= 0); 52 assert(ep != NULL); 53 54 /* 55 * This function must only be called on platforms where the 56 * CPU_ON platform hooks have been implemented. 57 */ 58 assert(psci_plat_pm_ops->pwr_domain_on && 59 psci_plat_pm_ops->pwr_domain_on_finish); 60 61 /* Protect against multiple CPUs trying to turn ON the same target CPU */ 62 psci_spin_lock_cpu(target_idx); 63 64 /* 65 * Generic management: Ensure that the cpu is off to be 66 * turned on. 67 * Perform cache maintanence ahead of reading the target CPU state to 68 * ensure that the data is not stale. 69 * There is a theoretical edge case where the cache may contain stale 70 * data for the target CPU data - this can occur under the following 71 * conditions: 72 * - the target CPU is in another cluster from the current 73 * - the target CPU was the last CPU to shutdown on its cluster 74 * - the cluster was removed from coherency as part of the CPU shutdown 75 * 76 * In this case the cache maintenace that was performed as part of the 77 * target CPUs shutdown was not seen by the current CPU's cluster. And 78 * so the cache may contain stale data for the target CPU. 79 */ 80 flush_cpu_data_by_index(target_idx, psci_svc_cpu_data.aff_info_state); 81 rc = cpu_on_validate_state(psci_get_aff_info_state_by_idx(target_idx)); 82 if (rc != PSCI_E_SUCCESS) 83 goto exit; 84 85 /* 86 * Call the cpu on handler registered by the Secure Payload Dispatcher 87 * to let it do any bookeeping. If the handler encounters an error, it's 88 * expected to assert within 89 */ 90 if (psci_spd_pm && psci_spd_pm->svc_on) 91 psci_spd_pm->svc_on(target_cpu); 92 93 /* 94 * Set the Affinity info state of the target cpu to ON_PENDING. 95 * Flush aff_info_state as it will be accessed with caches 96 * turned OFF. 97 */ 98 psci_set_aff_info_state_by_idx(target_idx, AFF_STATE_ON_PENDING); 99 flush_cpu_data_by_index(target_idx, psci_svc_cpu_data.aff_info_state); 100 101 /* 102 * The cache line invalidation by the target CPU after setting the 103 * state to OFF (see psci_do_cpu_off()), could cause the update to 104 * aff_info_state to be invalidated. Retry the update if the target 105 * CPU aff_info_state is not ON_PENDING. 106 */ 107 target_aff_state = psci_get_aff_info_state_by_idx(target_idx); 108 if (target_aff_state != AFF_STATE_ON_PENDING) { 109 assert(target_aff_state == AFF_STATE_OFF); 110 psci_set_aff_info_state_by_idx(target_idx, AFF_STATE_ON_PENDING); 111 flush_cpu_data_by_index(target_idx, psci_svc_cpu_data.aff_info_state); 112 113 assert(psci_get_aff_info_state_by_idx(target_idx) == AFF_STATE_ON_PENDING); 114 } 115 116 /* 117 * Perform generic, architecture and platform specific handling. 118 */ 119 /* 120 * Plat. management: Give the platform the current state 121 * of the target cpu to allow it to perform the necessary 122 * steps to power on. 123 */ 124 rc = psci_plat_pm_ops->pwr_domain_on(target_cpu); 125 assert(rc == PSCI_E_SUCCESS || rc == PSCI_E_INTERN_FAIL); 126 127 if (rc == PSCI_E_SUCCESS) 128 /* Store the re-entry information for the non-secure world. */ 129 cm_init_context_by_index(target_idx, ep); 130 else { 131 /* Restore the state on error. */ 132 psci_set_aff_info_state_by_idx(target_idx, AFF_STATE_OFF); 133 flush_cpu_data_by_index(target_idx, psci_svc_cpu_data.aff_info_state); 134 } 135 136 exit: 137 psci_spin_unlock_cpu(target_idx); 138 return rc; 139 } 140 141 /******************************************************************************* 142 * The following function finish an earlier power on request. They 143 * are called by the common finisher routine in psci_common.c. The `state_info` 144 * is the psci_power_state from which this CPU has woken up from. 145 ******************************************************************************/ 146 void psci_cpu_on_finish(unsigned int cpu_idx, 147 psci_power_state_t *state_info) 148 { 149 /* 150 * Plat. management: Perform the platform specific actions 151 * for this cpu e.g. enabling the gic or zeroing the mailbox 152 * register. The actual state of this cpu has already been 153 * changed. 154 */ 155 psci_plat_pm_ops->pwr_domain_on_finish(state_info); 156 157 #if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY) 158 /* 159 * Arch. management: Enable data cache and manage stack memory 160 */ 161 psci_do_pwrup_cache_maintenance(); 162 #endif 163 164 /* 165 * All the platform specific actions for turning this cpu 166 * on have completed. Perform enough arch.initialization 167 * to run in the non-secure address space. 168 */ 169 psci_arch_setup(); 170 171 /* 172 * Lock the CPU spin lock to make sure that the context initialization 173 * is done. Since the lock is only used in this function to create 174 * a synchronization point with cpu_on_start(), it can be released 175 * immediately. 176 */ 177 psci_spin_lock_cpu(cpu_idx); 178 psci_spin_unlock_cpu(cpu_idx); 179 180 /* Ensure we have been explicitly woken up by another cpu */ 181 assert(psci_get_aff_info_state() == AFF_STATE_ON_PENDING); 182 183 /* 184 * Call the cpu on finish handler registered by the Secure Payload 185 * Dispatcher to let it do any bookeeping. If the handler encounters an 186 * error, it's expected to assert within 187 */ 188 if (psci_spd_pm && psci_spd_pm->svc_on_finish) 189 psci_spd_pm->svc_on_finish(0); 190 191 /* Populate the mpidr field within the cpu node array */ 192 /* This needs to be done only once */ 193 psci_cpu_pd_nodes[cpu_idx].mpidr = read_mpidr() & MPIDR_AFFINITY_MASK; 194 195 /* 196 * Generic management: Now we just need to retrieve the 197 * information that we had stashed away during the cpu_on 198 * call to set this cpu on its way. 199 */ 200 cm_prepare_el3_exit(NON_SECURE); 201 } 202