1 /* 2 * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch.h> 32 #include <arch_helpers.h> 33 #include <assert.h> 34 #include <bl_common.h> 35 #include <debug.h> 36 #include <context_mgmt.h> 37 #include <platform.h> 38 #include <stddef.h> 39 #include "psci_private.h" 40 41 /******************************************************************************* 42 * This function checks whether a cpu which has been requested to be turned on 43 * is OFF to begin with. 44 ******************************************************************************/ 45 static int cpu_on_validate_state(aff_info_state_t aff_state) 46 { 47 if (aff_state == AFF_STATE_ON) 48 return PSCI_E_ALREADY_ON; 49 50 if (aff_state == AFF_STATE_ON_PENDING) 51 return PSCI_E_ON_PENDING; 52 53 assert(aff_state == AFF_STATE_OFF); 54 return PSCI_E_SUCCESS; 55 } 56 57 /******************************************************************************* 58 * Generic handler which is called to physically power on a cpu identified by 59 * its mpidr. It performs the generic, architectural, platform setup and state 60 * management to power on the target cpu e.g. it will ensure that 61 * enough information is stashed for it to resume execution in the non-secure 62 * security state. 63 * 64 * The state of all the relevant power domains are changed after calling the 65 * platform handler as it can return error. 66 ******************************************************************************/ 67 int psci_cpu_on_start(u_register_t target_cpu, 68 entry_point_info_t *ep) 69 { 70 int rc; 71 unsigned int target_idx = plat_core_pos_by_mpidr(target_cpu); 72 aff_info_state_t target_aff_state; 73 74 /* Calling function must supply valid input arguments */ 75 assert((int) target_idx >= 0); 76 assert(ep != NULL); 77 78 /* 79 * This function must only be called on platforms where the 80 * CPU_ON platform hooks have been implemented. 81 */ 82 assert(psci_plat_pm_ops->pwr_domain_on && 83 psci_plat_pm_ops->pwr_domain_on_finish); 84 85 /* Protect against multiple CPUs trying to turn ON the same target CPU */ 86 psci_spin_lock_cpu(target_idx); 87 88 /* 89 * Generic management: Ensure that the cpu is off to be 90 * turned on. 91 */ 92 rc = cpu_on_validate_state(psci_get_aff_info_state_by_idx(target_idx)); 93 if (rc != PSCI_E_SUCCESS) 94 goto exit; 95 96 /* 97 * Call the cpu on handler registered by the Secure Payload Dispatcher 98 * to let it do any bookeeping. If the handler encounters an error, it's 99 * expected to assert within 100 */ 101 if (psci_spd_pm && psci_spd_pm->svc_on) 102 psci_spd_pm->svc_on(target_cpu); 103 104 /* 105 * Set the Affinity info state of the target cpu to ON_PENDING. 106 * Flush aff_info_state as it will be accessed with caches 107 * turned OFF. 108 */ 109 psci_set_aff_info_state_by_idx(target_idx, AFF_STATE_ON_PENDING); 110 flush_cpu_data_by_index(target_idx, psci_svc_cpu_data.aff_info_state); 111 112 /* 113 * The cache line invalidation by the target CPU after setting the 114 * state to OFF (see psci_do_cpu_off()), could cause the update to 115 * aff_info_state to be invalidated. Retry the update if the target 116 * CPU aff_info_state is not ON_PENDING. 117 */ 118 target_aff_state = psci_get_aff_info_state_by_idx(target_idx); 119 if (target_aff_state != AFF_STATE_ON_PENDING) { 120 assert(target_aff_state == AFF_STATE_OFF); 121 psci_set_aff_info_state_by_idx(target_idx, AFF_STATE_ON_PENDING); 122 flush_cpu_data_by_index(target_idx, psci_svc_cpu_data.aff_info_state); 123 124 assert(psci_get_aff_info_state_by_idx(target_idx) == AFF_STATE_ON_PENDING); 125 } 126 127 /* 128 * Perform generic, architecture and platform specific handling. 129 */ 130 /* 131 * Plat. management: Give the platform the current state 132 * of the target cpu to allow it to perform the necessary 133 * steps to power on. 134 */ 135 rc = psci_plat_pm_ops->pwr_domain_on(target_cpu); 136 assert(rc == PSCI_E_SUCCESS || rc == PSCI_E_INTERN_FAIL); 137 138 if (rc == PSCI_E_SUCCESS) 139 /* Store the re-entry information for the non-secure world. */ 140 cm_init_context_by_index(target_idx, ep); 141 else { 142 /* Restore the state on error. */ 143 psci_set_aff_info_state_by_idx(target_idx, AFF_STATE_OFF); 144 flush_cpu_data_by_index(target_idx, psci_svc_cpu_data.aff_info_state); 145 } 146 147 exit: 148 psci_spin_unlock_cpu(target_idx); 149 return rc; 150 } 151 152 /******************************************************************************* 153 * The following function finish an earlier power on request. They 154 * are called by the common finisher routine in psci_common.c. The `state_info` 155 * is the psci_power_state from which this CPU has woken up from. 156 ******************************************************************************/ 157 void psci_cpu_on_finish(unsigned int cpu_idx, 158 psci_power_state_t *state_info) 159 { 160 /* 161 * Plat. management: Perform the platform specific actions 162 * for this cpu e.g. enabling the gic or zeroing the mailbox 163 * register. The actual state of this cpu has already been 164 * changed. 165 */ 166 psci_plat_pm_ops->pwr_domain_on_finish(state_info); 167 168 #if !HW_ASSISTED_COHERENCY 169 /* 170 * Arch. management: Enable data cache and manage stack memory 171 */ 172 psci_do_pwrup_cache_maintenance(); 173 #endif 174 175 /* 176 * All the platform specific actions for turning this cpu 177 * on have completed. Perform enough arch.initialization 178 * to run in the non-secure address space. 179 */ 180 psci_arch_setup(); 181 182 /* 183 * Lock the CPU spin lock to make sure that the context initialization 184 * is done. Since the lock is only used in this function to create 185 * a synchronization point with cpu_on_start(), it can be released 186 * immediately. 187 */ 188 psci_spin_lock_cpu(cpu_idx); 189 psci_spin_unlock_cpu(cpu_idx); 190 191 /* Ensure we have been explicitly woken up by another cpu */ 192 assert(psci_get_aff_info_state() == AFF_STATE_ON_PENDING); 193 194 /* 195 * Call the cpu on finish handler registered by the Secure Payload 196 * Dispatcher to let it do any bookeeping. If the handler encounters an 197 * error, it's expected to assert within 198 */ 199 if (psci_spd_pm && psci_spd_pm->svc_on_finish) 200 psci_spd_pm->svc_on_finish(0); 201 202 /* Populate the mpidr field within the cpu node array */ 203 /* This needs to be done only once */ 204 psci_cpu_pd_nodes[cpu_idx].mpidr = read_mpidr() & MPIDR_AFFINITY_MASK; 205 206 /* 207 * Generic management: Now we just need to retrieve the 208 * information that we had stashed away during the cpu_on 209 * call to set this cpu on its way. 210 */ 211 cm_prepare_el3_exit(NON_SECURE); 212 } 213