1 /* 2 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <assert.h> 10 #include <bl_common.h> 11 #include <context_mgmt.h> 12 #include <debug.h> 13 #include <platform.h> 14 #include <pubsub_events.h> 15 #include <stddef.h> 16 #include "psci_private.h" 17 18 /* 19 * Helper functions for the CPU level spinlocks 20 */ 21 static inline void psci_spin_lock_cpu(int idx) 22 { 23 spin_lock(&psci_cpu_pd_nodes[idx].cpu_lock); 24 } 25 26 static inline void psci_spin_unlock_cpu(int idx) 27 { 28 spin_unlock(&psci_cpu_pd_nodes[idx].cpu_lock); 29 } 30 31 /******************************************************************************* 32 * This function checks whether a cpu which has been requested to be turned on 33 * is OFF to begin with. 34 ******************************************************************************/ 35 static int cpu_on_validate_state(aff_info_state_t aff_state) 36 { 37 if (aff_state == AFF_STATE_ON) 38 return PSCI_E_ALREADY_ON; 39 40 if (aff_state == AFF_STATE_ON_PENDING) 41 return PSCI_E_ON_PENDING; 42 43 assert(aff_state == AFF_STATE_OFF); 44 return PSCI_E_SUCCESS; 45 } 46 47 /******************************************************************************* 48 * Generic handler which is called to physically power on a cpu identified by 49 * its mpidr. It performs the generic, architectural, platform setup and state 50 * management to power on the target cpu e.g. it will ensure that 51 * enough information is stashed for it to resume execution in the non-secure 52 * security state. 53 * 54 * The state of all the relevant power domains are changed after calling the 55 * platform handler as it can return error. 56 ******************************************************************************/ 57 int psci_cpu_on_start(u_register_t target_cpu, 58 const entry_point_info_t *ep) 59 { 60 int rc; 61 aff_info_state_t target_aff_state; 62 int target_idx = plat_core_pos_by_mpidr(target_cpu); 63 64 /* Calling function must supply valid input arguments */ 65 assert(target_idx >= 0); 66 assert(ep != NULL); 67 68 /* 69 * This function must only be called on platforms where the 70 * CPU_ON platform hooks have been implemented. 71 */ 72 assert((psci_plat_pm_ops->pwr_domain_on != NULL) && 73 (psci_plat_pm_ops->pwr_domain_on_finish != NULL)); 74 75 /* Protect against multiple CPUs trying to turn ON the same target CPU */ 76 psci_spin_lock_cpu(target_idx); 77 78 /* 79 * Generic management: Ensure that the cpu is off to be 80 * turned on. 81 * Perform cache maintanence ahead of reading the target CPU state to 82 * ensure that the data is not stale. 83 * There is a theoretical edge case where the cache may contain stale 84 * data for the target CPU data - this can occur under the following 85 * conditions: 86 * - the target CPU is in another cluster from the current 87 * - the target CPU was the last CPU to shutdown on its cluster 88 * - the cluster was removed from coherency as part of the CPU shutdown 89 * 90 * In this case the cache maintenace that was performed as part of the 91 * target CPUs shutdown was not seen by the current CPU's cluster. And 92 * so the cache may contain stale data for the target CPU. 93 */ 94 flush_cpu_data_by_index((unsigned int)target_idx, 95 psci_svc_cpu_data.aff_info_state); 96 rc = cpu_on_validate_state(psci_get_aff_info_state_by_idx(target_idx)); 97 if (rc != PSCI_E_SUCCESS) 98 goto exit; 99 100 /* 101 * Call the cpu on handler registered by the Secure Payload Dispatcher 102 * to let it do any bookeeping. If the handler encounters an error, it's 103 * expected to assert within 104 */ 105 if ((psci_spd_pm != NULL) && (psci_spd_pm->svc_on != NULL)) 106 psci_spd_pm->svc_on(target_cpu); 107 108 /* 109 * Set the Affinity info state of the target cpu to ON_PENDING. 110 * Flush aff_info_state as it will be accessed with caches 111 * turned OFF. 112 */ 113 psci_set_aff_info_state_by_idx(target_idx, AFF_STATE_ON_PENDING); 114 flush_cpu_data_by_index((unsigned int)target_idx, 115 psci_svc_cpu_data.aff_info_state); 116 117 /* 118 * The cache line invalidation by the target CPU after setting the 119 * state to OFF (see psci_do_cpu_off()), could cause the update to 120 * aff_info_state to be invalidated. Retry the update if the target 121 * CPU aff_info_state is not ON_PENDING. 122 */ 123 target_aff_state = psci_get_aff_info_state_by_idx(target_idx); 124 if (target_aff_state != AFF_STATE_ON_PENDING) { 125 assert(target_aff_state == AFF_STATE_OFF); 126 psci_set_aff_info_state_by_idx(target_idx, AFF_STATE_ON_PENDING); 127 flush_cpu_data_by_index((unsigned int)target_idx, 128 psci_svc_cpu_data.aff_info_state); 129 130 assert(psci_get_aff_info_state_by_idx(target_idx) == 131 AFF_STATE_ON_PENDING); 132 } 133 134 /* 135 * Perform generic, architecture and platform specific handling. 136 */ 137 /* 138 * Plat. management: Give the platform the current state 139 * of the target cpu to allow it to perform the necessary 140 * steps to power on. 141 */ 142 rc = psci_plat_pm_ops->pwr_domain_on(target_cpu); 143 assert((rc == PSCI_E_SUCCESS) || (rc == PSCI_E_INTERN_FAIL)); 144 145 if (rc == PSCI_E_SUCCESS) 146 /* Store the re-entry information for the non-secure world. */ 147 cm_init_context_by_index((unsigned int)target_idx, ep); 148 else { 149 /* Restore the state on error. */ 150 psci_set_aff_info_state_by_idx(target_idx, AFF_STATE_OFF); 151 flush_cpu_data_by_index((unsigned int)target_idx, 152 psci_svc_cpu_data.aff_info_state); 153 } 154 155 exit: 156 psci_spin_unlock_cpu(target_idx); 157 return rc; 158 } 159 160 /******************************************************************************* 161 * The following function finish an earlier power on request. They 162 * are called by the common finisher routine in psci_common.c. The `state_info` 163 * is the psci_power_state from which this CPU has woken up from. 164 ******************************************************************************/ 165 void psci_cpu_on_finish(int cpu_idx, const psci_power_state_t *state_info) 166 { 167 /* 168 * Plat. management: Perform the platform specific actions 169 * for this cpu e.g. enabling the gic or zeroing the mailbox 170 * register. The actual state of this cpu has already been 171 * changed. 172 */ 173 psci_plat_pm_ops->pwr_domain_on_finish(state_info); 174 175 #if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY) 176 /* 177 * Arch. management: Enable data cache and manage stack memory 178 */ 179 psci_do_pwrup_cache_maintenance(); 180 #endif 181 182 /* 183 * All the platform specific actions for turning this cpu 184 * on have completed. Perform enough arch.initialization 185 * to run in the non-secure address space. 186 */ 187 psci_arch_setup(); 188 189 /* 190 * Lock the CPU spin lock to make sure that the context initialization 191 * is done. Since the lock is only used in this function to create 192 * a synchronization point with cpu_on_start(), it can be released 193 * immediately. 194 */ 195 psci_spin_lock_cpu(cpu_idx); 196 psci_spin_unlock_cpu(cpu_idx); 197 198 /* Ensure we have been explicitly woken up by another cpu */ 199 assert(psci_get_aff_info_state() == AFF_STATE_ON_PENDING); 200 201 /* 202 * Call the cpu on finish handler registered by the Secure Payload 203 * Dispatcher to let it do any bookeeping. If the handler encounters an 204 * error, it's expected to assert within 205 */ 206 if ((psci_spd_pm != NULL) && (psci_spd_pm->svc_on_finish != NULL)) 207 psci_spd_pm->svc_on_finish(0); 208 209 PUBLISH_EVENT(psci_cpu_on_finish); 210 211 /* Populate the mpidr field within the cpu node array */ 212 /* This needs to be done only once */ 213 psci_cpu_pd_nodes[cpu_idx].mpidr = read_mpidr() & MPIDR_AFFINITY_MASK; 214 215 /* 216 * Generic management: Now we just need to retrieve the 217 * information that we had stashed away during the cpu_on 218 * call to set this cpu on its way. 219 */ 220 cm_prepare_el3_exit(NON_SECURE); 221 } 222