1 /* 2 * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stddef.h> 9 10 #include <arch.h> 11 #include <arch_helpers.h> 12 #include <common/bl_common.h> 13 #include <common/debug.h> 14 #include <drivers/arm/gic.h> 15 #include <lib/el3_runtime/context_mgmt.h> 16 #include <lib/el3_runtime/pubsub_events.h> 17 #include <plat/common/platform.h> 18 19 #include "psci_private.h" 20 21 /* 22 * Helper functions for the CPU level spinlocks 23 */ 24 static inline void psci_spin_lock_cpu(unsigned int idx) 25 { 26 spin_lock(&psci_cpu_pd_nodes[idx].cpu_lock); 27 } 28 29 static inline void psci_spin_unlock_cpu(unsigned int idx) 30 { 31 spin_unlock(&psci_cpu_pd_nodes[idx].cpu_lock); 32 } 33 34 /******************************************************************************* 35 * This function checks whether a cpu which has been requested to be turned on 36 * is OFF to begin with. 37 ******************************************************************************/ 38 static int cpu_on_validate_state(aff_info_state_t aff_state) 39 { 40 if (aff_state == AFF_STATE_ON) 41 return PSCI_E_ALREADY_ON; 42 43 if (aff_state == AFF_STATE_ON_PENDING) 44 return PSCI_E_ON_PENDING; 45 46 assert(aff_state == AFF_STATE_OFF); 47 return PSCI_E_SUCCESS; 48 } 49 50 /******************************************************************************* 51 * Generic handler which is called to physically power on a cpu identified by 52 * its mpidr. It performs the generic, architectural, platform setup and state 53 * management to power on the target cpu e.g. it will ensure that 54 * enough information is stashed for it to resume execution in the non-secure 55 * security state. 56 * 57 * The state of all the relevant power domains are changed after calling the 58 * platform handler as it can return error. 59 ******************************************************************************/ 60 int psci_cpu_on_start(u_register_t target_cpu, 61 const entry_point_info_t *ep) 62 { 63 int rc; 64 aff_info_state_t target_aff_state; 65 unsigned int target_idx = (unsigned int)plat_core_pos_by_mpidr(target_cpu); 66 67 /* 68 * This function must only be called on platforms where the 69 * CPU_ON platform hooks have been implemented. 70 */ 71 assert((psci_plat_pm_ops->pwr_domain_on != NULL) && 72 (psci_plat_pm_ops->pwr_domain_on_finish != NULL)); 73 74 /* Protect against multiple CPUs trying to turn ON the same target CPU */ 75 psci_spin_lock_cpu(target_idx); 76 77 /* 78 * Generic management: Ensure that the cpu is off to be 79 * turned on. 80 * Perform cache maintanence ahead of reading the target CPU state to 81 * ensure that the data is not stale. 82 * There is a theoretical edge case where the cache may contain stale 83 * data for the target CPU data - this can occur under the following 84 * conditions: 85 * - the target CPU is in another cluster from the current 86 * - the target CPU was the last CPU to shutdown on its cluster 87 * - the cluster was removed from coherency as part of the CPU shutdown 88 * 89 * In this case the cache maintenace that was performed as part of the 90 * target CPUs shutdown was not seen by the current CPU's cluster. And 91 * so the cache may contain stale data for the target CPU. 92 */ 93 flush_cpu_data_by_index(target_idx, 94 psci_svc_cpu_data.aff_info_state); 95 rc = cpu_on_validate_state(psci_get_aff_info_state_by_idx(target_idx)); 96 if (rc != PSCI_E_SUCCESS) 97 goto on_exit; 98 99 /* 100 * Call the cpu on handler registered by the Secure Payload Dispatcher 101 * to let it do any bookeeping. If the handler encounters an error, it's 102 * expected to assert within 103 */ 104 if ((psci_spd_pm != NULL) && (psci_spd_pm->svc_on != NULL)) { 105 psci_spd_pm->svc_on(target_cpu); 106 } 107 108 /* 109 * Set the Affinity info state of the target cpu to ON_PENDING. 110 * Flush aff_info_state as it will be accessed with caches 111 * turned OFF. 112 */ 113 psci_set_aff_info_state_by_idx(target_idx, AFF_STATE_ON_PENDING); 114 flush_cpu_data_by_index(target_idx, 115 psci_svc_cpu_data.aff_info_state); 116 117 /* 118 * The cache line invalidation by the target CPU after setting the 119 * state to OFF (see psci_do_cpu_off()), could cause the update to 120 * aff_info_state to be invalidated. Retry the update if the target 121 * CPU aff_info_state is not ON_PENDING. 122 */ 123 target_aff_state = psci_get_aff_info_state_by_idx(target_idx); 124 if (target_aff_state != AFF_STATE_ON_PENDING) { 125 assert(target_aff_state == AFF_STATE_OFF); 126 psci_set_aff_info_state_by_idx(target_idx, AFF_STATE_ON_PENDING); 127 flush_cpu_data_by_index(target_idx, 128 psci_svc_cpu_data.aff_info_state); 129 130 assert(psci_get_aff_info_state_by_idx(target_idx) == 131 AFF_STATE_ON_PENDING); 132 } 133 134 /* 135 * Perform generic, architecture and platform specific handling. 136 */ 137 /* 138 * Plat. management: Give the platform the current state 139 * of the target cpu to allow it to perform the necessary 140 * steps to power on. 141 */ 142 rc = psci_plat_pm_ops->pwr_domain_on(target_cpu); 143 assert((rc == PSCI_E_SUCCESS) || (rc == PSCI_E_INTERN_FAIL)); 144 145 if (rc != PSCI_E_SUCCESS) { 146 /* Restore the state on error. */ 147 psci_set_aff_info_state_by_idx(target_idx, AFF_STATE_OFF); 148 flush_cpu_data_by_index(target_idx, 149 psci_svc_cpu_data.aff_info_state); 150 } 151 152 on_exit: 153 psci_spin_unlock_cpu(target_idx); 154 return rc; 155 } 156 157 /******************************************************************************* 158 * The following function finish an earlier power on request. They 159 * are called by the common finisher routine in psci_common.c. The `state_info` 160 * is the psci_power_state from which this CPU has woken up from. 161 ******************************************************************************/ 162 void psci_cpu_on_finish(unsigned int cpu_idx, const psci_power_state_t *state_info) 163 { 164 /* 165 * Plat. management: Perform the platform specific actions 166 * for this cpu e.g. enabling the gic or zeroing the mailbox 167 * register. The actual state of this cpu has already been 168 * changed. 169 */ 170 psci_plat_pm_ops->pwr_domain_on_finish(state_info); 171 172 #if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY) 173 /* 174 * Arch. management: Enable data cache and manage stack memory 175 */ 176 psci_do_pwrup_cache_maintenance(); 177 #endif 178 179 /* 180 * Plat. management: Perform any platform specific actions which 181 * can only be done with the cpu and the cluster guaranteed to 182 * be coherent. 183 */ 184 if (psci_plat_pm_ops->pwr_domain_on_finish_late != NULL) { 185 psci_plat_pm_ops->pwr_domain_on_finish_late(state_info); 186 } 187 188 #if USE_GIC_DRIVER 189 /* GIC init after platform has had a say with MMU on */ 190 gic_pcpu_init(cpu_idx); 191 gic_cpuif_enable(cpu_idx); 192 #endif /* USE_GIC_DRIVER */ 193 194 /* 195 * All the platform specific actions for turning this cpu 196 * on have completed. Perform enough arch.initialization 197 * to run in the non-secure address space. 198 */ 199 psci_arch_setup(); 200 201 /* 202 * Lock the CPU spin lock to make sure that the context initialization 203 * is done. Since the lock is only used in this function to create 204 * a synchronization point with cpu_on_start(), it can be released 205 * immediately. 206 */ 207 psci_spin_lock_cpu(cpu_idx); 208 psci_spin_unlock_cpu(cpu_idx); 209 210 /* Ensure we have been explicitly woken up by another cpu */ 211 assert(psci_get_aff_info_state() == AFF_STATE_ON_PENDING); 212 213 /* 214 * Call the cpu on finish handler registered by the Secure Payload 215 * Dispatcher to let it do any bookeeping. If the handler encounters an 216 * error, it's expected to assert within 217 */ 218 if ((psci_spd_pm != NULL) && (psci_spd_pm->svc_on_finish != NULL)) { 219 psci_spd_pm->svc_on_finish(0); 220 } 221 PUBLISH_EVENT(psci_cpu_on_finish); 222 223 /* Populate the mpidr field within the cpu node array */ 224 /* This needs to be done only once */ 225 psci_cpu_pd_nodes[cpu_idx].mpidr = read_mpidr() & MPIDR_AFFINITY_MASK; 226 } 227