1 /* 2 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <string.h> 9 10 #include <arch.h> 11 #include <arch_helpers.h> 12 #include <common/debug.h> 13 #include <lib/pmf/pmf.h> 14 #include <lib/runtime_instr.h> 15 #include <plat/common/platform.h> 16 17 #include "psci_private.h" 18 19 /****************************************************************************** 20 * Construct the psci_power_state to request power OFF at all power levels. 21 ******************************************************************************/ 22 static void psci_set_power_off_state(psci_power_state_t *state_info) 23 { 24 unsigned int lvl; 25 26 for (lvl = PSCI_CPU_PWR_LVL; lvl <= PLAT_MAX_PWR_LVL; lvl++) 27 state_info->pwr_domain_state[lvl] = PLAT_MAX_OFF_STATE; 28 } 29 30 /****************************************************************************** 31 * Top level handler which is called when a cpu wants to power itself down. 32 * It's assumed that along with turning the cpu power domain off, power 33 * domains at higher levels will be turned off as far as possible. It finds 34 * the highest level where a domain has to be powered off by traversing the 35 * node information and then performs generic, architectural, platform setup 36 * and state management required to turn OFF that power domain and domains 37 * below it. e.g. For a cpu that's to be powered OFF, it could mean programming 38 * the power controller whereas for a cluster that's to be powered off, it will 39 * call the platform specific code which will disable coherency at the 40 * interconnect level if the cpu is the last in the cluster and also the 41 * program the power controller. 42 ******************************************************************************/ 43 int psci_do_cpu_off(unsigned int end_pwrlvl) 44 { 45 int rc = PSCI_E_SUCCESS; 46 unsigned int idx = plat_my_core_pos(); 47 psci_power_state_t state_info; 48 unsigned int parent_nodes[PLAT_MAX_PWR_LVL] = {0}; 49 50 /* 51 * This function must only be called on platforms where the 52 * CPU_OFF platform hooks have been implemented. 53 */ 54 assert(psci_plat_pm_ops->pwr_domain_off != NULL); 55 56 /* Construct the psci_power_state for CPU_OFF */ 57 psci_set_power_off_state(&state_info); 58 59 /* 60 * Get the parent nodes here, this is important to do before we 61 * initiate the power down sequence as after that point the core may 62 * have exited coherency and its cache may be disabled, any access to 63 * shared memory after that (such as the parent node lookup in 64 * psci_cpu_pd_nodes) can cause coherency issues on some platforms. 65 */ 66 psci_get_parent_pwr_domain_nodes(idx, end_pwrlvl, parent_nodes); 67 68 /* 69 * This function acquires the lock corresponding to each power 70 * level so that by the time all locks are taken, the system topology 71 * is snapshot and state management can be done safely. 72 */ 73 psci_acquire_pwr_domain_locks(end_pwrlvl, parent_nodes); 74 75 /* 76 * Call the cpu off handler registered by the Secure Payload Dispatcher 77 * to let it do any bookkeeping. Assume that the SPD always reports an 78 * E_DENIED error if SP refuse to power down 79 */ 80 if ((psci_spd_pm != NULL) && (psci_spd_pm->svc_off != NULL)) { 81 rc = psci_spd_pm->svc_off(0); 82 if (rc != 0) 83 goto exit; 84 } 85 86 /* 87 * This function is passed the requested state info and 88 * it returns the negotiated state info for each power level upto 89 * the end level specified. 90 */ 91 psci_do_state_coordination(end_pwrlvl, &state_info); 92 93 #if ENABLE_PSCI_STAT 94 /* Update the last cpu for each level till end_pwrlvl */ 95 psci_stats_update_pwr_down(end_pwrlvl, &state_info); 96 #endif 97 98 #if ENABLE_RUNTIME_INSTRUMENTATION 99 100 /* 101 * Flush cache line so that even if CPU power down happens 102 * the timestamp update is reflected in memory. 103 */ 104 PMF_CAPTURE_TIMESTAMP(rt_instr_svc, 105 RT_INSTR_ENTER_CFLUSH, 106 PMF_CACHE_MAINT); 107 #endif 108 109 /* 110 * Arch. management. Initiate power down sequence. 111 */ 112 psci_do_pwrdown_sequence(psci_find_max_off_lvl(&state_info)); 113 114 #if ENABLE_RUNTIME_INSTRUMENTATION 115 PMF_CAPTURE_TIMESTAMP(rt_instr_svc, 116 RT_INSTR_EXIT_CFLUSH, 117 PMF_NO_CACHE_MAINT); 118 #endif 119 120 /* 121 * Plat. management: Perform platform specific actions to turn this 122 * cpu off e.g. exit cpu coherency, program the power controller etc. 123 */ 124 psci_plat_pm_ops->pwr_domain_off(&state_info); 125 126 #if ENABLE_PSCI_STAT 127 plat_psci_stat_accounting_start(&state_info); 128 #endif 129 130 exit: 131 /* 132 * Release the locks corresponding to each power level in the 133 * reverse order to which they were acquired. 134 */ 135 psci_release_pwr_domain_locks(end_pwrlvl, parent_nodes); 136 137 /* 138 * Check if all actions needed to safely power down this cpu have 139 * successfully completed. 140 */ 141 if (rc == PSCI_E_SUCCESS) { 142 /* 143 * Set the affinity info state to OFF. When caches are disabled, 144 * this writes directly to main memory, so cache maintenance is 145 * required to ensure that later cached reads of aff_info_state 146 * return AFF_STATE_OFF. A dsbish() ensures ordering of the 147 * update to the affinity info state prior to cache line 148 * invalidation. 149 */ 150 psci_flush_cpu_data(psci_svc_cpu_data.aff_info_state); 151 psci_set_aff_info_state(AFF_STATE_OFF); 152 psci_dsbish(); 153 psci_inv_cpu_data(psci_svc_cpu_data.aff_info_state); 154 155 #if ENABLE_RUNTIME_INSTRUMENTATION 156 157 /* 158 * Update the timestamp with cache off. We assume this 159 * timestamp can only be read from the current CPU and the 160 * timestamp cache line will be flushed before return to 161 * normal world on wakeup. 162 */ 163 PMF_CAPTURE_TIMESTAMP(rt_instr_svc, 164 RT_INSTR_ENTER_HW_LOW_PWR, 165 PMF_NO_CACHE_MAINT); 166 #endif 167 168 if (psci_plat_pm_ops->pwr_domain_pwr_down_wfi != NULL) { 169 /* This function must not return */ 170 psci_plat_pm_ops->pwr_domain_pwr_down_wfi(&state_info); 171 } else { 172 /* 173 * Enter a wfi loop which will allow the power 174 * controller to physically power down this cpu. 175 */ 176 psci_power_down_wfi(); 177 } 178 } 179 180 return rc; 181 } 182