1 /* 2 * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch.h> 32 #include <arch_helpers.h> 33 #include <assert.h> 34 #include <debug.h> 35 #include <platform.h> 36 #include <pmf.h> 37 #include <runtime_instr.h> 38 #include <smcc.h> 39 #include <string.h> 40 #include "psci_private.h" 41 42 /******************************************************************************* 43 * PSCI frontend api for servicing SMCs. Described in the PSCI spec. 44 ******************************************************************************/ 45 int psci_cpu_on(u_register_t target_cpu, 46 uintptr_t entrypoint, 47 u_register_t context_id) 48 49 { 50 int rc; 51 entry_point_info_t ep; 52 53 /* Determine if the cpu exists of not */ 54 rc = psci_validate_mpidr(target_cpu); 55 if (rc != PSCI_E_SUCCESS) 56 return PSCI_E_INVALID_PARAMS; 57 58 /* Validate the entry point and get the entry_point_info */ 59 rc = psci_validate_entry_point(&ep, entrypoint, context_id); 60 if (rc != PSCI_E_SUCCESS) 61 return rc; 62 63 /* 64 * To turn this cpu on, specify which power 65 * levels need to be turned on 66 */ 67 return psci_cpu_on_start(target_cpu, &ep); 68 } 69 70 unsigned int psci_version(void) 71 { 72 return PSCI_MAJOR_VER | PSCI_MINOR_VER; 73 } 74 75 int psci_cpu_suspend(unsigned int power_state, 76 uintptr_t entrypoint, 77 u_register_t context_id) 78 { 79 int rc; 80 unsigned int target_pwrlvl, is_power_down_state; 81 entry_point_info_t ep; 82 psci_power_state_t state_info = { {PSCI_LOCAL_STATE_RUN} }; 83 plat_local_state_t cpu_pd_state; 84 85 /* Validate the power_state parameter */ 86 rc = psci_validate_power_state(power_state, &state_info); 87 if (rc != PSCI_E_SUCCESS) { 88 assert(rc == PSCI_E_INVALID_PARAMS); 89 return rc; 90 } 91 92 /* 93 * Get the value of the state type bit from the power state parameter. 94 */ 95 is_power_down_state = psci_get_pstate_type(power_state); 96 97 /* Sanity check the requested suspend levels */ 98 assert(psci_validate_suspend_req(&state_info, is_power_down_state) 99 == PSCI_E_SUCCESS); 100 101 target_pwrlvl = psci_find_target_suspend_lvl(&state_info); 102 if (target_pwrlvl == PSCI_INVALID_PWR_LVL) { 103 ERROR("Invalid target power level for suspend operation\n"); 104 panic(); 105 } 106 107 /* Fast path for CPU standby.*/ 108 if (is_cpu_standby_req(is_power_down_state, target_pwrlvl)) { 109 if (!psci_plat_pm_ops->cpu_standby) 110 return PSCI_E_INVALID_PARAMS; 111 112 /* 113 * Set the state of the CPU power domain to the platform 114 * specific retention state and enter the standby state. 115 */ 116 cpu_pd_state = state_info.pwr_domain_state[PSCI_CPU_PWR_LVL]; 117 psci_set_cpu_local_state(cpu_pd_state); 118 119 #if ENABLE_PSCI_STAT 120 plat_psci_stat_accounting_start(&state_info); 121 #endif 122 123 #if ENABLE_RUNTIME_INSTRUMENTATION 124 PMF_CAPTURE_TIMESTAMP(rt_instr_svc, 125 RT_INSTR_ENTER_HW_LOW_PWR, 126 PMF_NO_CACHE_MAINT); 127 #endif 128 129 psci_plat_pm_ops->cpu_standby(cpu_pd_state); 130 131 /* Upon exit from standby, set the state back to RUN. */ 132 psci_set_cpu_local_state(PSCI_LOCAL_STATE_RUN); 133 134 #if ENABLE_RUNTIME_INSTRUMENTATION 135 PMF_CAPTURE_TIMESTAMP(rt_instr_svc, 136 RT_INSTR_EXIT_HW_LOW_PWR, 137 PMF_NO_CACHE_MAINT); 138 #endif 139 140 #if ENABLE_PSCI_STAT 141 plat_psci_stat_accounting_stop(&state_info); 142 143 /* Update PSCI stats */ 144 psci_stats_update_pwr_up(PSCI_CPU_PWR_LVL, &state_info); 145 #endif 146 147 return PSCI_E_SUCCESS; 148 } 149 150 /* 151 * If a power down state has been requested, we need to verify entry 152 * point and program entry information. 153 */ 154 if (is_power_down_state) { 155 rc = psci_validate_entry_point(&ep, entrypoint, context_id); 156 if (rc != PSCI_E_SUCCESS) 157 return rc; 158 } 159 160 /* 161 * Do what is needed to enter the power down state. Upon success, 162 * enter the final wfi which will power down this CPU. This function 163 * might return if the power down was abandoned for any reason, e.g. 164 * arrival of an interrupt 165 */ 166 psci_cpu_suspend_start(&ep, 167 target_pwrlvl, 168 &state_info, 169 is_power_down_state); 170 171 return PSCI_E_SUCCESS; 172 } 173 174 175 int psci_system_suspend(uintptr_t entrypoint, u_register_t context_id) 176 { 177 int rc; 178 psci_power_state_t state_info; 179 entry_point_info_t ep; 180 181 /* Check if the current CPU is the last ON CPU in the system */ 182 if (!psci_is_last_on_cpu()) 183 return PSCI_E_DENIED; 184 185 /* Validate the entry point and get the entry_point_info */ 186 rc = psci_validate_entry_point(&ep, entrypoint, context_id); 187 if (rc != PSCI_E_SUCCESS) 188 return rc; 189 190 /* Query the psci_power_state for system suspend */ 191 psci_query_sys_suspend_pwrstate(&state_info); 192 193 /* Ensure that the psci_power_state makes sense */ 194 assert(psci_find_target_suspend_lvl(&state_info) == PLAT_MAX_PWR_LVL); 195 assert(psci_validate_suspend_req(&state_info, PSTATE_TYPE_POWERDOWN) 196 == PSCI_E_SUCCESS); 197 assert(is_local_state_off(state_info.pwr_domain_state[PLAT_MAX_PWR_LVL])); 198 199 /* 200 * Do what is needed to enter the system suspend state. This function 201 * might return if the power down was abandoned for any reason, e.g. 202 * arrival of an interrupt 203 */ 204 psci_cpu_suspend_start(&ep, 205 PLAT_MAX_PWR_LVL, 206 &state_info, 207 PSTATE_TYPE_POWERDOWN); 208 209 return PSCI_E_SUCCESS; 210 } 211 212 int psci_cpu_off(void) 213 { 214 int rc; 215 unsigned int target_pwrlvl = PLAT_MAX_PWR_LVL; 216 217 /* 218 * Do what is needed to power off this CPU and possible higher power 219 * levels if it able to do so. Upon success, enter the final wfi 220 * which will power down this CPU. 221 */ 222 rc = psci_do_cpu_off(target_pwrlvl); 223 224 /* 225 * The only error cpu_off can return is E_DENIED. So check if that's 226 * indeed the case. 227 */ 228 assert(rc == PSCI_E_DENIED); 229 230 return rc; 231 } 232 233 int psci_affinity_info(u_register_t target_affinity, 234 unsigned int lowest_affinity_level) 235 { 236 unsigned int target_idx; 237 238 /* We dont support level higher than PSCI_CPU_PWR_LVL */ 239 if (lowest_affinity_level > PSCI_CPU_PWR_LVL) 240 return PSCI_E_INVALID_PARAMS; 241 242 /* Calculate the cpu index of the target */ 243 target_idx = plat_core_pos_by_mpidr(target_affinity); 244 if (target_idx == -1) 245 return PSCI_E_INVALID_PARAMS; 246 247 return psci_get_aff_info_state_by_idx(target_idx); 248 } 249 250 int psci_migrate(u_register_t target_cpu) 251 { 252 int rc; 253 u_register_t resident_cpu_mpidr; 254 255 rc = psci_spd_migrate_info(&resident_cpu_mpidr); 256 if (rc != PSCI_TOS_UP_MIG_CAP) 257 return (rc == PSCI_TOS_NOT_UP_MIG_CAP) ? 258 PSCI_E_DENIED : PSCI_E_NOT_SUPPORTED; 259 260 /* 261 * Migrate should only be invoked on the CPU where 262 * the Secure OS is resident. 263 */ 264 if (resident_cpu_mpidr != read_mpidr_el1()) 265 return PSCI_E_NOT_PRESENT; 266 267 /* Check the validity of the specified target cpu */ 268 rc = psci_validate_mpidr(target_cpu); 269 if (rc != PSCI_E_SUCCESS) 270 return PSCI_E_INVALID_PARAMS; 271 272 assert(psci_spd_pm && psci_spd_pm->svc_migrate); 273 274 rc = psci_spd_pm->svc_migrate(read_mpidr_el1(), target_cpu); 275 assert(rc == PSCI_E_SUCCESS || rc == PSCI_E_INTERN_FAIL); 276 277 return rc; 278 } 279 280 int psci_migrate_info_type(void) 281 { 282 u_register_t resident_cpu_mpidr; 283 284 return psci_spd_migrate_info(&resident_cpu_mpidr); 285 } 286 287 long psci_migrate_info_up_cpu(void) 288 { 289 u_register_t resident_cpu_mpidr; 290 int rc; 291 292 /* 293 * Return value of this depends upon what 294 * psci_spd_migrate_info() returns. 295 */ 296 rc = psci_spd_migrate_info(&resident_cpu_mpidr); 297 if (rc != PSCI_TOS_NOT_UP_MIG_CAP && rc != PSCI_TOS_UP_MIG_CAP) 298 return PSCI_E_INVALID_PARAMS; 299 300 return resident_cpu_mpidr; 301 } 302 303 int psci_node_hw_state(u_register_t target_cpu, 304 unsigned int power_level) 305 { 306 int rc; 307 308 /* Validate target_cpu */ 309 rc = psci_validate_mpidr(target_cpu); 310 if (rc != PSCI_E_SUCCESS) 311 return PSCI_E_INVALID_PARAMS; 312 313 /* Validate power_level against PLAT_MAX_PWR_LVL */ 314 if (power_level > PLAT_MAX_PWR_LVL) 315 return PSCI_E_INVALID_PARAMS; 316 317 /* 318 * Dispatch this call to platform to query power controller, and pass on 319 * to the caller what it returns 320 */ 321 assert(psci_plat_pm_ops->get_node_hw_state); 322 rc = psci_plat_pm_ops->get_node_hw_state(target_cpu, power_level); 323 assert((rc >= HW_ON && rc <= HW_STANDBY) || rc == PSCI_E_NOT_SUPPORTED 324 || rc == PSCI_E_INVALID_PARAMS); 325 return rc; 326 } 327 328 int psci_features(unsigned int psci_fid) 329 { 330 unsigned int local_caps = psci_caps; 331 332 /* Check if it is a 64 bit function */ 333 if (((psci_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_64) 334 local_caps &= PSCI_CAP_64BIT_MASK; 335 336 /* Check for invalid fid */ 337 if (!(is_std_svc_call(psci_fid) && is_valid_fast_smc(psci_fid) 338 && is_psci_fid(psci_fid))) 339 return PSCI_E_NOT_SUPPORTED; 340 341 342 /* Check if the psci fid is supported or not */ 343 if (!(local_caps & define_psci_cap(psci_fid))) 344 return PSCI_E_NOT_SUPPORTED; 345 346 /* Format the feature flags */ 347 if (psci_fid == PSCI_CPU_SUSPEND_AARCH32 || 348 psci_fid == PSCI_CPU_SUSPEND_AARCH64) { 349 /* 350 * The trusted firmware does not support OS Initiated Mode. 351 */ 352 return (FF_PSTATE << FF_PSTATE_SHIFT) | 353 ((!FF_SUPPORTS_OS_INIT_MODE) << FF_MODE_SUPPORT_SHIFT); 354 } 355 356 /* Return 0 for all other fid's */ 357 return PSCI_E_SUCCESS; 358 } 359 360 /******************************************************************************* 361 * PSCI top level handler for servicing SMCs. 362 ******************************************************************************/ 363 u_register_t psci_smc_handler(uint32_t smc_fid, 364 u_register_t x1, 365 u_register_t x2, 366 u_register_t x3, 367 u_register_t x4, 368 void *cookie, 369 void *handle, 370 u_register_t flags) 371 { 372 if (is_caller_secure(flags)) 373 return SMC_UNK; 374 375 /* Check the fid against the capabilities */ 376 if (!(psci_caps & define_psci_cap(smc_fid))) 377 return SMC_UNK; 378 379 if (((smc_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_32) { 380 /* 32-bit PSCI function, clear top parameter bits */ 381 382 x1 = (uint32_t)x1; 383 x2 = (uint32_t)x2; 384 x3 = (uint32_t)x3; 385 386 switch (smc_fid) { 387 case PSCI_VERSION: 388 return psci_version(); 389 390 case PSCI_CPU_OFF: 391 return psci_cpu_off(); 392 393 case PSCI_CPU_SUSPEND_AARCH32: 394 return psci_cpu_suspend(x1, x2, x3); 395 396 case PSCI_CPU_ON_AARCH32: 397 return psci_cpu_on(x1, x2, x3); 398 399 case PSCI_AFFINITY_INFO_AARCH32: 400 return psci_affinity_info(x1, x2); 401 402 case PSCI_MIG_AARCH32: 403 return psci_migrate(x1); 404 405 case PSCI_MIG_INFO_TYPE: 406 return psci_migrate_info_type(); 407 408 case PSCI_MIG_INFO_UP_CPU_AARCH32: 409 return psci_migrate_info_up_cpu(); 410 411 case PSCI_NODE_HW_STATE_AARCH32: 412 return psci_node_hw_state(x1, x2); 413 414 case PSCI_SYSTEM_SUSPEND_AARCH32: 415 return psci_system_suspend(x1, x2); 416 417 case PSCI_SYSTEM_OFF: 418 psci_system_off(); 419 /* We should never return from psci_system_off() */ 420 421 case PSCI_SYSTEM_RESET: 422 psci_system_reset(); 423 /* We should never return from psci_system_reset() */ 424 425 case PSCI_FEATURES: 426 return psci_features(x1); 427 428 #if ENABLE_PSCI_STAT 429 case PSCI_STAT_RESIDENCY_AARCH32: 430 return psci_stat_residency(x1, x2); 431 432 case PSCI_STAT_COUNT_AARCH32: 433 return psci_stat_count(x1, x2); 434 #endif 435 436 default: 437 break; 438 } 439 } else { 440 /* 64-bit PSCI function */ 441 442 switch (smc_fid) { 443 case PSCI_CPU_SUSPEND_AARCH64: 444 return psci_cpu_suspend(x1, x2, x3); 445 446 case PSCI_CPU_ON_AARCH64: 447 return psci_cpu_on(x1, x2, x3); 448 449 case PSCI_AFFINITY_INFO_AARCH64: 450 return psci_affinity_info(x1, x2); 451 452 case PSCI_MIG_AARCH64: 453 return psci_migrate(x1); 454 455 case PSCI_MIG_INFO_UP_CPU_AARCH64: 456 return psci_migrate_info_up_cpu(); 457 458 case PSCI_NODE_HW_STATE_AARCH64: 459 return psci_node_hw_state(x1, x2); 460 461 case PSCI_SYSTEM_SUSPEND_AARCH64: 462 return psci_system_suspend(x1, x2); 463 464 #if ENABLE_PSCI_STAT 465 case PSCI_STAT_RESIDENCY_AARCH64: 466 return psci_stat_residency(x1, x2); 467 468 case PSCI_STAT_COUNT_AARCH64: 469 return psci_stat_count(x1, x2); 470 #endif 471 472 default: 473 break; 474 } 475 } 476 477 WARN("Unimplemented PSCI Call: 0x%x \n", smc_fid); 478 return SMC_UNK; 479 } 480