1 /* 2 * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <assert.h> 10 #include <bl_common.h> 11 #include <context.h> 12 #include <context_mgmt.h> 13 #include <debug.h> 14 #include <platform.h> 15 #include <string.h> 16 #include <utils.h> 17 #include "psci_private.h" 18 19 /* 20 * SPD power management operations, expected to be supplied by the registered 21 * SPD on successful SP initialization 22 */ 23 const spd_pm_ops_t *psci_spd_pm; 24 25 /* 26 * PSCI requested local power state map. This array is used to store the local 27 * power states requested by a CPU for power levels from level 1 to 28 * PLAT_MAX_PWR_LVL. It does not store the requested local power state for power 29 * level 0 (PSCI_CPU_PWR_LVL) as the requested and the target power state for a 30 * CPU are the same. 31 * 32 * During state coordination, the platform is passed an array containing the 33 * local states requested for a particular non cpu power domain by each cpu 34 * within the domain. 35 * 36 * TODO: Dense packing of the requested states will cause cache thrashing 37 * when multiple power domains write to it. If we allocate the requested 38 * states at each power level in a cache-line aligned per-domain memory, 39 * the cache thrashing can be avoided. 40 */ 41 static plat_local_state_t 42 psci_req_local_pwr_states[PLAT_MAX_PWR_LVL][PLATFORM_CORE_COUNT]; 43 44 45 /******************************************************************************* 46 * Arrays that hold the platform's power domain tree information for state 47 * management of power domains. 48 * Each node in the array 'psci_non_cpu_pd_nodes' corresponds to a power domain 49 * which is an ancestor of a CPU power domain. 50 * Each node in the array 'psci_cpu_pd_nodes' corresponds to a cpu power domain 51 ******************************************************************************/ 52 non_cpu_pd_node_t psci_non_cpu_pd_nodes[PSCI_NUM_NON_CPU_PWR_DOMAINS] 53 #if USE_COHERENT_MEM 54 __section("tzfw_coherent_mem") 55 #endif 56 ; 57 58 /* Lock for PSCI state coordination */ 59 DEFINE_PSCI_LOCK(psci_locks[PSCI_NUM_NON_CPU_PWR_DOMAINS]); 60 61 cpu_pd_node_t psci_cpu_pd_nodes[PLATFORM_CORE_COUNT]; 62 63 /******************************************************************************* 64 * Pointer to functions exported by the platform to complete power mgmt. ops 65 ******************************************************************************/ 66 const plat_psci_ops_t *psci_plat_pm_ops; 67 68 /****************************************************************************** 69 * Check that the maximum power level supported by the platform makes sense 70 *****************************************************************************/ 71 CASSERT(PLAT_MAX_PWR_LVL <= PSCI_MAX_PWR_LVL && \ 72 PLAT_MAX_PWR_LVL >= PSCI_CPU_PWR_LVL, \ 73 assert_platform_max_pwrlvl_check); 74 75 /* 76 * The plat_local_state used by the platform is one of these types: RUN, 77 * RETENTION and OFF. The platform can define further sub-states for each type 78 * apart from RUN. This categorization is done to verify the sanity of the 79 * psci_power_state passed by the platform and to print debug information. The 80 * categorization is done on the basis of the following conditions: 81 * 82 * 1. If (plat_local_state == 0) then the category is STATE_TYPE_RUN. 83 * 84 * 2. If (0 < plat_local_state <= PLAT_MAX_RET_STATE), then the category is 85 * STATE_TYPE_RETN. 86 * 87 * 3. If (plat_local_state > PLAT_MAX_RET_STATE), then the category is 88 * STATE_TYPE_OFF. 89 */ 90 typedef enum plat_local_state_type { 91 STATE_TYPE_RUN = 0, 92 STATE_TYPE_RETN, 93 STATE_TYPE_OFF 94 } plat_local_state_type_t; 95 96 /* The macro used to categorize plat_local_state. */ 97 #define find_local_state_type(plat_local_state) \ 98 ((plat_local_state) ? ((plat_local_state > PLAT_MAX_RET_STATE) \ 99 ? STATE_TYPE_OFF : STATE_TYPE_RETN) \ 100 : STATE_TYPE_RUN) 101 102 /****************************************************************************** 103 * Check that the maximum retention level supported by the platform is less 104 * than the maximum off level. 105 *****************************************************************************/ 106 CASSERT(PLAT_MAX_RET_STATE < PLAT_MAX_OFF_STATE, \ 107 assert_platform_max_off_and_retn_state_check); 108 109 /****************************************************************************** 110 * This function ensures that the power state parameter in a CPU_SUSPEND request 111 * is valid. If so, it returns the requested states for each power level. 112 *****************************************************************************/ 113 int psci_validate_power_state(unsigned int power_state, 114 psci_power_state_t *state_info) 115 { 116 /* Check SBZ bits in power state are zero */ 117 if (psci_check_power_state(power_state)) 118 return PSCI_E_INVALID_PARAMS; 119 120 assert(psci_plat_pm_ops->validate_power_state); 121 122 /* Validate the power_state using platform pm_ops */ 123 return psci_plat_pm_ops->validate_power_state(power_state, state_info); 124 } 125 126 /****************************************************************************** 127 * This function retrieves the `psci_power_state_t` for system suspend from 128 * the platform. 129 *****************************************************************************/ 130 void psci_query_sys_suspend_pwrstate(psci_power_state_t *state_info) 131 { 132 /* 133 * Assert that the required pm_ops hook is implemented to ensure that 134 * the capability detected during psci_setup() is valid. 135 */ 136 assert(psci_plat_pm_ops->get_sys_suspend_power_state); 137 138 /* 139 * Query the platform for the power_state required for system suspend 140 */ 141 psci_plat_pm_ops->get_sys_suspend_power_state(state_info); 142 } 143 144 /******************************************************************************* 145 * This function verifies that the all the other cores in the system have been 146 * turned OFF and the current CPU is the last running CPU in the system. 147 * Returns 1 (true) if the current CPU is the last ON CPU or 0 (false) 148 * otherwise. 149 ******************************************************************************/ 150 unsigned int psci_is_last_on_cpu(void) 151 { 152 unsigned int cpu_idx, my_idx = plat_my_core_pos(); 153 154 for (cpu_idx = 0; cpu_idx < PLATFORM_CORE_COUNT; cpu_idx++) { 155 if (cpu_idx == my_idx) { 156 assert(psci_get_aff_info_state() == AFF_STATE_ON); 157 continue; 158 } 159 160 if (psci_get_aff_info_state_by_idx(cpu_idx) != AFF_STATE_OFF) 161 return 0; 162 } 163 164 return 1; 165 } 166 167 /******************************************************************************* 168 * Routine to return the maximum power level to traverse to after a cpu has 169 * been physically powered up. It is expected to be called immediately after 170 * reset from assembler code. 171 ******************************************************************************/ 172 static unsigned int get_power_on_target_pwrlvl(void) 173 { 174 unsigned int pwrlvl; 175 176 /* 177 * Assume that this cpu was suspended and retrieve its target power 178 * level. If it is invalid then it could only have been turned off 179 * earlier. PLAT_MAX_PWR_LVL will be the highest power level a 180 * cpu can be turned off to. 181 */ 182 pwrlvl = psci_get_suspend_pwrlvl(); 183 if (pwrlvl == PSCI_INVALID_PWR_LVL) 184 pwrlvl = PLAT_MAX_PWR_LVL; 185 return pwrlvl; 186 } 187 188 /****************************************************************************** 189 * Helper function to update the requested local power state array. This array 190 * does not store the requested state for the CPU power level. Hence an 191 * assertion is added to prevent us from accessing the wrong index. 192 *****************************************************************************/ 193 static void psci_set_req_local_pwr_state(unsigned int pwrlvl, 194 unsigned int cpu_idx, 195 plat_local_state_t req_pwr_state) 196 { 197 assert(pwrlvl > PSCI_CPU_PWR_LVL); 198 psci_req_local_pwr_states[pwrlvl - 1][cpu_idx] = req_pwr_state; 199 } 200 201 /****************************************************************************** 202 * This function initializes the psci_req_local_pwr_states. 203 *****************************************************************************/ 204 void psci_init_req_local_pwr_states(void) 205 { 206 /* Initialize the requested state of all non CPU power domains as OFF */ 207 memset(&psci_req_local_pwr_states, PLAT_MAX_OFF_STATE, 208 sizeof(psci_req_local_pwr_states)); 209 } 210 211 /****************************************************************************** 212 * Helper function to return a reference to an array containing the local power 213 * states requested by each cpu for a power domain at 'pwrlvl'. The size of the 214 * array will be the number of cpu power domains of which this power domain is 215 * an ancestor. These requested states will be used to determine a suitable 216 * target state for this power domain during psci state coordination. An 217 * assertion is added to prevent us from accessing the CPU power level. 218 *****************************************************************************/ 219 static plat_local_state_t *psci_get_req_local_pwr_states(unsigned int pwrlvl, 220 unsigned int cpu_idx) 221 { 222 assert(pwrlvl > PSCI_CPU_PWR_LVL); 223 224 return &psci_req_local_pwr_states[pwrlvl - 1][cpu_idx]; 225 } 226 227 /* 228 * psci_non_cpu_pd_nodes can be placed either in normal memory or coherent 229 * memory. 230 * 231 * With !USE_COHERENT_MEM, psci_non_cpu_pd_nodes is placed in normal memory, 232 * it's accessed by both cached and non-cached participants. To serve the common 233 * minimum, perform a cache flush before read and after write so that non-cached 234 * participants operate on latest data in main memory. 235 * 236 * When USE_COHERENT_MEM is used, psci_non_cpu_pd_nodes is placed in coherent 237 * memory. With HW_ASSISTED_COHERENCY, all PSCI participants are cache-coherent. 238 * In both cases, no cache operations are required. 239 */ 240 241 /* 242 * Retrieve local state of non-CPU power domain node from a non-cached CPU, 243 * after any required cache maintenance operation. 244 */ 245 static plat_local_state_t get_non_cpu_pd_node_local_state( 246 unsigned int parent_idx) 247 { 248 #if !USE_COHERENT_MEM || !HW_ASSISTED_COHERENCY 249 flush_dcache_range( 250 (uintptr_t) &psci_non_cpu_pd_nodes[parent_idx], 251 sizeof(psci_non_cpu_pd_nodes[parent_idx])); 252 #endif 253 return psci_non_cpu_pd_nodes[parent_idx].local_state; 254 } 255 256 /* 257 * Update local state of non-CPU power domain node from a cached CPU; perform 258 * any required cache maintenance operation afterwards. 259 */ 260 static void set_non_cpu_pd_node_local_state(unsigned int parent_idx, 261 plat_local_state_t state) 262 { 263 psci_non_cpu_pd_nodes[parent_idx].local_state = state; 264 #if !USE_COHERENT_MEM || !HW_ASSISTED_COHERENCY 265 flush_dcache_range( 266 (uintptr_t) &psci_non_cpu_pd_nodes[parent_idx], 267 sizeof(psci_non_cpu_pd_nodes[parent_idx])); 268 #endif 269 } 270 271 /****************************************************************************** 272 * Helper function to return the current local power state of each power domain 273 * from the current cpu power domain to its ancestor at the 'end_pwrlvl'. This 274 * function will be called after a cpu is powered on to find the local state 275 * each power domain has emerged from. 276 *****************************************************************************/ 277 void psci_get_target_local_pwr_states(unsigned int end_pwrlvl, 278 psci_power_state_t *target_state) 279 { 280 unsigned int parent_idx, lvl; 281 plat_local_state_t *pd_state = target_state->pwr_domain_state; 282 283 pd_state[PSCI_CPU_PWR_LVL] = psci_get_cpu_local_state(); 284 parent_idx = psci_cpu_pd_nodes[plat_my_core_pos()].parent_node; 285 286 /* Copy the local power state from node to state_info */ 287 for (lvl = PSCI_CPU_PWR_LVL + 1; lvl <= end_pwrlvl; lvl++) { 288 pd_state[lvl] = get_non_cpu_pd_node_local_state(parent_idx); 289 parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node; 290 } 291 292 /* Set the the higher levels to RUN */ 293 for (; lvl <= PLAT_MAX_PWR_LVL; lvl++) 294 target_state->pwr_domain_state[lvl] = PSCI_LOCAL_STATE_RUN; 295 } 296 297 /****************************************************************************** 298 * Helper function to set the target local power state that each power domain 299 * from the current cpu power domain to its ancestor at the 'end_pwrlvl' will 300 * enter. This function will be called after coordination of requested power 301 * states has been done for each power level. 302 *****************************************************************************/ 303 static void psci_set_target_local_pwr_states(unsigned int end_pwrlvl, 304 const psci_power_state_t *target_state) 305 { 306 unsigned int parent_idx, lvl; 307 const plat_local_state_t *pd_state = target_state->pwr_domain_state; 308 309 psci_set_cpu_local_state(pd_state[PSCI_CPU_PWR_LVL]); 310 311 /* 312 * Need to flush as local_state might be accessed with Data Cache 313 * disabled during power on 314 */ 315 psci_flush_cpu_data(psci_svc_cpu_data.local_state); 316 317 parent_idx = psci_cpu_pd_nodes[plat_my_core_pos()].parent_node; 318 319 /* Copy the local_state from state_info */ 320 for (lvl = 1; lvl <= end_pwrlvl; lvl++) { 321 set_non_cpu_pd_node_local_state(parent_idx, pd_state[lvl]); 322 parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node; 323 } 324 } 325 326 327 /******************************************************************************* 328 * PSCI helper function to get the parent nodes corresponding to a cpu_index. 329 ******************************************************************************/ 330 void psci_get_parent_pwr_domain_nodes(unsigned int cpu_idx, 331 unsigned int end_lvl, 332 unsigned int node_index[]) 333 { 334 unsigned int parent_node = psci_cpu_pd_nodes[cpu_idx].parent_node; 335 unsigned int i; 336 337 for (i = PSCI_CPU_PWR_LVL + 1; i <= end_lvl; i++) { 338 *node_index++ = parent_node; 339 parent_node = psci_non_cpu_pd_nodes[parent_node].parent_node; 340 } 341 } 342 343 /****************************************************************************** 344 * This function is invoked post CPU power up and initialization. It sets the 345 * affinity info state, target power state and requested power state for the 346 * current CPU and all its ancestor power domains to RUN. 347 *****************************************************************************/ 348 void psci_set_pwr_domains_to_run(unsigned int end_pwrlvl) 349 { 350 unsigned int parent_idx, cpu_idx = plat_my_core_pos(), lvl; 351 parent_idx = psci_cpu_pd_nodes[cpu_idx].parent_node; 352 353 /* Reset the local_state to RUN for the non cpu power domains. */ 354 for (lvl = PSCI_CPU_PWR_LVL + 1; lvl <= end_pwrlvl; lvl++) { 355 set_non_cpu_pd_node_local_state(parent_idx, 356 PSCI_LOCAL_STATE_RUN); 357 psci_set_req_local_pwr_state(lvl, 358 cpu_idx, 359 PSCI_LOCAL_STATE_RUN); 360 parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node; 361 } 362 363 /* Set the affinity info state to ON */ 364 psci_set_aff_info_state(AFF_STATE_ON); 365 366 psci_set_cpu_local_state(PSCI_LOCAL_STATE_RUN); 367 psci_flush_cpu_data(psci_svc_cpu_data); 368 } 369 370 /****************************************************************************** 371 * This function is passed the local power states requested for each power 372 * domain (state_info) between the current CPU domain and its ancestors until 373 * the target power level (end_pwrlvl). It updates the array of requested power 374 * states with this information. 375 * 376 * Then, for each level (apart from the CPU level) until the 'end_pwrlvl', it 377 * retrieves the states requested by all the cpus of which the power domain at 378 * that level is an ancestor. It passes this information to the platform to 379 * coordinate and return the target power state. If the target state for a level 380 * is RUN then subsequent levels are not considered. At the CPU level, state 381 * coordination is not required. Hence, the requested and the target states are 382 * the same. 383 * 384 * The 'state_info' is updated with the target state for each level between the 385 * CPU and the 'end_pwrlvl' and returned to the caller. 386 * 387 * This function will only be invoked with data cache enabled and while 388 * powering down a core. 389 *****************************************************************************/ 390 void psci_do_state_coordination(unsigned int end_pwrlvl, 391 psci_power_state_t *state_info) 392 { 393 unsigned int lvl, parent_idx, cpu_idx = plat_my_core_pos(); 394 unsigned int start_idx, ncpus; 395 plat_local_state_t target_state, *req_states; 396 397 assert(end_pwrlvl <= PLAT_MAX_PWR_LVL); 398 parent_idx = psci_cpu_pd_nodes[cpu_idx].parent_node; 399 400 /* For level 0, the requested state will be equivalent 401 to target state */ 402 for (lvl = PSCI_CPU_PWR_LVL + 1; lvl <= end_pwrlvl; lvl++) { 403 404 /* First update the requested power state */ 405 psci_set_req_local_pwr_state(lvl, cpu_idx, 406 state_info->pwr_domain_state[lvl]); 407 408 /* Get the requested power states for this power level */ 409 start_idx = psci_non_cpu_pd_nodes[parent_idx].cpu_start_idx; 410 req_states = psci_get_req_local_pwr_states(lvl, start_idx); 411 412 /* 413 * Let the platform coordinate amongst the requested states at 414 * this power level and return the target local power state. 415 */ 416 ncpus = psci_non_cpu_pd_nodes[parent_idx].ncpus; 417 target_state = plat_get_target_pwr_state(lvl, 418 req_states, 419 ncpus); 420 421 state_info->pwr_domain_state[lvl] = target_state; 422 423 /* Break early if the negotiated target power state is RUN */ 424 if (is_local_state_run(state_info->pwr_domain_state[lvl])) 425 break; 426 427 parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node; 428 } 429 430 /* 431 * This is for cases when we break out of the above loop early because 432 * the target power state is RUN at a power level < end_pwlvl. 433 * We update the requested power state from state_info and then 434 * set the target state as RUN. 435 */ 436 for (lvl = lvl + 1; lvl <= end_pwrlvl; lvl++) { 437 psci_set_req_local_pwr_state(lvl, cpu_idx, 438 state_info->pwr_domain_state[lvl]); 439 state_info->pwr_domain_state[lvl] = PSCI_LOCAL_STATE_RUN; 440 441 } 442 443 /* Update the target state in the power domain nodes */ 444 psci_set_target_local_pwr_states(end_pwrlvl, state_info); 445 } 446 447 /****************************************************************************** 448 * This function validates a suspend request by making sure that if a standby 449 * state is requested then no power level is turned off and the highest power 450 * level is placed in a standby/retention state. 451 * 452 * It also ensures that the state level X will enter is not shallower than the 453 * state level X + 1 will enter. 454 * 455 * This validation will be enabled only for DEBUG builds as the platform is 456 * expected to perform these validations as well. 457 *****************************************************************************/ 458 int psci_validate_suspend_req(const psci_power_state_t *state_info, 459 unsigned int is_power_down_state) 460 { 461 unsigned int max_off_lvl, target_lvl, max_retn_lvl; 462 plat_local_state_t state; 463 plat_local_state_type_t req_state_type, deepest_state_type; 464 int i; 465 466 /* Find the target suspend power level */ 467 target_lvl = psci_find_target_suspend_lvl(state_info); 468 if (target_lvl == PSCI_INVALID_PWR_LVL) 469 return PSCI_E_INVALID_PARAMS; 470 471 /* All power domain levels are in a RUN state to begin with */ 472 deepest_state_type = STATE_TYPE_RUN; 473 474 for (i = target_lvl; i >= PSCI_CPU_PWR_LVL; i--) { 475 state = state_info->pwr_domain_state[i]; 476 req_state_type = find_local_state_type(state); 477 478 /* 479 * While traversing from the highest power level to the lowest, 480 * the state requested for lower levels has to be the same or 481 * deeper i.e. equal to or greater than the state at the higher 482 * levels. If this condition is true, then the requested state 483 * becomes the deepest state encountered so far. 484 */ 485 if (req_state_type < deepest_state_type) 486 return PSCI_E_INVALID_PARAMS; 487 deepest_state_type = req_state_type; 488 } 489 490 /* Find the highest off power level */ 491 max_off_lvl = psci_find_max_off_lvl(state_info); 492 493 /* The target_lvl is either equal to the max_off_lvl or max_retn_lvl */ 494 max_retn_lvl = PSCI_INVALID_PWR_LVL; 495 if (target_lvl != max_off_lvl) 496 max_retn_lvl = target_lvl; 497 498 /* 499 * If this is not a request for a power down state then max off level 500 * has to be invalid and max retention level has to be a valid power 501 * level. 502 */ 503 if (!is_power_down_state && (max_off_lvl != PSCI_INVALID_PWR_LVL || 504 max_retn_lvl == PSCI_INVALID_PWR_LVL)) 505 return PSCI_E_INVALID_PARAMS; 506 507 return PSCI_E_SUCCESS; 508 } 509 510 /****************************************************************************** 511 * This function finds the highest power level which will be powered down 512 * amongst all the power levels specified in the 'state_info' structure 513 *****************************************************************************/ 514 unsigned int psci_find_max_off_lvl(const psci_power_state_t *state_info) 515 { 516 int i; 517 518 for (i = PLAT_MAX_PWR_LVL; i >= PSCI_CPU_PWR_LVL; i--) { 519 if (is_local_state_off(state_info->pwr_domain_state[i])) 520 return i; 521 } 522 523 return PSCI_INVALID_PWR_LVL; 524 } 525 526 /****************************************************************************** 527 * This functions finds the level of the highest power domain which will be 528 * placed in a low power state during a suspend operation. 529 *****************************************************************************/ 530 unsigned int psci_find_target_suspend_lvl(const psci_power_state_t *state_info) 531 { 532 int i; 533 534 for (i = PLAT_MAX_PWR_LVL; i >= PSCI_CPU_PWR_LVL; i--) { 535 if (!is_local_state_run(state_info->pwr_domain_state[i])) 536 return i; 537 } 538 539 return PSCI_INVALID_PWR_LVL; 540 } 541 542 /******************************************************************************* 543 * This function is passed a cpu_index and the highest level in the topology 544 * tree that the operation should be applied to. It picks up locks in order of 545 * increasing power domain level in the range specified. 546 ******************************************************************************/ 547 void psci_acquire_pwr_domain_locks(unsigned int end_pwrlvl, 548 unsigned int cpu_idx) 549 { 550 unsigned int parent_idx = psci_cpu_pd_nodes[cpu_idx].parent_node; 551 unsigned int level; 552 553 /* No locking required for level 0. Hence start locking from level 1 */ 554 for (level = PSCI_CPU_PWR_LVL + 1; level <= end_pwrlvl; level++) { 555 psci_lock_get(&psci_non_cpu_pd_nodes[parent_idx]); 556 parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node; 557 } 558 } 559 560 /******************************************************************************* 561 * This function is passed a cpu_index and the highest level in the topology 562 * tree that the operation should be applied to. It releases the locks in order 563 * of decreasing power domain level in the range specified. 564 ******************************************************************************/ 565 void psci_release_pwr_domain_locks(unsigned int end_pwrlvl, 566 unsigned int cpu_idx) 567 { 568 unsigned int parent_idx, parent_nodes[PLAT_MAX_PWR_LVL] = {0}; 569 int level; 570 571 /* Get the parent nodes */ 572 psci_get_parent_pwr_domain_nodes(cpu_idx, end_pwrlvl, parent_nodes); 573 574 /* Unlock top down. No unlocking required for level 0. */ 575 for (level = end_pwrlvl; level >= PSCI_CPU_PWR_LVL + 1; level--) { 576 parent_idx = parent_nodes[level - 1]; 577 psci_lock_release(&psci_non_cpu_pd_nodes[parent_idx]); 578 } 579 } 580 581 /******************************************************************************* 582 * Simple routine to determine whether a mpidr is valid or not. 583 ******************************************************************************/ 584 int psci_validate_mpidr(u_register_t mpidr) 585 { 586 if (plat_core_pos_by_mpidr(mpidr) < 0) 587 return PSCI_E_INVALID_PARAMS; 588 589 return PSCI_E_SUCCESS; 590 } 591 592 /******************************************************************************* 593 * This function determines the full entrypoint information for the requested 594 * PSCI entrypoint on power on/resume and returns it. 595 ******************************************************************************/ 596 #ifdef AARCH32 597 static int psci_get_ns_ep_info(entry_point_info_t *ep, 598 uintptr_t entrypoint, 599 u_register_t context_id) 600 { 601 u_register_t ep_attr; 602 unsigned int aif, ee, mode; 603 u_register_t scr = read_scr(); 604 u_register_t ns_sctlr, sctlr; 605 606 /* Switch to non secure state */ 607 write_scr(scr | SCR_NS_BIT); 608 isb(); 609 ns_sctlr = read_sctlr(); 610 611 sctlr = scr & SCR_HCE_BIT ? read_hsctlr() : ns_sctlr; 612 613 /* Return to original state */ 614 write_scr(scr); 615 isb(); 616 ee = 0; 617 618 ep_attr = NON_SECURE | EP_ST_DISABLE; 619 if (sctlr & SCTLR_EE_BIT) { 620 ep_attr |= EP_EE_BIG; 621 ee = 1; 622 } 623 SET_PARAM_HEAD(ep, PARAM_EP, VERSION_1, ep_attr); 624 625 ep->pc = entrypoint; 626 zeromem(&ep->args, sizeof(ep->args)); 627 ep->args.arg0 = context_id; 628 629 mode = scr & SCR_HCE_BIT ? MODE32_hyp : MODE32_svc; 630 631 /* 632 * TODO: Choose async. exception bits if HYP mode is not 633 * implemented according to the values of SCR.{AW, FW} bits 634 */ 635 aif = SPSR_ABT_BIT | SPSR_IRQ_BIT | SPSR_FIQ_BIT; 636 637 ep->spsr = SPSR_MODE32(mode, entrypoint & 0x1, ee, aif); 638 639 return PSCI_E_SUCCESS; 640 } 641 642 #else 643 static int psci_get_ns_ep_info(entry_point_info_t *ep, 644 uintptr_t entrypoint, 645 u_register_t context_id) 646 { 647 u_register_t ep_attr, sctlr; 648 unsigned int daif, ee, mode; 649 u_register_t ns_scr_el3 = read_scr_el3(); 650 u_register_t ns_sctlr_el1 = read_sctlr_el1(); 651 652 sctlr = ns_scr_el3 & SCR_HCE_BIT ? read_sctlr_el2() : ns_sctlr_el1; 653 ee = 0; 654 655 ep_attr = NON_SECURE | EP_ST_DISABLE; 656 if (sctlr & SCTLR_EE_BIT) { 657 ep_attr |= EP_EE_BIG; 658 ee = 1; 659 } 660 SET_PARAM_HEAD(ep, PARAM_EP, VERSION_1, ep_attr); 661 662 ep->pc = entrypoint; 663 zeromem(&ep->args, sizeof(ep->args)); 664 ep->args.arg0 = context_id; 665 666 /* 667 * Figure out whether the cpu enters the non-secure address space 668 * in aarch32 or aarch64 669 */ 670 if (ns_scr_el3 & SCR_RW_BIT) { 671 672 /* 673 * Check whether a Thumb entry point has been provided for an 674 * aarch64 EL 675 */ 676 if (entrypoint & 0x1) 677 return PSCI_E_INVALID_ADDRESS; 678 679 mode = ns_scr_el3 & SCR_HCE_BIT ? MODE_EL2 : MODE_EL1; 680 681 ep->spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 682 } else { 683 684 mode = ns_scr_el3 & SCR_HCE_BIT ? MODE32_hyp : MODE32_svc; 685 686 /* 687 * TODO: Choose async. exception bits if HYP mode is not 688 * implemented according to the values of SCR.{AW, FW} bits 689 */ 690 daif = DAIF_ABT_BIT | DAIF_IRQ_BIT | DAIF_FIQ_BIT; 691 692 ep->spsr = SPSR_MODE32(mode, entrypoint & 0x1, ee, daif); 693 } 694 695 return PSCI_E_SUCCESS; 696 } 697 #endif 698 699 /******************************************************************************* 700 * This function validates the entrypoint with the platform layer if the 701 * appropriate pm_ops hook is exported by the platform and returns the 702 * 'entry_point_info'. 703 ******************************************************************************/ 704 int psci_validate_entry_point(entry_point_info_t *ep, 705 uintptr_t entrypoint, 706 u_register_t context_id) 707 { 708 int rc; 709 710 /* Validate the entrypoint using platform psci_ops */ 711 if (psci_plat_pm_ops->validate_ns_entrypoint) { 712 rc = psci_plat_pm_ops->validate_ns_entrypoint(entrypoint); 713 if (rc != PSCI_E_SUCCESS) 714 return PSCI_E_INVALID_ADDRESS; 715 } 716 717 /* 718 * Verify and derive the re-entry information for 719 * the non-secure world from the non-secure state from 720 * where this call originated. 721 */ 722 rc = psci_get_ns_ep_info(ep, entrypoint, context_id); 723 return rc; 724 } 725 726 /******************************************************************************* 727 * Generic handler which is called when a cpu is physically powered on. It 728 * traverses the node information and finds the highest power level powered 729 * off and performs generic, architectural, platform setup and state management 730 * to power on that power level and power levels below it. 731 * e.g. For a cpu that's been powered on, it will call the platform specific 732 * code to enable the gic cpu interface and for a cluster it will enable 733 * coherency at the interconnect level in addition to gic cpu interface. 734 ******************************************************************************/ 735 void psci_warmboot_entrypoint(void) 736 { 737 unsigned int end_pwrlvl, cpu_idx = plat_my_core_pos(); 738 psci_power_state_t state_info = { {PSCI_LOCAL_STATE_RUN} }; 739 740 /* 741 * Verify that we have been explicitly turned ON or resumed from 742 * suspend. 743 */ 744 if (psci_get_aff_info_state() == AFF_STATE_OFF) { 745 ERROR("Unexpected affinity info state"); 746 panic(); 747 } 748 749 /* 750 * Get the maximum power domain level to traverse to after this cpu 751 * has been physically powered up. 752 */ 753 end_pwrlvl = get_power_on_target_pwrlvl(); 754 755 /* 756 * This function acquires the lock corresponding to each power level so 757 * that by the time all locks are taken, the system topology is snapshot 758 * and state management can be done safely. 759 */ 760 psci_acquire_pwr_domain_locks(end_pwrlvl, 761 cpu_idx); 762 763 #if ENABLE_PSCI_STAT 764 plat_psci_stat_accounting_stop(&state_info); 765 #endif 766 767 psci_get_target_local_pwr_states(end_pwrlvl, &state_info); 768 769 /* 770 * This CPU could be resuming from suspend or it could have just been 771 * turned on. To distinguish between these 2 cases, we examine the 772 * affinity state of the CPU: 773 * - If the affinity state is ON_PENDING then it has just been 774 * turned on. 775 * - Else it is resuming from suspend. 776 * 777 * Depending on the type of warm reset identified, choose the right set 778 * of power management handler and perform the generic, architecture 779 * and platform specific handling. 780 */ 781 if (psci_get_aff_info_state() == AFF_STATE_ON_PENDING) 782 psci_cpu_on_finish(cpu_idx, &state_info); 783 else 784 psci_cpu_suspend_finish(cpu_idx, &state_info); 785 786 /* 787 * Set the requested and target state of this CPU and all the higher 788 * power domains which are ancestors of this CPU to run. 789 */ 790 psci_set_pwr_domains_to_run(end_pwrlvl); 791 792 #if ENABLE_PSCI_STAT 793 /* 794 * Update PSCI stats. 795 * Caches are off when writing stats data on the power down path. 796 * Since caches are now enabled, it's necessary to do cache 797 * maintenance before reading that same data. 798 */ 799 psci_stats_update_pwr_up(end_pwrlvl, &state_info); 800 #endif 801 802 /* 803 * This loop releases the lock corresponding to each power level 804 * in the reverse order to which they were acquired. 805 */ 806 psci_release_pwr_domain_locks(end_pwrlvl, 807 cpu_idx); 808 } 809 810 /******************************************************************************* 811 * This function initializes the set of hooks that PSCI invokes as part of power 812 * management operation. The power management hooks are expected to be provided 813 * by the SPD, after it finishes all its initialization 814 ******************************************************************************/ 815 void psci_register_spd_pm_hook(const spd_pm_ops_t *pm) 816 { 817 assert(pm); 818 psci_spd_pm = pm; 819 820 if (pm->svc_migrate) 821 psci_caps |= define_psci_cap(PSCI_MIG_AARCH64); 822 823 if (pm->svc_migrate_info) 824 psci_caps |= define_psci_cap(PSCI_MIG_INFO_UP_CPU_AARCH64) 825 | define_psci_cap(PSCI_MIG_INFO_TYPE); 826 } 827 828 /******************************************************************************* 829 * This function invokes the migrate info hook in the spd_pm_ops. It performs 830 * the necessary return value validation. If the Secure Payload is UP and 831 * migrate capable, it returns the mpidr of the CPU on which the Secure payload 832 * is resident through the mpidr parameter. Else the value of the parameter on 833 * return is undefined. 834 ******************************************************************************/ 835 int psci_spd_migrate_info(u_register_t *mpidr) 836 { 837 int rc; 838 839 if (!psci_spd_pm || !psci_spd_pm->svc_migrate_info) 840 return PSCI_E_NOT_SUPPORTED; 841 842 rc = psci_spd_pm->svc_migrate_info(mpidr); 843 844 assert(rc == PSCI_TOS_UP_MIG_CAP || rc == PSCI_TOS_NOT_UP_MIG_CAP \ 845 || rc == PSCI_TOS_NOT_PRESENT_MP || rc == PSCI_E_NOT_SUPPORTED); 846 847 return rc; 848 } 849 850 851 /******************************************************************************* 852 * This function prints the state of all power domains present in the 853 * system 854 ******************************************************************************/ 855 void psci_print_power_domain_map(void) 856 { 857 #if LOG_LEVEL >= LOG_LEVEL_INFO 858 unsigned int idx; 859 plat_local_state_t state; 860 plat_local_state_type_t state_type; 861 862 /* This array maps to the PSCI_STATE_X definitions in psci.h */ 863 static const char * const psci_state_type_str[] = { 864 "ON", 865 "RETENTION", 866 "OFF", 867 }; 868 869 INFO("PSCI Power Domain Map:\n"); 870 for (idx = 0; idx < (PSCI_NUM_PWR_DOMAINS - PLATFORM_CORE_COUNT); 871 idx++) { 872 state_type = find_local_state_type( 873 psci_non_cpu_pd_nodes[idx].local_state); 874 INFO(" Domain Node : Level %u, parent_node %d," 875 " State %s (0x%x)\n", 876 psci_non_cpu_pd_nodes[idx].level, 877 psci_non_cpu_pd_nodes[idx].parent_node, 878 psci_state_type_str[state_type], 879 psci_non_cpu_pd_nodes[idx].local_state); 880 } 881 882 for (idx = 0; idx < PLATFORM_CORE_COUNT; idx++) { 883 state = psci_get_cpu_local_state_by_idx(idx); 884 state_type = find_local_state_type(state); 885 INFO(" CPU Node : MPID 0x%llx, parent_node %d," 886 " State %s (0x%x)\n", 887 (unsigned long long)psci_cpu_pd_nodes[idx].mpidr, 888 psci_cpu_pd_nodes[idx].parent_node, 889 psci_state_type_str[state_type], 890 psci_get_cpu_local_state_by_idx(idx)); 891 } 892 #endif 893 } 894 895 /****************************************************************************** 896 * Return whether any secondaries were powered up with CPU_ON call. A CPU that 897 * have ever been powered up would have set its MPDIR value to something other 898 * than PSCI_INVALID_MPIDR. Note that MPDIR isn't reset back to 899 * PSCI_INVALID_MPIDR when a CPU is powered down later, so the return value is 900 * meaningful only when called on the primary CPU during early boot. 901 *****************************************************************************/ 902 int psci_secondaries_brought_up(void) 903 { 904 unsigned int idx, n_valid = 0; 905 906 for (idx = 0; idx < ARRAY_SIZE(psci_cpu_pd_nodes); idx++) { 907 if (psci_cpu_pd_nodes[idx].mpidr != PSCI_INVALID_MPIDR) 908 n_valid++; 909 } 910 911 assert(n_valid); 912 913 return (n_valid > 1); 914 } 915 916 #if ENABLE_PLAT_COMPAT 917 /******************************************************************************* 918 * PSCI Compatibility helper function to return the 'power_state' parameter of 919 * the PSCI CPU SUSPEND request for the current CPU. Returns PSCI_INVALID_DATA 920 * if not invoked within CPU_SUSPEND for the current CPU. 921 ******************************************************************************/ 922 int psci_get_suspend_powerstate(void) 923 { 924 /* Sanity check to verify that CPU is within CPU_SUSPEND */ 925 if (psci_get_aff_info_state() == AFF_STATE_ON && 926 !is_local_state_run(psci_get_cpu_local_state())) 927 return psci_power_state_compat[plat_my_core_pos()]; 928 929 return PSCI_INVALID_DATA; 930 } 931 932 /******************************************************************************* 933 * PSCI Compatibility helper function to return the state id of the current 934 * cpu encoded in the 'power_state' parameter. Returns PSCI_INVALID_DATA 935 * if not invoked within CPU_SUSPEND for the current CPU. 936 ******************************************************************************/ 937 int psci_get_suspend_stateid(void) 938 { 939 unsigned int power_state; 940 power_state = psci_get_suspend_powerstate(); 941 if (power_state != PSCI_INVALID_DATA) 942 return psci_get_pstate_id(power_state); 943 944 return PSCI_INVALID_DATA; 945 } 946 947 /******************************************************************************* 948 * PSCI Compatibility helper function to return the state id encoded in the 949 * 'power_state' parameter of the CPU specified by 'mpidr'. Returns 950 * PSCI_INVALID_DATA if the CPU is not in CPU_SUSPEND. 951 ******************************************************************************/ 952 int psci_get_suspend_stateid_by_mpidr(unsigned long mpidr) 953 { 954 int cpu_idx = plat_core_pos_by_mpidr(mpidr); 955 956 if (cpu_idx == -1) 957 return PSCI_INVALID_DATA; 958 959 /* Sanity check to verify that the CPU is in CPU_SUSPEND */ 960 if (psci_get_aff_info_state_by_idx(cpu_idx) == AFF_STATE_ON && 961 !is_local_state_run(psci_get_cpu_local_state_by_idx(cpu_idx))) 962 return psci_get_pstate_id(psci_power_state_compat[cpu_idx]); 963 964 return PSCI_INVALID_DATA; 965 } 966 967 /******************************************************************************* 968 * This function returns highest affinity level which is in OFF 969 * state. The affinity instance with which the level is associated is 970 * determined by the caller. 971 ******************************************************************************/ 972 unsigned int psci_get_max_phys_off_afflvl(void) 973 { 974 psci_power_state_t state_info; 975 976 zeromem(&state_info, sizeof(state_info)); 977 psci_get_target_local_pwr_states(PLAT_MAX_PWR_LVL, &state_info); 978 979 return psci_find_target_suspend_lvl(&state_info); 980 } 981 982 /******************************************************************************* 983 * PSCI Compatibility helper function to return target affinity level requested 984 * for the CPU_SUSPEND. This function assumes affinity levels correspond to 985 * power domain levels on the platform. 986 ******************************************************************************/ 987 int psci_get_suspend_afflvl(void) 988 { 989 return psci_get_suspend_pwrlvl(); 990 } 991 992 #endif 993 994 /******************************************************************************* 995 * Initiate power down sequence, by calling power down operations registered for 996 * this CPU. 997 ******************************************************************************/ 998 void psci_do_pwrdown_sequence(unsigned int power_level) 999 { 1000 #if HW_ASSISTED_COHERENCY 1001 /* 1002 * With hardware-assisted coherency, the CPU drivers only initiate the 1003 * power down sequence, without performing cache-maintenance operations 1004 * in software. Data caches and MMU remain enabled both before and after 1005 * this call. 1006 */ 1007 prepare_cpu_pwr_dwn(power_level); 1008 #else 1009 /* 1010 * Without hardware-assisted coherency, the CPU drivers disable data 1011 * caches and MMU, then perform cache-maintenance operations in 1012 * software. 1013 * 1014 * We ought to call prepare_cpu_pwr_dwn() to initiate power down 1015 * sequence. We currently have data caches and MMU enabled, but the 1016 * function will return with data caches and MMU disabled. We must 1017 * ensure that the stack memory is flushed out to memory before we start 1018 * popping from it again. 1019 */ 1020 psci_do_pwrdown_cache_maintenance(power_level); 1021 #endif 1022 } 1023