1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <bakery_lock.h> 10 #include <cpu_data.h> 11 #include <platform.h> 12 #include <string.h> 13 #include <utils_def.h> 14 15 /* 16 * Functions in this file implement Bakery Algorithm for mutual exclusion with the 17 * bakery lock data structures in cacheable and Normal memory. 18 * 19 * ARM architecture offers a family of exclusive access instructions to 20 * efficiently implement mutual exclusion with hardware support. However, as 21 * well as depending on external hardware, these instructions have defined 22 * behavior only on certain memory types (cacheable and Normal memory in 23 * particular; see ARMv8 Architecture Reference Manual section B2.10). Use cases 24 * in trusted firmware are such that mutual exclusion implementation cannot 25 * expect that accesses to the lock have the specific type required by the 26 * architecture for these primitives to function (for example, not all 27 * contenders may have address translation enabled). 28 * 29 * This implementation does not use mutual exclusion primitives. It expects 30 * memory regions where the locks reside to be cacheable and Normal. 31 * 32 * Note that the ARM architecture guarantees single-copy atomicity for aligned 33 * accesses regardless of status of address translation. 34 */ 35 36 #ifdef PLAT_PERCPU_BAKERY_LOCK_SIZE 37 /* 38 * Verify that the platform defined value for the per-cpu space for bakery locks is 39 * a multiple of the cache line size, to prevent multiple CPUs writing to the same 40 * bakery lock cache line 41 * 42 * Using this value, if provided, rather than the linker generated value results in 43 * more efficient code 44 */ 45 CASSERT((PLAT_PERCPU_BAKERY_LOCK_SIZE & (CACHE_WRITEBACK_GRANULE - 1)) == 0, \ 46 PLAT_PERCPU_BAKERY_LOCK_SIZE_not_cacheline_multiple); 47 #define PERCPU_BAKERY_LOCK_SIZE (PLAT_PERCPU_BAKERY_LOCK_SIZE) 48 #else 49 /* 50 * Use the linker defined symbol which has evaluated the size reqiurement. 51 * This is not as efficient as using a platform defined constant 52 */ 53 IMPORT_SYM(uintptr_t, __PERCPU_BAKERY_LOCK_SIZE__, PERCPU_BAKERY_LOCK_SIZE); 54 #endif 55 56 static inline bakery_lock_t *get_bakery_info(unsigned int cpu_ix, 57 bakery_lock_t *lock) 58 { 59 return (bakery_info_t *)((uintptr_t)lock + 60 cpu_ix * PERCPU_BAKERY_LOCK_SIZE); 61 } 62 63 static inline void write_cache_op(uintptr_t addr, bool cached) 64 { 65 if (cached) 66 dccvac(addr); 67 else 68 dcivac(addr); 69 70 dsbish(); 71 } 72 73 static inline void read_cache_op(uintptr_t addr, bool cached) 74 { 75 if (cached) 76 dccivac(addr); 77 } 78 79 /* Helper function to check if the lock is acquired */ 80 static inline bool is_lock_acquired(const bakery_info_t *my_bakery_info, 81 int is_cached) 82 { 83 /* 84 * Even though lock data is updated only by the owning cpu and 85 * appropriate cache maintenance operations are performed, 86 * if the previous update was done when the cpu was not participating 87 * in coherency, then there is a chance that cache maintenance 88 * operations were not propagated to all the caches in the system. 89 * Hence do a `read_cache_op()` prior to read. 90 */ 91 read_cache_op((uintptr_t)my_bakery_info, is_cached); 92 return bakery_ticket_number(my_bakery_info->lock_data) != 0U; 93 } 94 95 static unsigned int bakery_get_ticket(bakery_lock_t *lock, 96 unsigned int me, int is_cached) 97 { 98 unsigned int my_ticket, their_ticket; 99 unsigned int they; 100 bakery_info_t *my_bakery_info, *their_bakery_info; 101 102 /* 103 * Obtain a reference to the bakery information for this cpu and ensure 104 * it is not NULL. 105 */ 106 my_bakery_info = get_bakery_info(me, lock); 107 assert(my_bakery_info != NULL); 108 109 /* Prevent recursive acquisition.*/ 110 assert(!is_lock_acquired(my_bakery_info, is_cached)); 111 112 /* 113 * Tell other contenders that we are through the bakery doorway i.e. 114 * going to allocate a ticket for this cpu. 115 */ 116 my_ticket = 0U; 117 my_bakery_info->lock_data = make_bakery_data(CHOOSING_TICKET, my_ticket); 118 119 write_cache_op((uintptr_t)my_bakery_info, is_cached); 120 121 /* 122 * Iterate through the bakery information of each contender to allocate 123 * the highest ticket number for this cpu. 124 */ 125 for (they = 0U; they < BAKERY_LOCK_MAX_CPUS; they++) { 126 if (me == they) 127 continue; 128 129 /* 130 * Get a reference to the other contender's bakery info and 131 * ensure that a stale copy is not read. 132 */ 133 their_bakery_info = get_bakery_info(they, lock); 134 assert(their_bakery_info != NULL); 135 136 read_cache_op((uintptr_t)their_bakery_info, is_cached); 137 138 /* 139 * Update this cpu's ticket number if a higher ticket number is 140 * seen 141 */ 142 their_ticket = bakery_ticket_number(their_bakery_info->lock_data); 143 if (their_ticket > my_ticket) 144 my_ticket = their_ticket; 145 } 146 147 /* 148 * Compute ticket; then signal to other contenders waiting for us to 149 * finish calculating our ticket value that we're done 150 */ 151 ++my_ticket; 152 my_bakery_info->lock_data = make_bakery_data(CHOSEN_TICKET, my_ticket); 153 154 write_cache_op((uintptr_t)my_bakery_info, is_cached); 155 156 return my_ticket; 157 } 158 159 void bakery_lock_get(bakery_lock_t *lock) 160 { 161 unsigned int they, me, is_cached; 162 unsigned int my_ticket, my_prio, their_ticket; 163 bakery_info_t *their_bakery_info; 164 unsigned int their_bakery_data; 165 166 me = plat_my_core_pos(); 167 #ifdef AARCH32 168 is_cached = read_sctlr() & SCTLR_C_BIT; 169 #else 170 is_cached = read_sctlr_el3() & SCTLR_C_BIT; 171 #endif 172 173 /* Get a ticket */ 174 my_ticket = bakery_get_ticket(lock, me, is_cached); 175 176 /* 177 * Now that we got our ticket, compute our priority value, then compare 178 * with that of others, and proceed to acquire the lock 179 */ 180 my_prio = bakery_get_priority(my_ticket, me); 181 for (they = 0U; they < BAKERY_LOCK_MAX_CPUS; they++) { 182 if (me == they) 183 continue; 184 185 /* 186 * Get a reference to the other contender's bakery info and 187 * ensure that a stale copy is not read. 188 */ 189 their_bakery_info = get_bakery_info(they, lock); 190 assert(their_bakery_info != NULL); 191 192 /* Wait for the contender to get their ticket */ 193 do { 194 read_cache_op((uintptr_t)their_bakery_info, is_cached); 195 their_bakery_data = their_bakery_info->lock_data; 196 } while (bakery_is_choosing(their_bakery_data)); 197 198 /* 199 * If the other party is a contender, they'll have non-zero 200 * (valid) ticket value. If they do, compare priorities 201 */ 202 their_ticket = bakery_ticket_number(their_bakery_data); 203 if (their_ticket && (bakery_get_priority(their_ticket, they) < my_prio)) { 204 /* 205 * They have higher priority (lower value). Wait for 206 * their ticket value to change (either release the lock 207 * to have it dropped to 0; or drop and probably content 208 * again for the same lock to have an even higher value) 209 */ 210 do { 211 wfe(); 212 read_cache_op((uintptr_t)their_bakery_info, is_cached); 213 } while (their_ticket 214 == bakery_ticket_number(their_bakery_info->lock_data)); 215 } 216 } 217 218 /* 219 * Lock acquired. Ensure that any reads from a shared resource in the 220 * critical section read values after the lock is acquired. 221 */ 222 dmbld(); 223 } 224 225 void bakery_lock_release(bakery_lock_t *lock) 226 { 227 bakery_info_t *my_bakery_info; 228 #ifdef AARCH32 229 unsigned int is_cached = read_sctlr() & SCTLR_C_BIT; 230 #else 231 unsigned int is_cached = read_sctlr_el3() & SCTLR_C_BIT; 232 #endif 233 234 my_bakery_info = get_bakery_info(plat_my_core_pos(), lock); 235 236 assert(is_lock_acquired(my_bakery_info, is_cached)); 237 238 /* 239 * Ensure that other observers see any stores in the critical section 240 * before releasing the lock. Release the lock by resetting ticket. 241 * Then signal other waiting contenders. 242 */ 243 dmbst(); 244 my_bakery_info->lock_data = 0U; 245 write_cache_op((uintptr_t)my_bakery_info, is_cached); 246 sev(); 247 } 248