1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <string.h> 9 10 #include <arch_helpers.h> 11 #include <lib/bakery_lock.h> 12 #include <lib/el3_runtime/cpu_data.h> 13 #include <lib/utils_def.h> 14 #include <plat/common/platform.h> 15 16 /* 17 * Functions in this file implement Bakery Algorithm for mutual exclusion with the 18 * bakery lock data structures in cacheable and Normal memory. 19 * 20 * ARM architecture offers a family of exclusive access instructions to 21 * efficiently implement mutual exclusion with hardware support. However, as 22 * well as depending on external hardware, these instructions have defined 23 * behavior only on certain memory types (cacheable and Normal memory in 24 * particular; see ARMv8 Architecture Reference Manual section B2.10). Use cases 25 * in trusted firmware are such that mutual exclusion implementation cannot 26 * expect that accesses to the lock have the specific type required by the 27 * architecture for these primitives to function (for example, not all 28 * contenders may have address translation enabled). 29 * 30 * This implementation does not use mutual exclusion primitives. It expects 31 * memory regions where the locks reside to be cacheable and Normal. 32 * 33 * Note that the ARM architecture guarantees single-copy atomicity for aligned 34 * accesses regardless of status of address translation. 35 */ 36 37 #ifdef PLAT_PERCPU_BAKERY_LOCK_SIZE 38 /* 39 * Verify that the platform defined value for the per-cpu space for bakery locks is 40 * a multiple of the cache line size, to prevent multiple CPUs writing to the same 41 * bakery lock cache line 42 * 43 * Using this value, if provided, rather than the linker generated value results in 44 * more efficient code 45 */ 46 CASSERT((PLAT_PERCPU_BAKERY_LOCK_SIZE & (CACHE_WRITEBACK_GRANULE - 1)) == 0, \ 47 PLAT_PERCPU_BAKERY_LOCK_SIZE_not_cacheline_multiple); 48 #define PERCPU_BAKERY_LOCK_SIZE (PLAT_PERCPU_BAKERY_LOCK_SIZE) 49 #else 50 /* 51 * Use the linker defined symbol which has evaluated the size reqiurement. 52 * This is not as efficient as using a platform defined constant 53 */ 54 IMPORT_SYM(uintptr_t, __PERCPU_BAKERY_LOCK_START__, BAKERY_LOCK_START); 55 IMPORT_SYM(uintptr_t, __PERCPU_BAKERY_LOCK_END__, BAKERY_LOCK_END); 56 #define PERCPU_BAKERY_LOCK_SIZE (BAKERY_LOCK_END - BAKERY_LOCK_START) 57 #endif 58 59 static inline bakery_lock_t *get_bakery_info(unsigned int cpu_ix, 60 bakery_lock_t *lock) 61 { 62 return (bakery_info_t *)((uintptr_t)lock + 63 cpu_ix * PERCPU_BAKERY_LOCK_SIZE); 64 } 65 66 static inline void write_cache_op(uintptr_t addr, bool cached) 67 { 68 if (cached) 69 dccvac(addr); 70 else 71 dcivac(addr); 72 73 dsbish(); 74 } 75 76 static inline void read_cache_op(uintptr_t addr, bool cached) 77 { 78 if (cached) 79 dccivac(addr); 80 } 81 82 /* Helper function to check if the lock is acquired */ 83 static inline bool is_lock_acquired(const bakery_info_t *my_bakery_info, 84 int is_cached) 85 { 86 /* 87 * Even though lock data is updated only by the owning cpu and 88 * appropriate cache maintenance operations are performed, 89 * if the previous update was done when the cpu was not participating 90 * in coherency, then there is a chance that cache maintenance 91 * operations were not propagated to all the caches in the system. 92 * Hence do a `read_cache_op()` prior to read. 93 */ 94 read_cache_op((uintptr_t)my_bakery_info, is_cached); 95 return bakery_ticket_number(my_bakery_info->lock_data) != 0U; 96 } 97 98 static unsigned int bakery_get_ticket(bakery_lock_t *lock, 99 unsigned int me, int is_cached) 100 { 101 unsigned int my_ticket, their_ticket; 102 unsigned int they; 103 bakery_info_t *my_bakery_info, *their_bakery_info; 104 105 /* 106 * Obtain a reference to the bakery information for this cpu and ensure 107 * it is not NULL. 108 */ 109 my_bakery_info = get_bakery_info(me, lock); 110 assert(my_bakery_info != NULL); 111 112 /* Prevent recursive acquisition.*/ 113 assert(!is_lock_acquired(my_bakery_info, is_cached)); 114 115 /* 116 * Tell other contenders that we are through the bakery doorway i.e. 117 * going to allocate a ticket for this cpu. 118 */ 119 my_ticket = 0U; 120 my_bakery_info->lock_data = make_bakery_data(CHOOSING_TICKET, my_ticket); 121 122 write_cache_op((uintptr_t)my_bakery_info, is_cached); 123 124 /* 125 * Iterate through the bakery information of each contender to allocate 126 * the highest ticket number for this cpu. 127 */ 128 for (they = 0U; they < BAKERY_LOCK_MAX_CPUS; they++) { 129 if (me == they) 130 continue; 131 132 /* 133 * Get a reference to the other contender's bakery info and 134 * ensure that a stale copy is not read. 135 */ 136 their_bakery_info = get_bakery_info(they, lock); 137 assert(their_bakery_info != NULL); 138 139 read_cache_op((uintptr_t)their_bakery_info, is_cached); 140 141 /* 142 * Update this cpu's ticket number if a higher ticket number is 143 * seen 144 */ 145 their_ticket = bakery_ticket_number(their_bakery_info->lock_data); 146 if (their_ticket > my_ticket) 147 my_ticket = their_ticket; 148 } 149 150 /* 151 * Compute ticket; then signal to other contenders waiting for us to 152 * finish calculating our ticket value that we're done 153 */ 154 ++my_ticket; 155 my_bakery_info->lock_data = make_bakery_data(CHOSEN_TICKET, my_ticket); 156 157 write_cache_op((uintptr_t)my_bakery_info, is_cached); 158 159 return my_ticket; 160 } 161 162 void bakery_lock_get(bakery_lock_t *lock) 163 { 164 unsigned int they, me, is_cached; 165 unsigned int my_ticket, my_prio, their_ticket; 166 bakery_info_t *their_bakery_info; 167 unsigned int their_bakery_data; 168 169 me = plat_my_core_pos(); 170 #ifdef __aarch64__ 171 is_cached = read_sctlr_el3() & SCTLR_C_BIT; 172 #else 173 is_cached = read_sctlr() & SCTLR_C_BIT; 174 #endif 175 176 /* Get a ticket */ 177 my_ticket = bakery_get_ticket(lock, me, is_cached); 178 179 /* 180 * Now that we got our ticket, compute our priority value, then compare 181 * with that of others, and proceed to acquire the lock 182 */ 183 my_prio = bakery_get_priority(my_ticket, me); 184 for (they = 0U; they < BAKERY_LOCK_MAX_CPUS; they++) { 185 if (me == they) 186 continue; 187 188 /* 189 * Get a reference to the other contender's bakery info and 190 * ensure that a stale copy is not read. 191 */ 192 their_bakery_info = get_bakery_info(they, lock); 193 assert(their_bakery_info != NULL); 194 195 /* Wait for the contender to get their ticket */ 196 do { 197 read_cache_op((uintptr_t)their_bakery_info, is_cached); 198 their_bakery_data = their_bakery_info->lock_data; 199 } while (bakery_is_choosing(their_bakery_data)); 200 201 /* 202 * If the other party is a contender, they'll have non-zero 203 * (valid) ticket value. If they do, compare priorities 204 */ 205 their_ticket = bakery_ticket_number(their_bakery_data); 206 if (their_ticket && (bakery_get_priority(their_ticket, they) < my_prio)) { 207 /* 208 * They have higher priority (lower value). Wait for 209 * their ticket value to change (either release the lock 210 * to have it dropped to 0; or drop and probably content 211 * again for the same lock to have an even higher value) 212 */ 213 do { 214 wfe(); 215 read_cache_op((uintptr_t)their_bakery_info, is_cached); 216 } while (their_ticket 217 == bakery_ticket_number(their_bakery_info->lock_data)); 218 } 219 } 220 221 /* 222 * Lock acquired. Ensure that any reads and writes from a shared 223 * resource in the critical section read/write values after the lock is 224 * acquired. 225 */ 226 dmbish(); 227 } 228 229 void bakery_lock_release(bakery_lock_t *lock) 230 { 231 bakery_info_t *my_bakery_info; 232 #ifdef __aarch64__ 233 unsigned int is_cached = read_sctlr_el3() & SCTLR_C_BIT; 234 #else 235 unsigned int is_cached = read_sctlr() & SCTLR_C_BIT; 236 #endif 237 238 my_bakery_info = get_bakery_info(plat_my_core_pos(), lock); 239 240 assert(is_lock_acquired(my_bakery_info, is_cached)); 241 242 /* 243 * Ensure that other observers see any stores in the critical section 244 * before releasing the lock. Also ensure all loads in the critical 245 * section are complete before releasing the lock. Release the lock by 246 * resetting ticket. Then signal other waiting contenders. 247 */ 248 dmbish(); 249 my_bakery_info->lock_data = 0U; 250 write_cache_op((uintptr_t)my_bakery_info, is_cached); 251 252 /* This sev is ordered by the dsbish in write_cahce_op */ 253 sev(); 254 } 255