1 /* 2 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <string.h> 10 11 #include <arch_helpers.h> 12 #include <lib/bakery_lock.h> 13 #include <lib/el3_runtime/cpu_data.h> 14 #include <lib/utils_def.h> 15 #include <plat/common/platform.h> 16 17 /* 18 * Functions in this file implement Bakery Algorithm for mutual exclusion with the 19 * bakery lock data structures in cacheable and Normal memory. 20 * 21 * ARM architecture offers a family of exclusive access instructions to 22 * efficiently implement mutual exclusion with hardware support. However, as 23 * well as depending on external hardware, these instructions have defined 24 * behavior only on certain memory types (cacheable and Normal memory in 25 * particular; see ARMv8 Architecture Reference Manual section B2.10). Use cases 26 * in trusted firmware are such that mutual exclusion implementation cannot 27 * expect that accesses to the lock have the specific type required by the 28 * architecture for these primitives to function (for example, not all 29 * contenders may have address translation enabled). 30 * 31 * This implementation does not use mutual exclusion primitives. It expects 32 * memory regions where the locks reside to be cacheable and Normal. 33 * 34 * Note that the ARM architecture guarantees single-copy atomicity for aligned 35 * accesses regardless of status of address translation. 36 */ 37 38 #ifdef PLAT_PERCPU_BAKERY_LOCK_SIZE 39 /* 40 * Verify that the platform defined value for the per-cpu space for bakery locks is 41 * a multiple of the cache line size, to prevent multiple CPUs writing to the same 42 * bakery lock cache line 43 * 44 * Using this value, if provided, rather than the linker generated value results in 45 * more efficient code 46 */ 47 CASSERT((PLAT_PERCPU_BAKERY_LOCK_SIZE & (CACHE_WRITEBACK_GRANULE - 1)) == 0, 48 PLAT_PERCPU_BAKERY_LOCK_SIZE_not_cacheline_multiple); 49 #define PERCPU_BAKERY_LOCK_SIZE (PLAT_PERCPU_BAKERY_LOCK_SIZE) 50 #else 51 /* 52 * Use the linker defined symbol which has evaluated the size reqiurement. 53 * This is not as efficient as using a platform defined constant 54 */ 55 IMPORT_SYM(uintptr_t, __PERCPU_BAKERY_LOCK_START__, BAKERY_LOCK_START); 56 IMPORT_SYM(uintptr_t, __PERCPU_BAKERY_LOCK_END__, BAKERY_LOCK_END); 57 #define PERCPU_BAKERY_LOCK_SIZE (BAKERY_LOCK_END - BAKERY_LOCK_START) 58 #endif 59 60 static inline bakery_lock_t *get_bakery_info(unsigned int cpu_ix, 61 bakery_lock_t *lock) 62 { 63 return (bakery_info_t *)((uintptr_t)lock + 64 cpu_ix * PERCPU_BAKERY_LOCK_SIZE); 65 } 66 67 static inline void write_cache_op(uintptr_t addr, bool cached) 68 { 69 if (cached) 70 dccvac(addr); 71 else 72 dcivac(addr); 73 74 dsbish(); 75 } 76 77 static inline void read_cache_op(uintptr_t addr, bool cached) 78 { 79 if (cached) 80 dccivac(addr); 81 82 dmbish(); 83 } 84 85 /* Helper function to check if the lock is acquired */ 86 static inline __unused bool is_lock_acquired(const bakery_info_t *my_bakery_info, 87 bool is_cached) 88 { 89 /* 90 * Even though lock data is updated only by the owning cpu and 91 * appropriate cache maintenance operations are performed, 92 * if the previous update was done when the cpu was not participating 93 * in coherency, then there is a chance that cache maintenance 94 * operations were not propagated to all the caches in the system. 95 * Hence do a `read_cache_op()` prior to read. 96 */ 97 read_cache_op((uintptr_t)my_bakery_info, is_cached); 98 return bakery_ticket_number(my_bakery_info->lock_data) != 0U; 99 } 100 101 static unsigned int bakery_get_ticket(bakery_lock_t *lock, 102 unsigned int me, bool is_cached) 103 { 104 unsigned int my_ticket, their_ticket; 105 unsigned int they; 106 bakery_info_t *my_bakery_info, *their_bakery_info; 107 108 /* 109 * Obtain a reference to the bakery information for this cpu and ensure 110 * it is not NULL. 111 */ 112 my_bakery_info = get_bakery_info(me, lock); 113 assert(my_bakery_info != NULL); 114 115 /* Prevent recursive acquisition.*/ 116 assert(!is_lock_acquired(my_bakery_info, is_cached)); 117 118 /* 119 * Tell other contenders that we are through the bakery doorway i.e. 120 * going to allocate a ticket for this cpu. 121 */ 122 my_ticket = 0U; 123 my_bakery_info->lock_data = make_bakery_data(CHOOSING_TICKET, my_ticket); 124 125 write_cache_op((uintptr_t)my_bakery_info, is_cached); 126 127 /* 128 * Iterate through the bakery information of each contender to allocate 129 * the highest ticket number for this cpu. 130 */ 131 for (they = 0U; they < BAKERY_LOCK_MAX_CPUS; they++) { 132 if (me == they) 133 continue; 134 135 /* 136 * Get a reference to the other contender's bakery info and 137 * ensure that a stale copy is not read. 138 */ 139 their_bakery_info = get_bakery_info(they, lock); 140 assert(their_bakery_info != NULL); 141 142 read_cache_op((uintptr_t)their_bakery_info, is_cached); 143 144 /* 145 * Update this cpu's ticket number if a higher ticket number is 146 * seen 147 */ 148 their_ticket = bakery_ticket_number(their_bakery_info->lock_data); 149 if (their_ticket > my_ticket) 150 my_ticket = their_ticket; 151 } 152 153 /* 154 * Compute ticket; then signal to other contenders waiting for us to 155 * finish calculating our ticket value that we're done 156 */ 157 ++my_ticket; 158 my_bakery_info->lock_data = make_bakery_data(CHOSEN_TICKET, my_ticket); 159 160 write_cache_op((uintptr_t)my_bakery_info, is_cached); 161 162 return my_ticket; 163 } 164 165 void bakery_lock_get(bakery_lock_t *lock) 166 { 167 unsigned int they, me; 168 unsigned int my_ticket, my_prio, their_ticket; 169 bakery_info_t *their_bakery_info; 170 unsigned int their_bakery_data; 171 bool is_cached; 172 173 me = plat_my_core_pos(); 174 is_cached = is_dcache_enabled(); 175 176 /* Get a ticket */ 177 my_ticket = bakery_get_ticket(lock, me, is_cached); 178 179 /* 180 * Now that we got our ticket, compute our priority value, then compare 181 * with that of others, and proceed to acquire the lock 182 */ 183 my_prio = bakery_get_priority(my_ticket, me); 184 for (they = 0U; they < BAKERY_LOCK_MAX_CPUS; they++) { 185 if (me == they) 186 continue; 187 188 /* 189 * Get a reference to the other contender's bakery info and 190 * ensure that a stale copy is not read. 191 */ 192 their_bakery_info = get_bakery_info(they, lock); 193 assert(their_bakery_info != NULL); 194 195 /* Wait for the contender to get their ticket */ 196 do { 197 read_cache_op((uintptr_t)their_bakery_info, is_cached); 198 their_bakery_data = their_bakery_info->lock_data; 199 } while (bakery_is_choosing(their_bakery_data)); 200 201 /* 202 * If the other party is a contender, they'll have non-zero 203 * (valid) ticket value. If they do, compare priorities 204 */ 205 their_ticket = bakery_ticket_number(their_bakery_data); 206 if (their_ticket && (bakery_get_priority(their_ticket, they) < my_prio)) { 207 /* 208 * They have higher priority (lower value). Wait for 209 * their ticket value to change (either release the lock 210 * to have it dropped to 0; or drop and probably content 211 * again for the same lock to have an even higher value) 212 */ 213 do { 214 wfe(); 215 read_cache_op((uintptr_t)their_bakery_info, is_cached); 216 } while (their_ticket 217 == bakery_ticket_number(their_bakery_info->lock_data)); 218 } 219 } 220 221 /* 222 * Lock acquired. Ensure that any reads and writes from a shared 223 * resource in the critical section read/write values after the lock is 224 * acquired. 225 */ 226 dmbish(); 227 } 228 229 void bakery_lock_release(bakery_lock_t *lock) 230 { 231 bakery_info_t *my_bakery_info; 232 bool is_cached = is_dcache_enabled(); 233 234 my_bakery_info = get_bakery_info(plat_my_core_pos(), lock); 235 236 assert(is_lock_acquired(my_bakery_info, is_cached)); 237 238 /* 239 * Ensure that other observers see any stores in the critical section 240 * before releasing the lock. Also ensure all loads in the critical 241 * section are complete before releasing the lock. Release the lock by 242 * resetting ticket. Then signal other waiting contenders. 243 */ 244 dmbish(); 245 my_bakery_info->lock_data = 0U; 246 write_cache_op((uintptr_t)my_bakery_info, is_cached); 247 248 /* This sev is ordered by the dsbish in write_cahce_op */ 249 sev(); 250 } 251