18c5fe0b5SSoby Mathew /* 28c5fe0b5SSoby Mathew * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 38c5fe0b5SSoby Mathew * 48c5fe0b5SSoby Mathew * Redistribution and use in source and binary forms, with or without 58c5fe0b5SSoby Mathew * modification, are permitted provided that the following conditions are met: 68c5fe0b5SSoby Mathew * 78c5fe0b5SSoby Mathew * Redistributions of source code must retain the above copyright notice, this 88c5fe0b5SSoby Mathew * list of conditions and the following disclaimer. 98c5fe0b5SSoby Mathew * 108c5fe0b5SSoby Mathew * Redistributions in binary form must reproduce the above copyright notice, 118c5fe0b5SSoby Mathew * this list of conditions and the following disclaimer in the documentation 128c5fe0b5SSoby Mathew * and/or other materials provided with the distribution. 138c5fe0b5SSoby Mathew * 148c5fe0b5SSoby Mathew * Neither the name of ARM nor the names of its contributors may be used 158c5fe0b5SSoby Mathew * to endorse or promote products derived from this software without specific 168c5fe0b5SSoby Mathew * prior written permission. 178c5fe0b5SSoby Mathew * 188c5fe0b5SSoby Mathew * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 198c5fe0b5SSoby Mathew * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 208c5fe0b5SSoby Mathew * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 218c5fe0b5SSoby Mathew * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 228c5fe0b5SSoby Mathew * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 238c5fe0b5SSoby Mathew * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 248c5fe0b5SSoby Mathew * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 258c5fe0b5SSoby Mathew * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 268c5fe0b5SSoby Mathew * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 278c5fe0b5SSoby Mathew * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 288c5fe0b5SSoby Mathew * POSSIBILITY OF SUCH DAMAGE. 298c5fe0b5SSoby Mathew */ 308c5fe0b5SSoby Mathew 318c5fe0b5SSoby Mathew #include <arch_helpers.h> 328c5fe0b5SSoby Mathew #include <assert.h> 338c5fe0b5SSoby Mathew #include <bakery_lock.h> 348c5fe0b5SSoby Mathew #include <cpu_data.h> 358c5fe0b5SSoby Mathew #include <platform.h> 368c5fe0b5SSoby Mathew #include <string.h> 378c5fe0b5SSoby Mathew 388c5fe0b5SSoby Mathew /* 398c5fe0b5SSoby Mathew * Functions in this file implement Bakery Algorithm for mutual exclusion with the 408c5fe0b5SSoby Mathew * bakery lock data structures in cacheable and Normal memory. 418c5fe0b5SSoby Mathew * 428c5fe0b5SSoby Mathew * ARM architecture offers a family of exclusive access instructions to 438c5fe0b5SSoby Mathew * efficiently implement mutual exclusion with hardware support. However, as 448c5fe0b5SSoby Mathew * well as depending on external hardware, these instructions have defined 458c5fe0b5SSoby Mathew * behavior only on certain memory types (cacheable and Normal memory in 468c5fe0b5SSoby Mathew * particular; see ARMv8 Architecture Reference Manual section B2.10). Use cases 478c5fe0b5SSoby Mathew * in trusted firmware are such that mutual exclusion implementation cannot 488c5fe0b5SSoby Mathew * expect that accesses to the lock have the specific type required by the 498c5fe0b5SSoby Mathew * architecture for these primitives to function (for example, not all 508c5fe0b5SSoby Mathew * contenders may have address translation enabled). 518c5fe0b5SSoby Mathew * 528c5fe0b5SSoby Mathew * This implementation does not use mutual exclusion primitives. It expects 538c5fe0b5SSoby Mathew * memory regions where the locks reside to be cacheable and Normal. 548c5fe0b5SSoby Mathew * 558c5fe0b5SSoby Mathew * Note that the ARM architecture guarantees single-copy atomicity for aligned 568c5fe0b5SSoby Mathew * accesses regardless of status of address translation. 578c5fe0b5SSoby Mathew */ 588c5fe0b5SSoby Mathew 598c5fe0b5SSoby Mathew /* This macro assumes that the bakery_info array is located at the offset specified */ 608c5fe0b5SSoby Mathew #define get_my_bakery_info(offset, id) \ 618c5fe0b5SSoby Mathew (((bakery_info_t *) (((uint8_t *)_cpu_data()) + offset)) + id) 628c5fe0b5SSoby Mathew 638c5fe0b5SSoby Mathew #define get_bakery_info_by_index(offset, id, ix) \ 648c5fe0b5SSoby Mathew (((bakery_info_t *) (((uint8_t *)_cpu_data_by_index(ix)) + offset)) + id) 658c5fe0b5SSoby Mathew 668c5fe0b5SSoby Mathew #define write_cache_op(addr, cached) \ 678c5fe0b5SSoby Mathew do { \ 688c5fe0b5SSoby Mathew (cached ? dccvac((uint64_t)addr) :\ 698c5fe0b5SSoby Mathew dcivac((uint64_t)addr));\ 708c5fe0b5SSoby Mathew dsbish();\ 718c5fe0b5SSoby Mathew } while (0) 728c5fe0b5SSoby Mathew 738c5fe0b5SSoby Mathew #define read_cache_op(addr, cached) if (cached) \ 748c5fe0b5SSoby Mathew dccivac((uint64_t)addr) 758c5fe0b5SSoby Mathew 768c5fe0b5SSoby Mathew static unsigned int bakery_get_ticket(int id, unsigned int offset, 778c5fe0b5SSoby Mathew unsigned int me, int is_cached) 788c5fe0b5SSoby Mathew { 798c5fe0b5SSoby Mathew unsigned int my_ticket, their_ticket; 808c5fe0b5SSoby Mathew unsigned int they; 818c5fe0b5SSoby Mathew bakery_info_t *my_bakery_info, *their_bakery_info; 828c5fe0b5SSoby Mathew 838c5fe0b5SSoby Mathew /* 848c5fe0b5SSoby Mathew * Obtain a reference to the bakery information for this cpu and ensure 858c5fe0b5SSoby Mathew * it is not NULL. 868c5fe0b5SSoby Mathew */ 878c5fe0b5SSoby Mathew my_bakery_info = get_my_bakery_info(offset, id); 888c5fe0b5SSoby Mathew assert(my_bakery_info); 898c5fe0b5SSoby Mathew 908c5fe0b5SSoby Mathew /* 91*548579f5SSoby Mathew * Prevent recursive acquisition. 92*548579f5SSoby Mathew * Since lock data is written to and cleaned by the owning cpu, it 93*548579f5SSoby Mathew * doesn't require any cache operations prior to reading the lock data. 94*548579f5SSoby Mathew */ 95*548579f5SSoby Mathew assert(!bakery_ticket_number(my_bakery_info->lock_data)); 96*548579f5SSoby Mathew 97*548579f5SSoby Mathew /* 988c5fe0b5SSoby Mathew * Tell other contenders that we are through the bakery doorway i.e. 998c5fe0b5SSoby Mathew * going to allocate a ticket for this cpu. 1008c5fe0b5SSoby Mathew */ 1018c5fe0b5SSoby Mathew my_ticket = 0; 1028c5fe0b5SSoby Mathew my_bakery_info->lock_data = make_bakery_data(CHOOSING_TICKET, my_ticket); 1038c5fe0b5SSoby Mathew 1048c5fe0b5SSoby Mathew write_cache_op(my_bakery_info, is_cached); 1058c5fe0b5SSoby Mathew 1068c5fe0b5SSoby Mathew /* 1078c5fe0b5SSoby Mathew * Iterate through the bakery information of each contender to allocate 1088c5fe0b5SSoby Mathew * the highest ticket number for this cpu. 1098c5fe0b5SSoby Mathew */ 1108c5fe0b5SSoby Mathew for (they = 0; they < BAKERY_LOCK_MAX_CPUS; they++) { 1118c5fe0b5SSoby Mathew if (me == they) 1128c5fe0b5SSoby Mathew continue; 1138c5fe0b5SSoby Mathew 1148c5fe0b5SSoby Mathew /* 1158c5fe0b5SSoby Mathew * Get a reference to the other contender's bakery info and 1168c5fe0b5SSoby Mathew * ensure that a stale copy is not read. 1178c5fe0b5SSoby Mathew */ 1188c5fe0b5SSoby Mathew their_bakery_info = get_bakery_info_by_index(offset, id, they); 1198c5fe0b5SSoby Mathew assert(their_bakery_info); 1208c5fe0b5SSoby Mathew 1218c5fe0b5SSoby Mathew read_cache_op(their_bakery_info, is_cached); 1228c5fe0b5SSoby Mathew 1238c5fe0b5SSoby Mathew /* 1248c5fe0b5SSoby Mathew * Update this cpu's ticket number if a higher ticket number is 1258c5fe0b5SSoby Mathew * seen 1268c5fe0b5SSoby Mathew */ 1278c5fe0b5SSoby Mathew their_ticket = bakery_ticket_number(their_bakery_info->lock_data); 1288c5fe0b5SSoby Mathew if (their_ticket > my_ticket) 1298c5fe0b5SSoby Mathew my_ticket = their_ticket; 1308c5fe0b5SSoby Mathew } 1318c5fe0b5SSoby Mathew 1328c5fe0b5SSoby Mathew /* 1338c5fe0b5SSoby Mathew * Compute ticket; then signal to other contenders waiting for us to 1348c5fe0b5SSoby Mathew * finish calculating our ticket value that we're done 1358c5fe0b5SSoby Mathew */ 1368c5fe0b5SSoby Mathew ++my_ticket; 1371c9573a1SSoby Mathew my_bakery_info->lock_data = make_bakery_data(CHOSEN_TICKET, my_ticket); 1388c5fe0b5SSoby Mathew 1398c5fe0b5SSoby Mathew write_cache_op(my_bakery_info, is_cached); 1408c5fe0b5SSoby Mathew 1418c5fe0b5SSoby Mathew return my_ticket; 1428c5fe0b5SSoby Mathew } 1438c5fe0b5SSoby Mathew 1448c5fe0b5SSoby Mathew void bakery_lock_get(unsigned int id, unsigned int offset) 1458c5fe0b5SSoby Mathew { 1468c5fe0b5SSoby Mathew unsigned int they, me, is_cached; 1478c5fe0b5SSoby Mathew unsigned int my_ticket, my_prio, their_ticket; 1488c5fe0b5SSoby Mathew bakery_info_t *their_bakery_info; 1491c9573a1SSoby Mathew unsigned int their_bakery_data; 1508c5fe0b5SSoby Mathew 1518c5fe0b5SSoby Mathew me = platform_get_core_pos(read_mpidr_el1()); 1528c5fe0b5SSoby Mathew 1538c5fe0b5SSoby Mathew is_cached = read_sctlr_el3() & SCTLR_C_BIT; 1548c5fe0b5SSoby Mathew 1558c5fe0b5SSoby Mathew /* Get a ticket */ 1568c5fe0b5SSoby Mathew my_ticket = bakery_get_ticket(id, offset, me, is_cached); 1578c5fe0b5SSoby Mathew 1588c5fe0b5SSoby Mathew /* 1598c5fe0b5SSoby Mathew * Now that we got our ticket, compute our priority value, then compare 1608c5fe0b5SSoby Mathew * with that of others, and proceed to acquire the lock 1618c5fe0b5SSoby Mathew */ 1628c5fe0b5SSoby Mathew my_prio = PRIORITY(my_ticket, me); 1638c5fe0b5SSoby Mathew for (they = 0; they < BAKERY_LOCK_MAX_CPUS; they++) { 1648c5fe0b5SSoby Mathew if (me == they) 1658c5fe0b5SSoby Mathew continue; 1668c5fe0b5SSoby Mathew 1678c5fe0b5SSoby Mathew /* 1688c5fe0b5SSoby Mathew * Get a reference to the other contender's bakery info and 1698c5fe0b5SSoby Mathew * ensure that a stale copy is not read. 1708c5fe0b5SSoby Mathew */ 1718c5fe0b5SSoby Mathew their_bakery_info = get_bakery_info_by_index(offset, id, they); 1728c5fe0b5SSoby Mathew assert(their_bakery_info); 1738c5fe0b5SSoby Mathew 1748c5fe0b5SSoby Mathew /* Wait for the contender to get their ticket */ 1751c9573a1SSoby Mathew do { 1768c5fe0b5SSoby Mathew read_cache_op(their_bakery_info, is_cached); 1778c5fe0b5SSoby Mathew their_bakery_data = their_bakery_info->lock_data; 1781c9573a1SSoby Mathew } while (bakery_is_choosing(their_bakery_data)); 1798c5fe0b5SSoby Mathew 1808c5fe0b5SSoby Mathew /* 1818c5fe0b5SSoby Mathew * If the other party is a contender, they'll have non-zero 1828c5fe0b5SSoby Mathew * (valid) ticket value. If they do, compare priorities 1838c5fe0b5SSoby Mathew */ 1848c5fe0b5SSoby Mathew their_ticket = bakery_ticket_number(their_bakery_data); 1858c5fe0b5SSoby Mathew if (their_ticket && (PRIORITY(their_ticket, they) < my_prio)) { 1868c5fe0b5SSoby Mathew /* 1878c5fe0b5SSoby Mathew * They have higher priority (lower value). Wait for 1888c5fe0b5SSoby Mathew * their ticket value to change (either release the lock 1898c5fe0b5SSoby Mathew * to have it dropped to 0; or drop and probably content 1908c5fe0b5SSoby Mathew * again for the same lock to have an even higher value) 1918c5fe0b5SSoby Mathew */ 1928c5fe0b5SSoby Mathew do { 1938c5fe0b5SSoby Mathew wfe(); 1948c5fe0b5SSoby Mathew read_cache_op(their_bakery_info, is_cached); 1958c5fe0b5SSoby Mathew } while (their_ticket 1968c5fe0b5SSoby Mathew == bakery_ticket_number(their_bakery_info->lock_data)); 1978c5fe0b5SSoby Mathew } 1988c5fe0b5SSoby Mathew } 199*548579f5SSoby Mathew /* Lock acquired */ 2008c5fe0b5SSoby Mathew } 2018c5fe0b5SSoby Mathew 2028c5fe0b5SSoby Mathew void bakery_lock_release(unsigned int id, unsigned int offset) 2038c5fe0b5SSoby Mathew { 2048c5fe0b5SSoby Mathew bakery_info_t *my_bakery_info; 2058c5fe0b5SSoby Mathew unsigned int is_cached = read_sctlr_el3() & SCTLR_C_BIT; 2068c5fe0b5SSoby Mathew 2078c5fe0b5SSoby Mathew my_bakery_info = get_my_bakery_info(offset, id); 208*548579f5SSoby Mathew assert(bakery_ticket_number(my_bakery_info->lock_data)); 209*548579f5SSoby Mathew 2108c5fe0b5SSoby Mathew my_bakery_info->lock_data = 0; 2118c5fe0b5SSoby Mathew write_cache_op(my_bakery_info, is_cached); 2128c5fe0b5SSoby Mathew sev(); 2138c5fe0b5SSoby Mathew } 214