1 /* 2 * Copyright (c) 2022-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef GPT_RME_PRIVATE_H 8 #define GPT_RME_PRIVATE_H 9 10 #include <lib/gpt_rme/gpt_rme.h> 11 #include <lib/utils_def.h> 12 13 /******************************************************************************/ 14 /* GPT descriptor definitions */ 15 /******************************************************************************/ 16 17 /* GPT level 0 descriptor bit definitions */ 18 #define GPT_L0_TYPE_MASK UL(0xF) 19 #define GPT_L0_TYPE_SHIFT U(0) 20 21 /* GPT level 0 table and block descriptors */ 22 #define GPT_L0_TYPE_TBL_DESC UL(3) 23 #define GPT_L0_TYPE_BLK_DESC UL(1) 24 25 #define GPT_L0_TBL_DESC_L1ADDR_MASK UL(0xFFFFFFFFFF) 26 #define GPT_L0_TBL_DESC_L1ADDR_SHIFT U(12) 27 28 #define GPT_L0_BLK_DESC_GPI_MASK UL(0xF) 29 #define GPT_L0_BLK_DESC_GPI_SHIFT U(4) 30 31 /* GPT level 1 Contiguous descriptor */ 32 #define GPT_L1_TYPE_CONT_DESC_MASK UL(0xF) 33 #define GPT_L1_TYPE_CONT_DESC UL(1) 34 35 /* GPT level 1 Contiguous descriptor definitions */ 36 #define GPT_L1_CONTIG_2MB UL(1) 37 #define GPT_L1_CONTIG_32MB UL(2) 38 #define GPT_L1_CONTIG_512MB UL(3) 39 40 #define GPT_L1_CONT_DESC_GPI_SHIFT U(4) 41 #define GPT_L1_CONT_DESC_GPI_MASK UL(0xF) 42 #define GPT_L1_CONT_DESC_CONTIG_SHIFT U(8) 43 #define GPT_L1_CONT_DESC_CONTIG_MASK UL(3) 44 45 /* GPT level 1 Granules descriptor bit definitions */ 46 #define GPT_L1_GRAN_DESC_GPI_MASK UL(0xF) 47 48 /* L1 Contiguous descriptors templates */ 49 #define GPT_L1_CONT_DESC_2MB \ 50 (GPT_L1_TYPE_CONT_DESC | \ 51 (GPT_L1_CONTIG_2MB << GPT_L1_CONT_DESC_CONTIG_SHIFT)) 52 #define GPT_L1_CONT_DESC_32MB \ 53 (GPT_L1_TYPE_CONT_DESC | \ 54 (GPT_L1_CONTIG_32MB << GPT_L1_CONT_DESC_CONTIG_SHIFT)) 55 #define GPT_L1_CONT_DESC_512MB \ 56 (GPT_L1_TYPE_CONT_DESC | \ 57 (GPT_L1_CONTIG_512MB << GPT_L1_CONT_DESC_CONTIG_SHIFT)) 58 59 /* Create L1 Contiguous descriptor from GPI and template */ 60 #define GPT_L1_GPI_CONT_DESC(_gpi, _desc) \ 61 ((_desc) | ((uint64_t)(_gpi) << GPT_L1_CONT_DESC_GPI_SHIFT)) 62 63 /* Create L1 Contiguous descriptor from Granules descriptor and size */ 64 #define GPT_L1_CONT_DESC(_desc, _size) \ 65 (GPT_L1_CONT_DESC_##_size | \ 66 (((_desc) & GPT_L1_GRAN_DESC_GPI_MASK) << \ 67 GPT_L1_CONT_DESC_GPI_SHIFT)) 68 69 /* Create L1 Contiguous descriptor from GPI and size */ 70 #define GPT_L1_CONT_DESC_SIZE(_gpi, _size) \ 71 (GPT_L1_CONT_DESC_##_size | \ 72 (((uint64_t)(_gpi) << GPT_L1_CONT_DESC_GPI_SHIFT)) 73 74 #define GPT_L1_GPI_BYTE(_gpi) (uint64_t)((_gpi) | ((_gpi) << 4)) 75 #define GPT_L1_GPI_HALF(_gpi) (GPT_L1_GPI_BYTE(_gpi) | (GPT_L1_GPI_BYTE(_gpi) << 8)) 76 #define GPT_L1_GPI_WORD(_gpi) (GPT_L1_GPI_HALF(_gpi) | (GPT_L1_GPI_HALF(_gpi) << 16)) 77 78 /* 79 * This macro generates a Granules descriptor 80 * with the same value for every GPI entry. 81 */ 82 #define GPT_BUILD_L1_DESC(_gpi) (GPT_L1_GPI_WORD(_gpi) | (GPT_L1_GPI_WORD(_gpi) << 32)) 83 84 #define GPT_L1_SECURE_DESC GPT_BUILD_L1_DESC(GPT_GPI_SECURE) 85 #define GPT_L1_NS_DESC GPT_BUILD_L1_DESC(GPT_GPI_NS) 86 #define GPT_L1_REALM_DESC GPT_BUILD_L1_DESC(GPT_GPI_REALM) 87 #define GPT_L1_ANY_DESC GPT_BUILD_L1_DESC(GPT_GPI_ANY) 88 89 /******************************************************************************/ 90 /* GPT platform configuration */ 91 /******************************************************************************/ 92 93 /* This value comes from GPCCR_EL3 so no externally supplied definition */ 94 #define GPT_L0GPTSZ ((unsigned int)((read_gpccr_el3() >> \ 95 GPCCR_L0GPTSZ_SHIFT) & GPCCR_L0GPTSZ_MASK)) 96 97 /* The "S" value is directly related to L0GPTSZ */ 98 #define GPT_S_VAL (GPT_L0GPTSZ + 30U) 99 100 /* 101 * Map PPS values to T values. 102 * 103 * PPS Size T 104 * 0b000 4GB 32 105 * 0b001 64GB 36 106 * 0b010 1TB 40 107 * 0b011 4TB 42 108 * 0b100 16TB 44 109 * 0b101 256TB 48 110 * 0b110 4PB 52 111 * 112 * See section 15.1.27 of the RME specification. 113 */ 114 typedef enum { 115 PPS_4GB_T = 32U, 116 PPS_64GB_T = 36U, 117 PPS_1TB_T = 40U, 118 PPS_4TB_T = 42U, 119 PPS_16TB_T = 44U, 120 PPS_256TB_T = 48U, 121 PPS_4PB_T = 52U 122 } gpt_t_val_e; 123 124 /* 125 * Map PGS values to P values. 126 * 127 * PGS Size P 128 * 0b00 4KB 12 129 * 0b10 16KB 14 130 * 0b01 64KB 16 131 * 132 * Note that pgs=0b10 is 16KB and pgs=0b01 is 64KB, this is not a typo. 133 * 134 * See section 15.1.27 of the RME specification. 135 */ 136 typedef enum { 137 PGS_4KB_P = 12U, 138 PGS_16KB_P = 14U, 139 PGS_64KB_P = 16U 140 } gpt_p_val_e; 141 142 /* 143 * Internal structure to retrieve the values from get_gpi_params(); 144 */ 145 typedef struct { 146 uint64_t gpt_l1_desc; 147 uint64_t *gpt_l1_addr; 148 unsigned int idx; 149 unsigned int gpi_shift; 150 unsigned int gpi; 151 #if (RME_GPT_BITLOCK_BLOCK != 0) 152 bitlock_t *lock; 153 LOCK_TYPE mask; 154 #endif 155 } gpi_info_t; 156 157 /* 158 * Look up structure for contiguous blocks and descriptors 159 */ 160 typedef struct { 161 size_t size; 162 unsigned int desc; 163 } gpt_fill_lookup_t; 164 165 typedef void (*gpt_shatter_func)(uintptr_t base, const gpi_info_t *gpi_info, 166 uint64_t l1_desc); 167 typedef void (*gpt_tlbi_func)(uintptr_t base); 168 169 /* 170 * Look-up structure for 171 * invalidating TLBs of GPT entries by Physical address, last level. 172 */ 173 typedef struct { 174 gpt_tlbi_func function; 175 size_t mask; 176 } gpt_tlbi_lookup_t; 177 178 /* Max valid value for PGS */ 179 #define GPT_PGS_MAX (2U) 180 181 /* Max valid value for PPS */ 182 #define GPT_PPS_MAX (6U) 183 184 /******************************************************************************/ 185 /* L0 address attribute macros */ 186 /******************************************************************************/ 187 188 /* 189 * Width of the L0 index field. 190 * 191 * If S is greater than or equal to T then there is a single L0 region covering 192 * the entire protected space so there is no L0 index, so the width (and the 193 * derivative mask value) are both zero. If we don't specifically handle this 194 * special case we'll get a negative width value which does not make sense and 195 * would cause problems. 196 */ 197 #define GPT_L0_IDX_WIDTH(_t) (((unsigned int)(_t) > GPT_S_VAL) ? \ 198 ((unsigned int)(_t) - GPT_S_VAL) : (0U)) 199 200 /* Bit shift for the L0 index field in a PA */ 201 #define GPT_L0_IDX_SHIFT (GPT_S_VAL) 202 203 /* 204 * Mask for the L0 index field, must be shifted. 205 * 206 * The value 0x3FFFFF is 22 bits wide which is the maximum possible width of the 207 * L0 index within a physical address. This is calculated by 208 * ((t_max - 1) - s_min + 1) where t_max is 52 for 4PB, the largest PPS, and 209 * s_min is 30 for 1GB, the smallest L0GPTSZ. 210 */ 211 #define GPT_L0_IDX_MASK(_t) (0x3FFFFFUL >> (22U - \ 212 (GPT_L0_IDX_WIDTH(_t)))) 213 214 /* Total number of L0 regions */ 215 #define GPT_L0_REGION_COUNT(_t) ((GPT_L0_IDX_MASK(_t)) + 1U) 216 217 /* Total size of each GPT L0 region in bytes */ 218 #define GPT_L0_REGION_SIZE (1UL << (GPT_L0_IDX_SHIFT)) 219 220 /* Total size in bytes of the whole L0 table */ 221 #define GPT_L0_TABLE_SIZE(_t) ((GPT_L0_REGION_COUNT(_t)) << 3U) 222 223 /******************************************************************************/ 224 /* L1 address attribute macros */ 225 /******************************************************************************/ 226 227 /* 228 * Width of the L1 index field. 229 * 230 * This field does not have a special case to handle widths less than zero like 231 * the L0 index field above since all valid combinations of PGS (p) and L0GPTSZ 232 * (s) will result in a positive width value. 233 */ 234 #define GPT_L1_IDX_WIDTH(_p) ((GPT_S_VAL - 1U) - \ 235 ((unsigned int)(_p) + 3U)) 236 237 /* Bit shift for the L1 index field */ 238 #define GPT_L1_IDX_SHIFT(_p) ((unsigned int)(_p) + 4U) 239 240 /* 241 * Mask for the L1 index field, must be shifted. 242 * 243 * The value 0x7FFFFF is 23 bits wide and is the maximum possible width of the 244 * L1 index within a physical address. It is calculated by 245 * ((s_max - 1) - (p_min + 4) + 1) where s_max is 39 for 512GB, the largest 246 * L0GPTSZ, and p_min is 12 for 4KB granules, the smallest PGS. 247 */ 248 #define GPT_L1_IDX_MASK(_p) (0x7FFFFFUL >> (23U - \ 249 (GPT_L1_IDX_WIDTH(_p)))) 250 251 /* Bit shift for the index of the L1 GPI in a PA */ 252 #define GPT_L1_GPI_IDX_SHIFT(_p) (_p) 253 254 /* Mask for the index of the L1 GPI in a PA */ 255 #define GPT_L1_GPI_IDX_MASK (0xF) 256 257 /* Total number of entries in each L1 table */ 258 #define GPT_L1_ENTRY_COUNT(_p) ((GPT_L1_IDX_MASK(_p)) + 1UL) 259 260 /* Number of L1 entries in 2MB block */ 261 #define GPT_L1_ENTRY_COUNT_2MB(_p) (SZ_2M >> GPT_L1_IDX_SHIFT(_p)) 262 263 /* Total size in bytes of each L1 table */ 264 #define GPT_L1_TABLE_SIZE(_p) ((GPT_L1_ENTRY_COUNT(_p)) << 3U) 265 266 /******************************************************************************/ 267 /* General helper macros */ 268 /******************************************************************************/ 269 270 /* Protected space actual size in bytes */ 271 #define GPT_PPS_ACTUAL_SIZE(_t) (1UL << (unsigned int)(_t)) 272 273 /* Granule actual size in bytes */ 274 #define GPT_PGS_ACTUAL_SIZE(_p) (1UL << (unsigned int)(_p)) 275 276 /* Number of granules in 2MB block */ 277 #define GPT_PGS_COUNT_2MB(_p) (1UL << (21U - (unsigned int)(_p))) 278 279 /* L0 GPT region size in bytes */ 280 #define GPT_L0GPTSZ_ACTUAL_SIZE (1UL << GPT_S_VAL) 281 282 /* Get the index of the L0 entry from a physical address */ 283 #define GPT_L0_IDX(_pa) ((_pa) >> GPT_L0_IDX_SHIFT) 284 285 /* 286 * This definition is used to determine if a physical address lies on an L0 287 * region boundary. 288 */ 289 #define GPT_IS_L0_ALIGNED(_pa) \ 290 (((_pa) & (GPT_L0_REGION_SIZE - UL(1))) == UL(0)) 291 292 /* Get the type field from an L0 descriptor */ 293 #define GPT_L0_TYPE(_desc) (((_desc) >> GPT_L0_TYPE_SHIFT) & \ 294 GPT_L0_TYPE_MASK) 295 296 /* Create an L0 block descriptor */ 297 #define GPT_L0_BLK_DESC(_gpi) (GPT_L0_TYPE_BLK_DESC | \ 298 (((_gpi) & GPT_L0_BLK_DESC_GPI_MASK) << \ 299 GPT_L0_BLK_DESC_GPI_SHIFT)) 300 301 /* Create an L0 table descriptor with an L1 table address */ 302 #define GPT_L0_TBL_DESC(_pa) (GPT_L0_TYPE_TBL_DESC | ((uint64_t)(_pa) & \ 303 (GPT_L0_TBL_DESC_L1ADDR_MASK << \ 304 GPT_L0_TBL_DESC_L1ADDR_SHIFT))) 305 306 /* Get the GPI from an L0 block descriptor */ 307 #define GPT_L0_BLKD_GPI(_desc) (((_desc) >> GPT_L0_BLK_DESC_GPI_SHIFT) & \ 308 GPT_L0_BLK_DESC_GPI_MASK) 309 310 /* Get the L1 address from an L0 table descriptor */ 311 #define GPT_L0_TBLD_ADDR(_desc) ((uint64_t *)(((_desc) & \ 312 (GPT_L0_TBL_DESC_L1ADDR_MASK << \ 313 GPT_L0_TBL_DESC_L1ADDR_SHIFT)))) 314 315 /* Get the GPI from L1 Contiguous descriptor */ 316 #define GPT_L1_CONT_GPI(_desc) \ 317 (((_desc) >> GPT_L1_CONT_DESC_GPI_SHIFT) & GPT_L1_CONT_DESC_GPI_MASK) 318 319 /* Get the GPI from L1 Granules descriptor */ 320 #define GPT_L1_GRAN_GPI(_desc) ((_desc) & GPT_L1_GRAN_DESC_GPI_MASK) 321 322 /* Get the Contig from L1 Contiguous descriptor */ 323 #define GPT_L1_CONT_CONTIG(_desc) \ 324 (((_desc) >> GPT_L1_CONT_DESC_CONTIG_SHIFT) & \ 325 GPT_L1_CONT_DESC_CONTIG_MASK) 326 327 /* Get the index into the L1 table from a physical address */ 328 #define GPT_L1_IDX(_p, _pa) \ 329 (((_pa) >> GPT_L1_IDX_SHIFT(_p)) & GPT_L1_IDX_MASK(_p)) 330 331 /* Get the index of the GPI within an L1 table entry from a physical address */ 332 #define GPT_L1_GPI_IDX(_p, _pa) \ 333 (((_pa) >> GPT_L1_GPI_IDX_SHIFT(_p)) & GPT_L1_GPI_IDX_MASK) 334 335 /* Determine if an address is granule-aligned */ 336 #define GPT_IS_L1_ALIGNED(_p, _pa) \ 337 (((_pa) & (GPT_PGS_ACTUAL_SIZE(_p) - UL(1))) == UL(0)) 338 339 /* Get aligned addresses */ 340 #define ALIGN_2MB(_addr) ((_addr) & ~(SZ_2M - 1UL)) 341 #define ALIGN_32MB(_addr) ((_addr) & ~(SZ_32M - 1UL)) 342 #define ALIGN_512MB(_addr) ((_addr) & ~(SZ_512M - 1UL)) 343 344 /* Determine if region is contiguous */ 345 #define GPT_REGION_IS_CONT(_len, _addr, _size) \ 346 (((_len) >= (_size)) && (((_addr) & ((_size) - UL(1))) == UL(0))) 347 348 /* Get 32MB block number in 512MB block: 0-15 */ 349 #define GET_32MB_NUM(_addr) ((_addr >> 25) & 0xF) 350 351 /* Get 2MB block number in 32MB block: 0-15 */ 352 #define GET_2MB_NUM(_addr) ((_addr >> 21) & 0xF) 353 354 #endif /* GPT_RME_PRIVATE_H */ 355