1 /* 2 * Copyright (c) 2021-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_features.h> 9 #include <arch_helpers.h> 10 #include <lib/extensions/trbe.h> 11 12 void trbe_enable(cpu_context_t *ctx) 13 { 14 el3_state_t *state = get_el3state_ctx(ctx); 15 u_register_t mdcr_el3_val = read_ctx_reg(state, CTX_MDCR_EL3); 16 17 /* 18 * MDCR_EL3.NSTBE = 0b0 19 * Trace Buffer owning Security state is Non-secure state. If FEAT_RME 20 * is not implemented, this field is RES0. 21 * 22 * MDCR_EL3.NSTB = 0b11 23 * Allow access of trace buffer control registers from NS-EL1 and 24 * NS-EL2, tracing is prohibited in Secure and Realm state (if 25 * implemented). 26 */ 27 mdcr_el3_val |= MDCR_NSTB(MDCR_NSTB_EL1); 28 mdcr_el3_val &= ~(MDCR_NSTBE_BIT); 29 write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3_val); 30 } 31 32 void trbe_disable(cpu_context_t *ctx) 33 { 34 el3_state_t *state = get_el3state_ctx(ctx); 35 u_register_t mdcr_el3_val = read_ctx_reg(state, CTX_MDCR_EL3); 36 37 /* 38 * MDCR_EL3.NSTBE = 0b0 39 * Trace Buffer owning Security state is secure state. If FEAT_RME 40 * is not implemented, this field is RES0. 41 * 42 * MDCR_EL3.NSTB = 0b00 43 * Clear these bits to disable access of trace buffer control registers 44 * from lower ELs in any security state. 45 */ 46 mdcr_el3_val &= ~(MDCR_NSTB(MDCR_NSTB_EL1)); 47 mdcr_el3_val &= ~(MDCR_NSTBE_BIT); 48 write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3_val); 49 } 50 51 void trbe_init_el2_unused(void) 52 { 53 /* 54 * MDCR_EL2.E2TB: Set to zero so that the trace Buffer 55 * owning exception level is NS-EL1 and, tracing is 56 * prohibited at NS-EL2. These bits are RES0 when 57 * FEAT_TRBE is not implemented. 58 */ 59 write_mdcr_el2(read_mdcr_el2() & ~MDCR_EL2_E2TB(MDCR_EL2_E2TB_EL1)); 60 } 61