1*30655136SGovindraj Raja/* 2*30655136SGovindraj Raja * Copyright (c) 2024, Arm Limited. All rights reserved. 3*30655136SGovindraj Raja * 4*30655136SGovindraj Raja * SPDX-License-Identifier: BSD-3-Clause 5*30655136SGovindraj Raja */ 6*30655136SGovindraj Raja 7*30655136SGovindraj Raja#include <arch.h> 8*30655136SGovindraj Raja#include <asm_macros.S> 9*30655136SGovindraj Raja#include <lib/extensions/sysreg128.h> 10*30655136SGovindraj Raja 11*30655136SGovindraj Raja .global read_par_el1 12*30655136SGovindraj Raja .global write_par_el1 13*30655136SGovindraj Raja .global read_ttbr0_el1 14*30655136SGovindraj Raja .global write_ttbr0_el1 15*30655136SGovindraj Raja .global read_ttbr1_el1 16*30655136SGovindraj Raja .global write_ttbr1_el1 17*30655136SGovindraj Raja .global read_ttbr0_el2 18*30655136SGovindraj Raja .global write_ttbr0_el2 19*30655136SGovindraj Raja .global read_ttbr1_el2 20*30655136SGovindraj Raja .global write_ttbr1_el2 21*30655136SGovindraj Raja .global read_vttbr_el2 22*30655136SGovindraj Raja .global write_vttbr_el2 23*30655136SGovindraj Raja .global read_rcwmask_el1 24*30655136SGovindraj Raja .global write_rcwmask_el1 25*30655136SGovindraj Raja .global read_rcwsmask_el1 26*30655136SGovindraj Raja .global write_rcwsmask_el1 27*30655136SGovindraj Raja 28*30655136SGovindraj Raja/* 29*30655136SGovindraj Raja * _mrrs - Move System register to two adjacent general-purpose 30*30655136SGovindraj Raja * registers. 31*30655136SGovindraj Raja * Instruction: MRRS <Xt>, <Xt+1>, (<systemreg>|S<op0>_<op1>_<Cn>_<Cm>_<op2>) 32*30655136SGovindraj Raja * 33*30655136SGovindraj Raja * Arguments/Opcode bit field: 34*30655136SGovindraj Raja * regins: System register opcode. 35*30655136SGovindraj Raja * 36*30655136SGovindraj Raja * Clobbers: x0,x1,x2 37*30655136SGovindraj Raja */ 38*30655136SGovindraj Raja.macro _mrrs regins:req 39*30655136SGovindraj Raja#if ENABLE_FEAT_D128 == 2 40*30655136SGovindraj Raja mrs x0, ID_AA64MMFR3_EL1 41*30655136SGovindraj Raja tst x0, #(ID_AA64MMFR3_EL1_D128_MASK << ID_AA64MMFR3_EL1_D128_SHIFT) 42*30655136SGovindraj Raja bne 1f 43*30655136SGovindraj Raja /* If FEAT_D128 is not implemented then use mrs */ 44*30655136SGovindraj Raja .inst 0xD5300000 | (\regins) 45*30655136SGovindraj Raja ret 46*30655136SGovindraj Raja#endif 47*30655136SGovindraj Raja1: 48*30655136SGovindraj Raja .inst 0xD5700000 | (\regins) 49*30655136SGovindraj Raja ret 50*30655136SGovindraj Raja.endm 51*30655136SGovindraj Raja 52*30655136SGovindraj Raja/* 53*30655136SGovindraj Raja * _msrr - Move two adjacent general-purpose registers to System register. 54*30655136SGovindraj Raja * Instruction: MSRR (<systemreg>|S<op0>_<op1>_<Cn>_<Cm>_<op2>), <Xt>, <Xt+1> 55*30655136SGovindraj Raja * 56*30655136SGovindraj Raja * Arguments/Opcode bit field: 57*30655136SGovindraj Raja * regins: System register opcode. 58*30655136SGovindraj Raja * 59*30655136SGovindraj Raja * Clobbers: x0,x1,x2 60*30655136SGovindraj Raja */ 61*30655136SGovindraj Raja.macro _msrr regins:req 62*30655136SGovindraj Raja /* If FEAT_D128 is not implemented use msr, dont tamper 63*30655136SGovindraj Raja * x0, x1 as they maybe used for mrrs */ 64*30655136SGovindraj Raja#if ENABLE_FEAT_D128 == 2 65*30655136SGovindraj Raja mrs x2, ID_AA64MMFR3_EL1 66*30655136SGovindraj Raja tst x2, #(ID_AA64MMFR3_EL1_D128_MASK << ID_AA64MMFR3_EL1_D128_SHIFT) 67*30655136SGovindraj Raja bne 1f 68*30655136SGovindraj Raja /* If FEAT_D128 is not implemented then use msr */ 69*30655136SGovindraj Raja .inst 0xD5100000 | (\regins) 70*30655136SGovindraj Raja ret 71*30655136SGovindraj Raja#endif 72*30655136SGovindraj Raja1: 73*30655136SGovindraj Raja .inst 0xD5500000 | (\regins) 74*30655136SGovindraj Raja ret 75*30655136SGovindraj Raja.endm 76*30655136SGovindraj Raja 77*30655136SGovindraj Rajafunc read_par_el1 78*30655136SGovindraj Raja _mrrs 0x87400 /* S3_0_C7_C4_0 */ 79*30655136SGovindraj Rajaendfunc read_par_el1 80*30655136SGovindraj Raja 81*30655136SGovindraj Rajafunc write_par_el1 82*30655136SGovindraj Raja _msrr 0x87400 83*30655136SGovindraj Rajaendfunc write_par_el1 84*30655136SGovindraj Raja 85*30655136SGovindraj Rajafunc read_ttbr0_el1 86*30655136SGovindraj Raja _mrrs 0x82000 /* S3_0_C2_C0_0 */ 87*30655136SGovindraj Rajaendfunc read_ttbr0_el1 88*30655136SGovindraj Raja 89*30655136SGovindraj Rajafunc write_ttbr0_el1 90*30655136SGovindraj Raja _msrr 0x82000 91*30655136SGovindraj Rajaendfunc write_ttbr0_el1 92*30655136SGovindraj Raja 93*30655136SGovindraj Rajafunc read_ttbr1_el1 94*30655136SGovindraj Raja _mrrs 0x82020 /* S3_0_C2_C0_1 */ 95*30655136SGovindraj Rajaendfunc read_ttbr1_el1 96*30655136SGovindraj Raja 97*30655136SGovindraj Rajafunc write_ttbr1_el1 98*30655136SGovindraj Raja _msrr 0x82020 99*30655136SGovindraj Rajaendfunc write_ttbr1_el1 100*30655136SGovindraj Raja 101*30655136SGovindraj Rajafunc read_ttbr0_el2 102*30655136SGovindraj Raja _mrrs 0xC2000 /* S3_4_C2_C0_0 */ 103*30655136SGovindraj Rajaendfunc read_ttbr0_el2 104*30655136SGovindraj Raja 105*30655136SGovindraj Rajafunc write_ttbr0_el2 106*30655136SGovindraj Raja _msrr 0xC2000 107*30655136SGovindraj Rajaendfunc write_ttbr0_el2 108*30655136SGovindraj Raja 109*30655136SGovindraj Rajafunc read_ttbr1_el2 110*30655136SGovindraj Raja _mrrs 0xC2020 /* S3_4_C2_C0_1 */ 111*30655136SGovindraj Rajaendfunc read_ttbr1_el2 112*30655136SGovindraj Raja 113*30655136SGovindraj Rajafunc write_ttbr1_el2 114*30655136SGovindraj Raja _msrr 0xC2020 115*30655136SGovindraj Rajaendfunc write_ttbr1_el2 116*30655136SGovindraj Raja 117*30655136SGovindraj Rajafunc read_vttbr_el2 118*30655136SGovindraj Raja _mrrs 0xC2100 /* S3_4_C2_C1_0 */ 119*30655136SGovindraj Rajaendfunc read_vttbr_el2 120*30655136SGovindraj Raja 121*30655136SGovindraj Rajafunc write_vttbr_el2 122*30655136SGovindraj Raja _msrr 0xC2100 123*30655136SGovindraj Rajaendfunc write_vttbr_el2 124*30655136SGovindraj Raja 125*30655136SGovindraj Rajafunc read_rcwmask_el1 126*30655136SGovindraj Raja _mrrs 0x8D0C0 /* S3_0_C13_C0_6 */ 127*30655136SGovindraj Rajaendfunc read_rcwmask_el1 128*30655136SGovindraj Raja 129*30655136SGovindraj Rajafunc write_rcwmask_el1 130*30655136SGovindraj Raja _msrr 0x8D0C0 131*30655136SGovindraj Rajaendfunc write_rcwmask_el1 132*30655136SGovindraj Raja 133*30655136SGovindraj Rajafunc read_rcwsmask_el1 134*30655136SGovindraj Raja _mrrs 0x8D060 /* S3_0_C13_C0_3 */ 135*30655136SGovindraj Rajaendfunc read_rcwsmask_el1 136*30655136SGovindraj Raja 137*30655136SGovindraj Rajafunc write_rcwsmask_el1 138*30655136SGovindraj Raja _msrr 0x8D060 139*30655136SGovindraj Rajaendfunc write_rcwsmask_el1 140