1 /* 2 * Copyright (c) 2021-2023, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <stdbool.h> 8 9 #include <arch.h> 10 #include <arch_helpers.h> 11 #include <lib/extensions/sys_reg_trace.h> 12 13 void sys_reg_trace_enable(cpu_context_t *ctx) 14 { 15 /* 16 * CPTR_EL3.TTA: Set to zero so that System register accesses to the 17 * trace registers do not trap to EL3. 18 */ 19 uint64_t val = read_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3); 20 21 val &= ~(TTA_BIT); 22 write_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3, val); 23 } 24 25 void sys_reg_trace_disable(cpu_context_t *ctx) 26 { 27 /* 28 * CPTR_EL3.TTA: Set to one so that System register accesses to the 29 * trace registers trap to EL3, unless it is trapped by CPACR.TRCDIS, 30 * CPACR_EL1.TTA, or CPTR_EL2.TTA 31 */ 32 uint64_t val = read_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3); 33 34 val |= TTA_BIT; 35 write_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3, val); 36 } 37 38 void sys_reg_trace_init_el2_unused(void) 39 { 40 /* 41 * CPTR_EL2.TTA: Set to zero so that Non-secure System register accesses 42 * to the trace registers from both Execution states do not trap to 43 * EL2. If PE trace unit System registers are not implemented then this 44 * bit is reserved, and must be set to zero. 45 */ 46 write_cptr_el2(read_cptr_el2() & ~CPTR_EL2_TTA_BIT); 47 } 48