1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <pubsub.h> 10 #include <stdbool.h> 11 #include <sve.h> 12 13 bool sve_supported(void) 14 { 15 uint64_t features; 16 17 features = read_id_aa64pfr0_el1() >> ID_AA64PFR0_SVE_SHIFT; 18 return (features & ID_AA64PFR0_SVE_MASK) == 1U; 19 } 20 21 static void *disable_sve_hook(const void *arg) 22 { 23 uint64_t cptr; 24 25 if (!sve_supported()) 26 return (void *)-1; 27 28 /* 29 * Disable SVE, SIMD and FP access for the Secure world. 30 * As the SIMD/FP registers are part of the SVE Z-registers, any 31 * use of SIMD/FP functionality will corrupt the SVE registers. 32 * Therefore it is necessary to prevent use of SIMD/FP support 33 * in the Secure world as well as SVE functionality. 34 */ 35 cptr = read_cptr_el3(); 36 cptr = (cptr | TFP_BIT) & ~(CPTR_EZ_BIT); 37 write_cptr_el3(cptr); 38 39 /* 40 * No explicit ISB required here as ERET to switch to Secure 41 * world covers it 42 */ 43 return (void *)0; 44 } 45 46 static void *enable_sve_hook(const void *arg) 47 { 48 uint64_t cptr; 49 50 if (!sve_supported()) 51 return (void *)-1; 52 53 /* 54 * Enable SVE, SIMD and FP access for the Non-secure world. 55 */ 56 cptr = read_cptr_el3(); 57 cptr = (cptr | CPTR_EZ_BIT) & ~(TFP_BIT); 58 write_cptr_el3(cptr); 59 60 /* 61 * No explicit ISB required here as ERET to switch to Non-secure 62 * world covers it 63 */ 64 return (void *)0; 65 } 66 67 void sve_enable(bool el2_unused) 68 { 69 uint64_t cptr; 70 71 if (!sve_supported()) 72 return; 73 74 #if CTX_INCLUDE_FPREGS 75 /* 76 * CTX_INCLUDE_FPREGS is not supported on SVE enabled systems. 77 */ 78 assert(0); 79 #endif 80 /* 81 * Update CPTR_EL3 to enable access to SVE functionality for the 82 * Non-secure world. 83 * NOTE - assumed that CPTR_EL3.TFP is set to allow access to 84 * the SIMD, floating-point and SVE support. 85 * 86 * CPTR_EL3.EZ: Set to 1 to enable access to SVE functionality 87 * in the Non-secure world. 88 */ 89 cptr = read_cptr_el3(); 90 cptr |= CPTR_EZ_BIT; 91 write_cptr_el3(cptr); 92 93 /* 94 * Need explicit ISB here to guarantee that update to ZCR_ELx 95 * and CPTR_EL2.TZ do not result in trap to EL3. 96 */ 97 isb(); 98 99 /* 100 * Ensure lower ELs have access to full vector length. 101 */ 102 write_zcr_el3(ZCR_EL3_LEN_MASK); 103 104 if (el2_unused) { 105 /* 106 * Update CPTR_EL2 to enable access to SVE functionality 107 * for Non-secure world, EL2 and Non-secure EL1 and EL0. 108 * NOTE - assumed that CPTR_EL2.TFP is set to allow 109 * access to the SIMD, floating-point and SVE support. 110 * 111 * CPTR_EL2.TZ: Set to 0 to enable access to SVE support 112 * for EL2 and Non-secure EL1 and EL0. 113 */ 114 cptr = read_cptr_el2(); 115 cptr &= ~(CPTR_EL2_TZ_BIT); 116 write_cptr_el2(cptr); 117 118 /* 119 * Ensure lower ELs have access to full vector length. 120 */ 121 write_zcr_el2(ZCR_EL2_LEN_MASK); 122 } 123 /* 124 * No explicit ISB required here as ERET to switch to 125 * Non-secure world covers it. 126 */ 127 } 128 129 SUBSCRIBE_TO_EVENT(cm_exited_normal_world, disable_sve_hook); 130 SUBSCRIBE_TO_EVENT(cm_entering_normal_world, enable_sve_hook); 131