1 /* 2 * Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <stdbool.h> 8 9 #include <arch.h> 10 #include <arch_helpers.h> 11 #include <lib/cassert.h> 12 #include <lib/el3_runtime/pubsub.h> 13 #include <lib/extensions/sve.h> 14 15 CASSERT(SVE_VECTOR_LEN <= 2048, assert_sve_vl_too_long); 16 CASSERT(SVE_VECTOR_LEN >= 128, assert_sve_vl_too_short); 17 CASSERT((SVE_VECTOR_LEN % 128) == 0, assert_sve_vl_granule); 18 19 /* 20 * Converts SVE vector size restriction in bytes to LEN according to ZCR_EL3 documentation. 21 * VECTOR_SIZE = (LEN+1) * 128 22 */ 23 #define CONVERT_SVE_LENGTH(x) (((x / 128) - 1)) 24 25 void sve_init_el3(void) 26 { 27 /* Restrict maximum SVE vector length (SVE_VECTOR_LEN+1) * 128. */ 28 write_zcr_el3(ZCR_EL3_LEN_MASK & CONVERT_SVE_LENGTH(SVE_VECTOR_LEN)); 29 } 30 31 void sve_enable_per_world(per_world_context_t *per_world_ctx) 32 { 33 u_register_t cptr_el3; 34 35 /* Enable access to SVE functionality for all ELs. */ 36 cptr_el3 = per_world_ctx->ctx_cptr_el3; 37 cptr_el3 = (cptr_el3 | CPTR_EZ_BIT) & ~(TFP_BIT); 38 per_world_ctx->ctx_cptr_el3 = cptr_el3; 39 } 40 41 void sve_init_el2_unused(void) 42 { 43 u_register_t reg; 44 45 /* 46 * CPTR_EL2.TFP: Set to zero so that Non-secure accesses to Advanced 47 * SIMD and floating-point functionality from both Execution states do 48 * not trap to EL2. 49 * 50 * CPTR_EL2.TZ: Set to zero so that no SVE instruction execution is 51 * trapped. 52 * 53 * CPTR_EL2.ZEN: Set to 0b11 so that no SVE instruction execution is 54 * trapped. 55 */ 56 reg = read_cptr_el2(); 57 reg &= ~(CPTR_EL2_TFP_BIT | CPTR_EL2_TZ_BIT); 58 reg |= ULL(3) << CPTR_EL2_ZEN_SHIFT; 59 write_cptr_el2(reg); 60 } 61 62 void sve_disable_per_world(per_world_context_t *per_world_ctx) 63 { 64 u_register_t reg; 65 66 /* Disable SVE and FPU since they share registers. */ 67 reg = per_world_ctx->ctx_cptr_el3; 68 reg &= ~CPTR_EZ_BIT; /* Trap SVE */ 69 reg |= TFP_BIT; /* Trap FPU/SIMD */ 70 per_world_ctx->ctx_cptr_el3 = reg; 71 } 72