11a853370SDavid Cunado /* 2*bebcf27fSMark Brown * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved. 31a853370SDavid Cunado * 41a853370SDavid Cunado * SPDX-License-Identifier: BSD-3-Clause 51a853370SDavid Cunado */ 61a853370SDavid Cunado 709d40e0eSAntonio Nino Diaz #include <stdbool.h> 809d40e0eSAntonio Nino Diaz 91a853370SDavid Cunado #include <arch.h> 101a853370SDavid Cunado #include <arch_helpers.h> 11*bebcf27fSMark Brown #include <lib/cassert.h> 1209d40e0eSAntonio Nino Diaz #include <lib/el3_runtime/pubsub.h> 1309d40e0eSAntonio Nino Diaz #include <lib/extensions/sve.h> 141a853370SDavid Cunado 15*bebcf27fSMark Brown CASSERT(SVE_VECTOR_LEN <= 2048, assert_sve_vl_too_long); 16*bebcf27fSMark Brown CASSERT(SVE_VECTOR_LEN >= 128, assert_sve_vl_too_short); 17*bebcf27fSMark Brown CASSERT((SVE_VECTOR_LEN % 128) == 0, assert_sve_vl_granule); 18*bebcf27fSMark Brown 190c5e7d1cSMax Shvetsov /* 200c5e7d1cSMax Shvetsov * Converts SVE vector size restriction in bytes to LEN according to ZCR_EL3 documentation. 210c5e7d1cSMax Shvetsov * VECTOR_SIZE = (LEN+1) * 128 220c5e7d1cSMax Shvetsov */ 230c5e7d1cSMax Shvetsov #define CONVERT_SVE_LENGTH(x) (((x / 128) - 1)) 240c5e7d1cSMax Shvetsov 250c5e7d1cSMax Shvetsov static bool sve_supported(void) 261a853370SDavid Cunado { 271a853370SDavid Cunado uint64_t features; 281a853370SDavid Cunado 291a853370SDavid Cunado features = read_id_aa64pfr0_el1() >> ID_AA64PFR0_SVE_SHIFT; 3040daecc1SAntonio Nino Diaz return (features & ID_AA64PFR0_SVE_MASK) == 1U; 312ff8fbf3SDimitris Papastamos } 322ff8fbf3SDimitris Papastamos 330c5e7d1cSMax Shvetsov void sve_enable(cpu_context_t *context) 342ff8fbf3SDimitris Papastamos { 3568ac5ed0SArunachalam Ganapathy u_register_t cptr_el3; 3668ac5ed0SArunachalam Ganapathy 370c5e7d1cSMax Shvetsov if (!sve_supported()) { 382ff8fbf3SDimitris Papastamos return; 391a853370SDavid Cunado } 401a853370SDavid Cunado 4168ac5ed0SArunachalam Ganapathy cptr_el3 = read_ctx_reg(get_el3state_ctx(context), CTX_CPTR_EL3); 420c5e7d1cSMax Shvetsov 430c5e7d1cSMax Shvetsov /* Enable access to SVE functionality for all ELs. */ 440c5e7d1cSMax Shvetsov cptr_el3 = (cptr_el3 | CPTR_EZ_BIT) & ~(TFP_BIT); 450c5e7d1cSMax Shvetsov write_ctx_reg(get_el3state_ctx(context), CTX_CPTR_EL3, cptr_el3); 460c5e7d1cSMax Shvetsov 47*bebcf27fSMark Brown /* Restrict maximum SVE vector length (SVE_VECTOR_LEN+1) * 128. */ 480c5e7d1cSMax Shvetsov write_ctx_reg(get_el3state_ctx(context), CTX_ZCR_EL3, 49*bebcf27fSMark Brown (ZCR_EL3_LEN_MASK & CONVERT_SVE_LENGTH(SVE_VECTOR_LEN))); 500c5e7d1cSMax Shvetsov } 51dc78e62dSjohpow01 52dc78e62dSjohpow01 void sve_disable(cpu_context_t *context) 53dc78e62dSjohpow01 { 54dc78e62dSjohpow01 u_register_t reg; 55dc78e62dSjohpow01 el3_state_t *state; 56dc78e62dSjohpow01 57dc78e62dSjohpow01 /* Make sure SME is implemented in hardware before continuing. */ 58dc78e62dSjohpow01 if (!sve_supported()) { 59dc78e62dSjohpow01 return; 60dc78e62dSjohpow01 } 61dc78e62dSjohpow01 62dc78e62dSjohpow01 /* Get the context state. */ 63dc78e62dSjohpow01 state = get_el3state_ctx(context); 64dc78e62dSjohpow01 65dc78e62dSjohpow01 /* Disable SVE and FPU since they share registers. */ 66dc78e62dSjohpow01 reg = read_ctx_reg(state, CTX_CPTR_EL3); 67dc78e62dSjohpow01 reg &= ~CPTR_EZ_BIT; /* Trap SVE */ 68dc78e62dSjohpow01 reg |= TFP_BIT; /* Trap FPU/SIMD */ 69dc78e62dSjohpow01 write_ctx_reg(state, CTX_CPTR_EL3, reg); 70dc78e62dSjohpow01 } 71