11a853370SDavid Cunado /* 22b0bc4e0SJayanth Dodderi Chidanand * Copyright (c) 2017-2023, ARM Limited and Contributors. All rights reserved. 31a853370SDavid Cunado * 41a853370SDavid Cunado * SPDX-License-Identifier: BSD-3-Clause 51a853370SDavid Cunado */ 61a853370SDavid Cunado 709d40e0eSAntonio Nino Diaz #include <stdbool.h> 809d40e0eSAntonio Nino Diaz 91a853370SDavid Cunado #include <arch.h> 101a853370SDavid Cunado #include <arch_helpers.h> 11bebcf27fSMark Brown #include <lib/cassert.h> 1209d40e0eSAntonio Nino Diaz #include <lib/el3_runtime/pubsub.h> 1309d40e0eSAntonio Nino Diaz #include <lib/extensions/sve.h> 141a853370SDavid Cunado 15bebcf27fSMark Brown CASSERT(SVE_VECTOR_LEN <= 2048, assert_sve_vl_too_long); 16bebcf27fSMark Brown CASSERT(SVE_VECTOR_LEN >= 128, assert_sve_vl_too_short); 17bebcf27fSMark Brown CASSERT((SVE_VECTOR_LEN % 128) == 0, assert_sve_vl_granule); 18bebcf27fSMark Brown 190c5e7d1cSMax Shvetsov /* 200c5e7d1cSMax Shvetsov * Converts SVE vector size restriction in bytes to LEN according to ZCR_EL3 documentation. 210c5e7d1cSMax Shvetsov * VECTOR_SIZE = (LEN+1) * 128 220c5e7d1cSMax Shvetsov */ 230c5e7d1cSMax Shvetsov #define CONVERT_SVE_LENGTH(x) (((x / 128) - 1)) 240c5e7d1cSMax Shvetsov 250c5e7d1cSMax Shvetsov void sve_enable(cpu_context_t *context) 262ff8fbf3SDimitris Papastamos { 2768ac5ed0SArunachalam Ganapathy u_register_t cptr_el3; 2868ac5ed0SArunachalam Ganapathy 2968ac5ed0SArunachalam Ganapathy cptr_el3 = read_ctx_reg(get_el3state_ctx(context), CTX_CPTR_EL3); 300c5e7d1cSMax Shvetsov 310c5e7d1cSMax Shvetsov /* Enable access to SVE functionality for all ELs. */ 320c5e7d1cSMax Shvetsov cptr_el3 = (cptr_el3 | CPTR_EZ_BIT) & ~(TFP_BIT); 330c5e7d1cSMax Shvetsov write_ctx_reg(get_el3state_ctx(context), CTX_CPTR_EL3, cptr_el3); 340c5e7d1cSMax Shvetsov 35bebcf27fSMark Brown /* Restrict maximum SVE vector length (SVE_VECTOR_LEN+1) * 128. */ 360c5e7d1cSMax Shvetsov write_ctx_reg(get_el3state_ctx(context), CTX_ZCR_EL3, 37bebcf27fSMark Brown (ZCR_EL3_LEN_MASK & CONVERT_SVE_LENGTH(SVE_VECTOR_LEN))); 380c5e7d1cSMax Shvetsov } 39dc78e62dSjohpow01 40*60d330dcSBoyan Karatotev void sve_init_el2_unused(void) 41*60d330dcSBoyan Karatotev { 42*60d330dcSBoyan Karatotev /* 43*60d330dcSBoyan Karatotev * CPTR_EL2.TFP: Set to zero so that Non-secure accesses to Advanced 44*60d330dcSBoyan Karatotev * SIMD and floating-point functionality from both Execution states do 45*60d330dcSBoyan Karatotev * not trap to EL2. 46*60d330dcSBoyan Karatotev */ 47*60d330dcSBoyan Karatotev write_cptr_el2(read_cptr_el2() & ~CPTR_EL2_TFP_BIT); 48*60d330dcSBoyan Karatotev } 49*60d330dcSBoyan Karatotev 50dc78e62dSjohpow01 void sve_disable(cpu_context_t *context) 51dc78e62dSjohpow01 { 52dc78e62dSjohpow01 u_register_t reg; 53dc78e62dSjohpow01 el3_state_t *state; 54dc78e62dSjohpow01 55dc78e62dSjohpow01 /* Get the context state. */ 56dc78e62dSjohpow01 state = get_el3state_ctx(context); 57dc78e62dSjohpow01 58dc78e62dSjohpow01 /* Disable SVE and FPU since they share registers. */ 59dc78e62dSjohpow01 reg = read_ctx_reg(state, CTX_CPTR_EL3); 60dc78e62dSjohpow01 reg &= ~CPTR_EZ_BIT; /* Trap SVE */ 61dc78e62dSjohpow01 reg |= TFP_BIT; /* Trap FPU/SIMD */ 62dc78e62dSjohpow01 write_ctx_reg(state, CTX_CPTR_EL3, reg); 63dc78e62dSjohpow01 } 64