1 /* 2 * Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <stdbool.h> 8 9 #include <arch.h> 10 #include <arch_features.h> 11 #include <arch_helpers.h> 12 #include <lib/extensions/spe.h> 13 14 #include <plat/common/platform.h> 15 16 void spe_enable(cpu_context_t *ctx) 17 { 18 el3_state_t *state = get_el3state_ctx(ctx); 19 u_register_t mdcr_el3_val = read_ctx_reg(state, CTX_MDCR_EL3); 20 21 /* 22 * MDCR_EL3.NSPB (ARM v8.2): SPE enabled in Non-secure state 23 * and disabled in secure state. Accesses to SPE registers at 24 * S-EL1 generate trap exceptions to EL3. 25 * 26 * MDCR_EL3.NSPBE: Profiling Buffer uses Non-secure Virtual Addresses. 27 * When FEAT_RME is not implemented, this field is RES0. 28 * 29 * MDCR_EL3.EnPMSN (ARM v8.7) and MDCR_EL3.EnPMS3: Do not trap access to 30 * PMSNEVFR_EL1 or PMSDSFR_EL1 register at NS-EL1 or NS-EL2 to EL3 if FEAT_SPEv1p2 31 * or FEAT_SPE_FDS are implemented. Setting these bits to 1 doesn't have any 32 * effect on it when the features aren't implemented. 33 */ 34 mdcr_el3_val |= MDCR_NSPB(MDCR_NSPB_EL1) | MDCR_EnPMSN_BIT | MDCR_EnPMS3_BIT; 35 mdcr_el3_val &= ~(MDCR_NSPBE_BIT); 36 write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3_val); 37 } 38 39 void spe_disable(cpu_context_t *ctx) 40 { 41 el3_state_t *state = get_el3state_ctx(ctx); 42 u_register_t mdcr_el3_val = read_ctx_reg(state, CTX_MDCR_EL3); 43 44 /* 45 * MDCR_EL3.{NSPB,NSPBE} = 0b00, 0b0 46 * Disable access of profiling buffer control registers from lower ELs 47 * in any security state. Secure state owns the buffer. 48 * 49 * MDCR_EL3.EnPMSN (ARM v8.7) and MDCR_EL3.EnPMS3: Clear the bits to trap access 50 * of PMSNEVFR_EL1 and PMSDSFR_EL1 from EL2/EL1 to EL3. 51 */ 52 mdcr_el3_val &= ~(MDCR_NSPB(MDCR_NSPB_EL1) | MDCR_NSPBE_BIT | MDCR_EnPMSN_BIT | 53 MDCR_EnPMS3_BIT); 54 write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3_val); 55 } 56 57 void spe_init_el2_unused(void) 58 { 59 uint64_t v; 60 61 /* 62 * MDCR_EL2.TPMS (ARM v8.2): Do not trap statistical 63 * profiling controls to EL2. 64 * 65 * MDCR_EL2.E2PB (ARM v8.2): SPE enabled in Non-secure 66 * state. Accesses to profiling buffer controls at 67 * Non-secure EL1 are not trapped to EL2. 68 */ 69 v = read_mdcr_el2(); 70 v &= ~MDCR_EL2_TPMS; 71 v |= MDCR_EL2_E2PB(MDCR_EL2_E2PB_EL1); 72 write_mdcr_el2(v); 73 } 74