1 /* 2 * Copyright (c) 2021-2023, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <stdbool.h> 8 9 #include <arch.h> 10 #include <arch_features.h> 11 #include <arch_helpers.h> 12 #include <common/debug.h> 13 #include <lib/el3_runtime/context_mgmt.h> 14 #include <lib/extensions/sme.h> 15 #include <lib/extensions/sve.h> 16 17 void sme_enable(cpu_context_t *context) 18 { 19 u_register_t reg; 20 u_register_t cptr_el3; 21 el3_state_t *state; 22 23 /* Get the context state. */ 24 state = get_el3state_ctx(context); 25 26 /* Enable SME in CPTR_EL3. */ 27 reg = read_ctx_reg(state, CTX_CPTR_EL3); 28 reg |= ESM_BIT; 29 write_ctx_reg(state, CTX_CPTR_EL3, reg); 30 31 /* Set the ENTP2 bit in SCR_EL3 to enable access to TPIDR2_EL0. */ 32 reg = read_ctx_reg(state, CTX_SCR_EL3); 33 reg |= SCR_ENTP2_BIT; 34 write_ctx_reg(state, CTX_SCR_EL3, reg); 35 36 /* Set CPTR_EL3.ESM bit so we can write SMCR_EL3 without trapping. */ 37 cptr_el3 = read_cptr_el3(); 38 write_cptr_el3(cptr_el3 | ESM_BIT); 39 isb(); 40 41 /* 42 * Set the max LEN value and FA64 bit. This register is set up globally 43 * to be the least restrictive, then lower ELs can restrict as needed 44 * using SMCR_EL2 and SMCR_EL1. 45 */ 46 reg = SMCR_ELX_LEN_MAX; 47 48 if (read_feat_sme_fa64_id_field() != 0U) { 49 VERBOSE("[SME] FA64 enabled\n"); 50 reg |= SMCR_ELX_FA64_BIT; 51 } 52 53 /* 54 * Enable access to ZT0 register. 55 * Make sure FEAT_SME2 is supported by the hardware before continuing. 56 * If supported, Set the EZT0 bit in SMCR_EL3 to allow instructions to 57 * access ZT0 register without trapping. 58 */ 59 if (is_feat_sme2_supported()) { 60 VERBOSE("SME2 enabled\n"); 61 reg |= SMCR_ELX_EZT0_BIT; 62 } 63 write_smcr_el3(reg); 64 65 /* Reset CPTR_EL3 value. */ 66 write_cptr_el3(cptr_el3); 67 isb(); 68 } 69 70 void sme_disable(cpu_context_t *context) 71 { 72 u_register_t reg; 73 el3_state_t *state; 74 75 /* Get the context state. */ 76 state = get_el3state_ctx(context); 77 78 /* Disable SME, SVE, and FPU since they all share registers. */ 79 reg = read_ctx_reg(state, CTX_CPTR_EL3); 80 reg &= ~ESM_BIT; /* Trap SME */ 81 reg &= ~CPTR_EZ_BIT; /* Trap SVE */ 82 reg |= TFP_BIT; /* Trap FPU/SIMD */ 83 write_ctx_reg(state, CTX_CPTR_EL3, reg); 84 85 /* Disable access to TPIDR2_EL0. */ 86 reg = read_ctx_reg(state, CTX_SCR_EL3); 87 reg &= ~SCR_ENTP2_BIT; 88 write_ctx_reg(state, CTX_SCR_EL3, reg); 89 } 90