1 /* 2 * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <stdbool.h> 8 9 #include <arch.h> 10 #include <arch_helpers.h> 11 #include <common/debug.h> 12 #include <lib/el3_runtime/context_mgmt.h> 13 #include <lib/extensions/sme.h> 14 #include <lib/extensions/sve.h> 15 16 static bool feat_sme_supported(void) 17 { 18 uint64_t features; 19 20 features = read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_SME_SHIFT; 21 return (features & ID_AA64PFR1_EL1_SME_MASK) != 0U; 22 } 23 24 static bool feat_sme_fa64_supported(void) 25 { 26 uint64_t features; 27 28 features = read_id_aa64smfr0_el1(); 29 return (features & ID_AA64SMFR0_EL1_FA64_BIT) != 0U; 30 } 31 32 void sme_enable(cpu_context_t *context) 33 { 34 u_register_t reg; 35 u_register_t cptr_el3; 36 el3_state_t *state; 37 38 /* Make sure SME is implemented in hardware before continuing. */ 39 if (!feat_sme_supported()) { 40 /* Perhaps the hardware supports SVE only */ 41 sve_enable(context); 42 return; 43 } 44 45 /* Get the context state. */ 46 state = get_el3state_ctx(context); 47 48 /* Enable SME in CPTR_EL3. */ 49 reg = read_ctx_reg(state, CTX_CPTR_EL3); 50 reg |= ESM_BIT; 51 write_ctx_reg(state, CTX_CPTR_EL3, reg); 52 53 /* Set the ENTP2 bit in SCR_EL3 to enable access to TPIDR2_EL0. */ 54 reg = read_ctx_reg(state, CTX_SCR_EL3); 55 reg |= SCR_ENTP2_BIT; 56 write_ctx_reg(state, CTX_SCR_EL3, reg); 57 58 /* Set CPTR_EL3.ESM bit so we can write SMCR_EL3 without trapping. */ 59 cptr_el3 = read_cptr_el3(); 60 write_cptr_el3(cptr_el3 | ESM_BIT); 61 62 /* 63 * Set the max LEN value and FA64 bit. This register is set up globally 64 * to be the least restrictive, then lower ELs can restrict as needed 65 * using SMCR_EL2 and SMCR_EL1. 66 */ 67 reg = SMCR_ELX_LEN_MASK; 68 if (feat_sme_fa64_supported()) { 69 VERBOSE("[SME] FA64 enabled\n"); 70 reg |= SMCR_ELX_FA64_BIT; 71 } 72 write_smcr_el3(reg); 73 74 /* Reset CPTR_EL3 value. */ 75 write_cptr_el3(cptr_el3); 76 77 /* Enable SVE/FPU in addition to SME. */ 78 sve_enable(context); 79 } 80 81 void sme_disable(cpu_context_t *context) 82 { 83 u_register_t reg; 84 el3_state_t *state; 85 86 /* Make sure SME is implemented in hardware before continuing. */ 87 if (!feat_sme_supported()) { 88 /* Perhaps the hardware supports SVE only */ 89 sve_disable(context); 90 return; 91 } 92 93 /* Get the context state. */ 94 state = get_el3state_ctx(context); 95 96 /* Disable SME, SVE, and FPU since they all share registers. */ 97 reg = read_ctx_reg(state, CTX_CPTR_EL3); 98 reg &= ~ESM_BIT; /* Trap SME */ 99 reg &= ~CPTR_EZ_BIT; /* Trap SVE */ 100 reg |= TFP_BIT; /* Trap FPU/SIMD */ 101 write_ctx_reg(state, CTX_CPTR_EL3, reg); 102 103 /* Disable access to TPIDR2_EL0. */ 104 reg = read_ctx_reg(state, CTX_SCR_EL3); 105 reg &= ~SCR_ENTP2_BIT; 106 write_ctx_reg(state, CTX_SCR_EL3, reg); 107 } 108