1*dc78e62dSjohpow01 /* 2*dc78e62dSjohpow01 * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. 3*dc78e62dSjohpow01 * 4*dc78e62dSjohpow01 * SPDX-License-Identifier: BSD-3-Clause 5*dc78e62dSjohpow01 */ 6*dc78e62dSjohpow01 7*dc78e62dSjohpow01 #include <stdbool.h> 8*dc78e62dSjohpow01 9*dc78e62dSjohpow01 #include <arch.h> 10*dc78e62dSjohpow01 #include <arch_helpers.h> 11*dc78e62dSjohpow01 #include <common/debug.h> 12*dc78e62dSjohpow01 #include <lib/el3_runtime/context_mgmt.h> 13*dc78e62dSjohpow01 #include <lib/extensions/sme.h> 14*dc78e62dSjohpow01 #include <lib/extensions/sve.h> 15*dc78e62dSjohpow01 16*dc78e62dSjohpow01 static bool feat_sme_supported(void) 17*dc78e62dSjohpow01 { 18*dc78e62dSjohpow01 uint64_t features; 19*dc78e62dSjohpow01 20*dc78e62dSjohpow01 features = read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_SME_SHIFT; 21*dc78e62dSjohpow01 return (features & ID_AA64PFR1_EL1_SME_MASK) != 0U; 22*dc78e62dSjohpow01 } 23*dc78e62dSjohpow01 24*dc78e62dSjohpow01 static bool feat_sme_fa64_supported(void) 25*dc78e62dSjohpow01 { 26*dc78e62dSjohpow01 uint64_t features; 27*dc78e62dSjohpow01 28*dc78e62dSjohpow01 features = read_id_aa64smfr0_el1(); 29*dc78e62dSjohpow01 return (features & ID_AA64SMFR0_EL1_FA64_BIT) != 0U; 30*dc78e62dSjohpow01 } 31*dc78e62dSjohpow01 32*dc78e62dSjohpow01 void sme_enable(cpu_context_t *context) 33*dc78e62dSjohpow01 { 34*dc78e62dSjohpow01 u_register_t reg; 35*dc78e62dSjohpow01 u_register_t cptr_el3; 36*dc78e62dSjohpow01 el3_state_t *state; 37*dc78e62dSjohpow01 38*dc78e62dSjohpow01 /* Make sure SME is implemented in hardware before continuing. */ 39*dc78e62dSjohpow01 if (!feat_sme_supported()) { 40*dc78e62dSjohpow01 return; 41*dc78e62dSjohpow01 } 42*dc78e62dSjohpow01 43*dc78e62dSjohpow01 /* Get the context state. */ 44*dc78e62dSjohpow01 state = get_el3state_ctx(context); 45*dc78e62dSjohpow01 46*dc78e62dSjohpow01 /* Enable SME in CPTR_EL3. */ 47*dc78e62dSjohpow01 reg = read_ctx_reg(state, CTX_CPTR_EL3); 48*dc78e62dSjohpow01 reg |= ESM_BIT; 49*dc78e62dSjohpow01 write_ctx_reg(state, CTX_CPTR_EL3, reg); 50*dc78e62dSjohpow01 51*dc78e62dSjohpow01 /* Set the ENTP2 bit in SCR_EL3 to enable access to TPIDR2_EL0. */ 52*dc78e62dSjohpow01 reg = read_ctx_reg(state, CTX_SCR_EL3); 53*dc78e62dSjohpow01 reg |= SCR_ENTP2_BIT; 54*dc78e62dSjohpow01 write_ctx_reg(state, CTX_SCR_EL3, reg); 55*dc78e62dSjohpow01 56*dc78e62dSjohpow01 /* Set CPTR_EL3.ESM bit so we can write SMCR_EL3 without trapping. */ 57*dc78e62dSjohpow01 cptr_el3 = read_cptr_el3(); 58*dc78e62dSjohpow01 write_cptr_el3(cptr_el3 | ESM_BIT); 59*dc78e62dSjohpow01 60*dc78e62dSjohpow01 /* 61*dc78e62dSjohpow01 * Set the max LEN value and FA64 bit. This register is set up globally 62*dc78e62dSjohpow01 * to be the least restrictive, then lower ELs can restrict as needed 63*dc78e62dSjohpow01 * using SMCR_EL2 and SMCR_EL1. 64*dc78e62dSjohpow01 */ 65*dc78e62dSjohpow01 reg = SMCR_ELX_LEN_MASK; 66*dc78e62dSjohpow01 if (feat_sme_fa64_supported()) { 67*dc78e62dSjohpow01 VERBOSE("[SME] FA64 enabled\n"); 68*dc78e62dSjohpow01 reg |= SMCR_ELX_FA64_BIT; 69*dc78e62dSjohpow01 } 70*dc78e62dSjohpow01 write_smcr_el3(reg); 71*dc78e62dSjohpow01 72*dc78e62dSjohpow01 /* Reset CPTR_EL3 value. */ 73*dc78e62dSjohpow01 write_cptr_el3(cptr_el3); 74*dc78e62dSjohpow01 75*dc78e62dSjohpow01 /* Enable SVE/FPU in addition to SME. */ 76*dc78e62dSjohpow01 sve_enable(context); 77*dc78e62dSjohpow01 } 78*dc78e62dSjohpow01 79*dc78e62dSjohpow01 void sme_disable(cpu_context_t *context) 80*dc78e62dSjohpow01 { 81*dc78e62dSjohpow01 u_register_t reg; 82*dc78e62dSjohpow01 el3_state_t *state; 83*dc78e62dSjohpow01 84*dc78e62dSjohpow01 /* Make sure SME is implemented in hardware before continuing. */ 85*dc78e62dSjohpow01 if (!feat_sme_supported()) { 86*dc78e62dSjohpow01 return; 87*dc78e62dSjohpow01 } 88*dc78e62dSjohpow01 89*dc78e62dSjohpow01 /* Get the context state. */ 90*dc78e62dSjohpow01 state = get_el3state_ctx(context); 91*dc78e62dSjohpow01 92*dc78e62dSjohpow01 /* Disable SME, SVE, and FPU since they all share registers. */ 93*dc78e62dSjohpow01 reg = read_ctx_reg(state, CTX_CPTR_EL3); 94*dc78e62dSjohpow01 reg &= ~ESM_BIT; /* Trap SME */ 95*dc78e62dSjohpow01 reg &= ~CPTR_EZ_BIT; /* Trap SVE */ 96*dc78e62dSjohpow01 reg |= TFP_BIT; /* Trap FPU/SIMD */ 97*dc78e62dSjohpow01 write_ctx_reg(state, CTX_CPTR_EL3, reg); 98*dc78e62dSjohpow01 99*dc78e62dSjohpow01 /* Disable access to TPIDR2_EL0. */ 100*dc78e62dSjohpow01 reg = read_ctx_reg(state, CTX_SCR_EL3); 101*dc78e62dSjohpow01 reg &= ~SCR_ENTP2_BIT; 102*dc78e62dSjohpow01 write_ctx_reg(state, CTX_SCR_EL3, reg); 103*dc78e62dSjohpow01 } 104