1 /* 2 * Copyright (c) 2023-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_features.h> 9 #include <arch_helpers.h> 10 #include <lib/extensions/pmuv3.h> 11 12 static u_register_t init_mdcr_el2_hpmn(u_register_t mdcr_el2) 13 { 14 /* 15 * Initialize MDCR_EL2.HPMN to its hardware reset value so we don't 16 * throw anyone off who expects this to be sensible. 17 */ 18 mdcr_el2 &= ~MDCR_EL2_HPMN_MASK; 19 mdcr_el2 |= ((read_pmcr_el0() >> PMCR_EL0_N_SHIFT) & PMCR_EL0_N_MASK); 20 21 return mdcr_el2; 22 } 23 24 static u_register_t mtpmu_disable_el3(u_register_t mdcr_el3) 25 { 26 if (!is_feat_mtpmu_supported()) { 27 return mdcr_el3; 28 } 29 30 /* 31 * MDCR_EL3.MTPME = 0 32 * FEAT_MTPMU is disabled. The Effective value of PMEVTYPER<n>_EL0.MT is 33 * zero. 34 */ 35 mdcr_el3 &= ~MDCR_MTPME_BIT; 36 37 return mdcr_el3; 38 } 39 40 void pmuv3_enable(cpu_context_t *ctx) 41 { 42 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 43 u_register_t mdcr_el2_val; 44 45 mdcr_el2_val = read_el2_ctx_common(get_el2_sysregs_ctx(ctx), mdcr_el2); 46 mdcr_el2_val = init_mdcr_el2_hpmn(mdcr_el2_val); 47 write_el2_ctx_common(get_el2_sysregs_ctx(ctx), mdcr_el2, mdcr_el2_val); 48 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 49 50 el3_state_t *state = get_el3state_ctx(ctx); 51 u_register_t mdcr_el3_val = read_ctx_reg(state, CTX_MDCR_EL3); 52 53 /* --------------------------------------------------------------------- 54 * MDCR_EL3.MPMX: Set to zero to not affect event counters (when 55 * SPME = 0). 56 * 57 * MDCR_EL3.MCCD: Set to one so that cycle counting by PMCCNTR_EL0 is 58 * prohibited in EL3. This bit is RES0 in versions of the 59 * architecture with FEAT_PMUv3p7 not implemented. 60 * 61 * MDCR_EL3.SCCD: Set to one so that cycle counting by PMCCNTR_EL0 is 62 * prohibited in Secure state. This bit is RES0 in versions of the 63 * architecture with FEAT_PMUv3p5 not implemented. 64 * 65 * MDCR_EL3.SPME: Set to zero so that event counting is prohibited in 66 * Secure state (and explicitly EL3 with later revisions). If ARMv8.2 67 * Debug is not implemented this bit does not have any effect on the 68 * counters unless there is support for the implementation defined 69 * authentication interface ExternalSecureNoninvasiveDebugEnabled(). 70 * 71 * The SPME/MPMX combination is a little tricky. Below is a small 72 * summary if another combination is ever needed: 73 * SPME | MPMX | secure world | EL3 74 * ------------------------------------- 75 * 0 | 0 | disabled | disabled 76 * 1 | 0 | enabled | enabled 77 * 0 | 1 | enabled | disabled 78 * 1 | 1 | enabled | disabled only for counters 0 to 79 * MDCR_EL2.HPMN - 1. Enabled for the rest 80 * 81 * MDCR_EL3.EnPM2: Set to one so that various PMUv3p9 related system 82 * register accesses do not trap to EL3. 83 * 84 * MDCR_EL3.TPM: Set to zero so that EL0, EL1, and EL2 System register 85 * accesses to all Performance Monitors registers do not trap to EL3. 86 */ 87 mdcr_el3_val |= MDCR_SCCD_BIT | MDCR_MCCD_BIT | MDCR_EnPM2_BIT; 88 mdcr_el3_val &= ~(MDCR_MPMX_BIT | MDCR_SPME_BIT | MDCR_TPM_BIT); 89 mdcr_el3_val = mtpmu_disable_el3(mdcr_el3_val); 90 91 write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3_val); 92 } 93 94 void pmuv3_init_el3(void) 95 { 96 /* --------------------------------------------------------------------- 97 * Initialise PMCR_EL0 setting all fields rather than relying 98 * on hw. Some fields are architecturally UNKNOWN on reset. 99 * 100 * PMCR_EL0.DP: Set to one so that the cycle counter, 101 * PMCCNTR_EL0 does not count when event counting is prohibited. 102 * Necessary on PMUv3 <= p7 where MDCR_EL3.{SCCD,MCCD} are not 103 * available 104 * 105 * PMCR_EL0.X: Set to zero to disable export of events. 106 * 107 * PMCR_EL0.C: Set to one to reset PMCCNTR_EL0 to zero. 108 * 109 * PMCR_EL0.P: Set to one to reset each event counter PMEVCNTR<n>_EL0 to 110 * zero. 111 * 112 * PMCR_EL0.E: Set to zero to disable cycle and event counters. 113 * --------------------------------------------------------------------- 114 */ 115 write_pmcr_el0((read_pmcr_el0() | PMCR_EL0_DP_BIT | PMCR_EL0_C_BIT | 116 PMCR_EL0_P_BIT) & ~(PMCR_EL0_X_BIT | PMCR_EL0_E_BIT)); 117 } 118 119 static u_register_t mtpmu_disable_el2(u_register_t mdcr_el2) 120 { 121 if (!is_feat_mtpmu_supported()) { 122 return mdcr_el2; 123 } 124 125 /* 126 * MDCR_EL2.MTPME = 0 127 * FEAT_MTPMU is disabled. The Effective value of PMEVTYPER<n>_EL0.MT is 128 * zero. 129 */ 130 mdcr_el2 &= ~MDCR_EL2_MTPME; 131 132 return mdcr_el2; 133 } 134 135 void pmuv3_init_el2_unused(void) 136 { 137 u_register_t mdcr_el2 = read_mdcr_el2(); 138 139 /* 140 * Initialise MDCR_EL2, setting all fields rather than 141 * relying on hw. Some fields are architecturally 142 * UNKNOWN on reset. 143 * 144 * MDCR_EL2.HLP: Set to one so that event counter overflow, that is 145 * recorded in PMOVSCLR_EL0[0-30], occurs on the increment that changes 146 * PMEVCNTR<n>_EL0[63] from 1 to 0, when ARMv8.5-PMU is implemented. 147 * This bit is RES0 in versions of the architecture earlier than 148 * ARMv8.5, setting it to 1 doesn't have any effect on them. 149 * 150 * MDCR_EL2.HCCD: Set to one to prohibit cycle counting at EL2. This bit 151 * is RES0 in versions of the architecture with FEAT_PMUv3p5 not 152 * implemented. 153 * 154 * MDCR_EL2.HPMD: Set to one so that event counting is 155 * prohibited at EL2 for counter n < MDCR_EL2.HPMN. This bit is RES0 156 * in versions of the architecture with FEAT_PMUv3p1 not implemented. 157 * 158 * MDCR_EL2.HPME: Set to zero to disable event counters for counters 159 * n >= MDCR_EL2.HPMN. 160 * 161 * MDCR_EL2.TPM: Set to zero so that Non-secure EL0 and 162 * EL1 accesses to all Performance Monitors registers 163 * are not trapped to EL2. 164 * 165 * MDCR_EL2.TPMCR: Set to zero so that Non-secure EL0 166 * and EL1 accesses to the PMCR_EL0 or PMCR are not 167 * trapped to EL2. 168 */ 169 mdcr_el2 = (mdcr_el2 | MDCR_EL2_HLP_BIT | MDCR_EL2_HPMD_BIT | 170 MDCR_EL2_HCCD_BIT) & 171 ~(MDCR_EL2_HPME_BIT | MDCR_EL2_TPM_BIT | MDCR_EL2_TPMCR_BIT); 172 mdcr_el2 = init_mdcr_el2_hpmn(mdcr_el2); 173 mdcr_el2 = mtpmu_disable_el2(mdcr_el2); 174 write_mdcr_el2(mdcr_el2); 175 } 176