1*c73686a1SBoyan Karatotev /* 2*c73686a1SBoyan Karatotev * Copyright (c) 2023, Arm Limited. All rights reserved. 3*c73686a1SBoyan Karatotev * 4*c73686a1SBoyan Karatotev * SPDX-License-Identifier: BSD-3-Clause 5*c73686a1SBoyan Karatotev */ 6*c73686a1SBoyan Karatotev 7*c73686a1SBoyan Karatotev #include <arch.h> 8*c73686a1SBoyan Karatotev #include <arch_features.h> 9*c73686a1SBoyan Karatotev #include <arch_helpers.h> 10*c73686a1SBoyan Karatotev #include <lib/extensions/pmuv3.h> 11*c73686a1SBoyan Karatotev 12*c73686a1SBoyan Karatotev /* 13*c73686a1SBoyan Karatotev * Applies to all PMU versions. Name is PMUv3 for compatibility with aarch64 and 14*c73686a1SBoyan Karatotev * to not clash with platforms which reuse the PMU name 15*c73686a1SBoyan Karatotev */ 16*c73686a1SBoyan Karatotev void pmuv3_disable_el3(void) 17*c73686a1SBoyan Karatotev { 18*c73686a1SBoyan Karatotev u_register_t sdcr = read_sdcr(); 19*c73686a1SBoyan Karatotev 20*c73686a1SBoyan Karatotev /* --------------------------------------------------------------------- 21*c73686a1SBoyan Karatotev * Initialise SDCR, setting all the fields rather than relying on hw. 22*c73686a1SBoyan Karatotev * 23*c73686a1SBoyan Karatotev * SDCR.SCCD: Set to one so that cycle counting by PMCCNTR is prohibited 24*c73686a1SBoyan Karatotev * in Secure state. This bit is RES0 in versions of the architecture 25*c73686a1SBoyan Karatotev * earlier than ARMv8.5 26*c73686a1SBoyan Karatotev * 27*c73686a1SBoyan Karatotev * SDCR.SPME: Set to zero so that event counting is prohibited in Secure 28*c73686a1SBoyan Karatotev * state (and explicitly EL3 with later revisions). If ARMv8.2 Debug is 29*c73686a1SBoyan Karatotev * not implemented this bit does not have any effect on the counters 30*c73686a1SBoyan Karatotev * unless there is support for the implementation defined 31*c73686a1SBoyan Karatotev * authentication interface ExternalSecureNoninvasiveDebugEnabled(). 32*c73686a1SBoyan Karatotev * --------------------------------------------------------------------- 33*c73686a1SBoyan Karatotev */ 34*c73686a1SBoyan Karatotev sdcr = (sdcr | SDCR_SCCD_BIT) & ~SDCR_SPME_BIT; 35*c73686a1SBoyan Karatotev write_sdcr(sdcr); 36*c73686a1SBoyan Karatotev 37*c73686a1SBoyan Karatotev /* --------------------------------------------------------------------- 38*c73686a1SBoyan Karatotev * Initialise PMCR, setting all fields rather than relying 39*c73686a1SBoyan Karatotev * on hw. Some fields are architecturally UNKNOWN on reset. 40*c73686a1SBoyan Karatotev * 41*c73686a1SBoyan Karatotev * PMCR.DP: Set to one to prohibit cycle counting whilst in Secure mode. 42*c73686a1SBoyan Karatotev * 43*c73686a1SBoyan Karatotev * PMCR.X: Set to zero to disable export of events. 44*c73686a1SBoyan Karatotev * 45*c73686a1SBoyan Karatotev * PMCR.C: Set to one to reset PMCCNTR. 46*c73686a1SBoyan Karatotev * 47*c73686a1SBoyan Karatotev * PMCR.P: Set to one to reset each event counter PMEVCNTR<n> to zero. 48*c73686a1SBoyan Karatotev * 49*c73686a1SBoyan Karatotev * PMCR.E: Set to zero to disable cycle and event counters. 50*c73686a1SBoyan Karatotev * --------------------------------------------------------------------- 51*c73686a1SBoyan Karatotev */ 52*c73686a1SBoyan Karatotev 53*c73686a1SBoyan Karatotev write_pmcr(read_pmcr() | PMCR_DP_BIT | PMCR_C_BIT | PMCR_P_BIT | 54*c73686a1SBoyan Karatotev ~(PMCR_X_BIT | PMCR_E_BIT)); 55*c73686a1SBoyan Karatotev } 56