1 /* 2 * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <stdbool.h> 10 #include <string.h> 11 12 #include <platform_def.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <arch_features.h> 17 #include <bl31/interrupt_mgmt.h> 18 #include <common/bl_common.h> 19 #include <common/debug.h> 20 #include <context.h> 21 #include <drivers/arm/gicv3.h> 22 #include <lib/cpus/cpu_ops.h> 23 #include <lib/cpus/errata.h> 24 #include <lib/el3_runtime/context_mgmt.h> 25 #include <lib/el3_runtime/cpu_data.h> 26 #include <lib/el3_runtime/pubsub_events.h> 27 #include <lib/extensions/amu.h> 28 #include <lib/extensions/brbe.h> 29 #include <lib/extensions/debug_v8p9.h> 30 #include <lib/extensions/fgt2.h> 31 #include <lib/extensions/fpmr.h> 32 #include <lib/extensions/mpam.h> 33 #include <lib/extensions/pauth.h> 34 #include <lib/extensions/pmuv3.h> 35 #include <lib/extensions/sme.h> 36 #include <lib/extensions/spe.h> 37 #include <lib/extensions/sve.h> 38 #include <lib/extensions/sysreg128.h> 39 #include <lib/extensions/sys_reg_trace.h> 40 #include <lib/extensions/tcr2.h> 41 #include <lib/extensions/trbe.h> 42 #include <lib/extensions/trf.h> 43 #include <lib/utils.h> 44 45 #if ENABLE_FEAT_TWED 46 /* Make sure delay value fits within the range(0-15) */ 47 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check); 48 #endif /* ENABLE_FEAT_TWED */ 49 50 per_world_context_t per_world_context[CPU_DATA_CONTEXT_NUM]; 51 static bool has_secure_perworld_init; 52 53 static void manage_extensions_nonsecure(cpu_context_t *ctx); 54 static void manage_extensions_secure(cpu_context_t *ctx); 55 static void manage_extensions_secure_per_world(void); 56 57 #if ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) 58 static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep) 59 { 60 u_register_t sctlr_elx, actlr_elx; 61 62 /* 63 * Initialise SCTLR_EL1 to the reset value corresponding to the target 64 * execution state setting all fields rather than relying on the hw. 65 * Some fields have architecturally UNKNOWN reset values and these are 66 * set to zero. 67 * 68 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 69 * 70 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 71 * required by PSCI specification) 72 */ 73 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 74 if (GET_RW(ep->spsr) == MODE_RW_64) { 75 sctlr_elx |= SCTLR_EL1_RES1; 76 } else { 77 /* 78 * If the target execution state is AArch32 then the following 79 * fields need to be set. 80 * 81 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 82 * instructions are not trapped to EL1. 83 * 84 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 85 * instructions are not trapped to EL1. 86 * 87 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 88 * CP15DMB, CP15DSB, and CP15ISB instructions. 89 */ 90 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 91 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 92 } 93 94 /* 95 * If workaround of errata 764081 for Cortex-A75 is used then set 96 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 97 */ 98 if (errata_a75_764081_applies()) { 99 sctlr_elx |= SCTLR_IESB_BIT; 100 } 101 102 /* Store the initialised SCTLR_EL1 value in the cpu_context */ 103 write_ctx_sctlr_el1_reg_errata(ctx, sctlr_elx); 104 105 /* 106 * Base the context ACTLR_EL1 on the current value, as it is 107 * implementation defined. The context restore process will write 108 * the value from the context to the actual register and can cause 109 * problems for processor cores that don't expect certain bits to 110 * be zero. 111 */ 112 actlr_elx = read_actlr_el1(); 113 write_el1_ctx_common(get_el1_sysregs_ctx(ctx), actlr_el1, actlr_elx); 114 } 115 #endif /* (IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS)) */ 116 117 /****************************************************************************** 118 * This function performs initializations that are specific to SECURE state 119 * and updates the cpu context specified by 'ctx'. 120 *****************************************************************************/ 121 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep) 122 { 123 u_register_t scr_el3; 124 el3_state_t *state; 125 126 state = get_el3state_ctx(ctx); 127 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 128 129 #if defined(IMAGE_BL31) && !defined(SPD_spmd) 130 /* 131 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 132 * indicated by the interrupt routing model for BL31. 133 */ 134 scr_el3 |= get_scr_el3_from_routing_model(SECURE); 135 #endif 136 137 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 138 if (is_feat_mte2_supported()) { 139 scr_el3 |= SCR_ATA_BIT; 140 } 141 142 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 143 144 /* 145 * Initialize EL1 context registers unless SPMC is running 146 * at S-EL2. 147 */ 148 #if (!SPMD_SPM_AT_SEL2) 149 setup_el1_context(ctx, ep); 150 #endif 151 152 manage_extensions_secure(ctx); 153 154 /** 155 * manage_extensions_secure_per_world api has to be executed once, 156 * as the registers getting initialised, maintain constant value across 157 * all the cpus for the secure world. 158 * Henceforth, this check ensures that the registers are initialised once 159 * and avoids re-initialization from multiple cores. 160 */ 161 if (!has_secure_perworld_init) { 162 manage_extensions_secure_per_world(); 163 } 164 } 165 166 #if ENABLE_RME 167 /****************************************************************************** 168 * This function performs initializations that are specific to REALM state 169 * and updates the cpu context specified by 'ctx'. 170 *****************************************************************************/ 171 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep) 172 { 173 u_register_t scr_el3; 174 el3_state_t *state; 175 176 state = get_el3state_ctx(ctx); 177 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 178 179 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT; 180 181 /* CSV2 version 2 and above */ 182 if (is_feat_csv2_2_supported()) { 183 /* Enable access to the SCXTNUM_ELx registers. */ 184 scr_el3 |= SCR_EnSCXT_BIT; 185 } 186 187 if (is_feat_sctlr2_supported()) { 188 /* Set the SCTLR2En bit in SCR_EL3 to enable access to 189 * SCTLR2_ELx registers. 190 */ 191 scr_el3 |= SCR_SCTLR2En_BIT; 192 } 193 194 if (is_feat_d128_supported()) { 195 /* 196 * Set the D128En bit in SCR_EL3 to enable access to 128-bit 197 * versions of TTBR0_EL1, TTBR1_EL1, RCWMASK_EL1, RCWSMASK_EL1, 198 * PAR_EL1 and TTBR1_EL2, TTBR0_EL2 and VTTBR_EL2 registers. 199 */ 200 scr_el3 |= SCR_D128En_BIT; 201 } 202 203 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 204 205 if (is_feat_fgt2_supported()) { 206 fgt2_enable(ctx); 207 } 208 209 if (is_feat_debugv8p9_supported()) { 210 debugv8p9_extended_bp_wp_enable(ctx); 211 } 212 213 if (is_feat_brbe_supported()) { 214 brbe_enable(ctx); 215 } 216 217 } 218 #endif /* ENABLE_RME */ 219 220 /****************************************************************************** 221 * This function performs initializations that are specific to NON-SECURE state 222 * and updates the cpu context specified by 'ctx'. 223 *****************************************************************************/ 224 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep) 225 { 226 u_register_t scr_el3; 227 el3_state_t *state; 228 229 state = get_el3state_ctx(ctx); 230 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 231 232 /* SCR_NS: Set the NS bit */ 233 scr_el3 |= SCR_NS_BIT; 234 235 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 236 if (is_feat_mte2_supported()) { 237 scr_el3 |= SCR_ATA_BIT; 238 } 239 240 /* 241 * Pointer Authentication feature, if present, is always enabled by 242 * default for Non secure lower exception levels. We do not have an 243 * explicit flag to set it. To prevent the leakage between the worlds 244 * during world switch, we enable it only for the non-secure world. 245 * 246 * CTX_INCLUDE_PAUTH_REGS flag, is explicitly used to enable for lower 247 * exception levels of secure and realm worlds. 248 * 249 * If the Secure/realm world wants to use pointer authentication, 250 * CTX_INCLUDE_PAUTH_REGS must be explicitly set to 1, in which case 251 * it will be enabled globally for all the contexts. 252 * 253 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 254 * other than EL3 255 * 256 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 257 * than EL3 258 */ 259 if (!is_ctx_pauth_supported()) { 260 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 261 } 262 263 #if HANDLE_EA_EL3_FIRST_NS 264 /* SCR_EL3.EA: Route External Abort and SError Interrupt to EL3. */ 265 scr_el3 |= SCR_EA_BIT; 266 #endif 267 268 #if RAS_TRAP_NS_ERR_REC_ACCESS 269 /* 270 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 271 * and RAS ERX registers from EL1 and EL2(from any security state) 272 * are trapped to EL3. 273 * Set here to trap only for NS EL1/EL2 274 */ 275 scr_el3 |= SCR_TERR_BIT; 276 #endif 277 278 /* CSV2 version 2 and above */ 279 if (is_feat_csv2_2_supported()) { 280 /* Enable access to the SCXTNUM_ELx registers. */ 281 scr_el3 |= SCR_EnSCXT_BIT; 282 } 283 284 #ifdef IMAGE_BL31 285 /* 286 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 287 * indicated by the interrupt routing model for BL31. 288 */ 289 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE); 290 #endif 291 292 if (is_feat_the_supported()) { 293 /* Set the RCWMASKEn bit in SCR_EL3 to enable access to 294 * RCWMASK_EL1 and RCWSMASK_EL1 registers. 295 */ 296 scr_el3 |= SCR_RCWMASKEn_BIT; 297 } 298 299 if (is_feat_sctlr2_supported()) { 300 /* Set the SCTLR2En bit in SCR_EL3 to enable access to 301 * SCTLR2_ELx registers. 302 */ 303 scr_el3 |= SCR_SCTLR2En_BIT; 304 } 305 306 if (is_feat_d128_supported()) { 307 /* Set the D128En bit in SCR_EL3 to enable access to 128-bit 308 * versions of TTBR0_EL1, TTBR1_EL1, RCWMASK_EL1, RCWSMASK_EL1, 309 * PAR_EL1 and TTBR1_EL2, TTBR0_EL2 and VTTBR_EL2 registers. 310 */ 311 scr_el3 |= SCR_D128En_BIT; 312 } 313 314 if (is_feat_fpmr_supported()) { 315 /* Set the EnFPM bit in SCR_EL3 to enable access to FPMR 316 * register. 317 */ 318 scr_el3 |= SCR_EnFPM_BIT; 319 } 320 321 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 322 323 /* Initialize EL2 context registers */ 324 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 325 326 /* 327 * Initialize SCTLR_EL2 context register with reset value. 328 */ 329 write_el2_ctx_common(get_el2_sysregs_ctx(ctx), sctlr_el2, SCTLR_EL2_RES1); 330 331 if (is_feat_hcx_supported()) { 332 /* 333 * Initialize register HCRX_EL2 with its init value. 334 * As the value of HCRX_EL2 is UNKNOWN on reset, there is a 335 * chance that this can lead to unexpected behavior in lower 336 * ELs that have not been updated since the introduction of 337 * this feature if not properly initialized, especially when 338 * it comes to those bits that enable/disable traps. 339 */ 340 write_el2_ctx_hcx(get_el2_sysregs_ctx(ctx), hcrx_el2, 341 HCRX_EL2_INIT_VAL); 342 } 343 344 if (is_feat_fgt_supported()) { 345 /* 346 * Initialize HFG*_EL2 registers with a default value so legacy 347 * systems unaware of FEAT_FGT do not get trapped due to their lack 348 * of initialization for this feature. 349 */ 350 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgitr_el2, 351 HFGITR_EL2_INIT_VAL); 352 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgrtr_el2, 353 HFGRTR_EL2_INIT_VAL); 354 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgwtr_el2, 355 HFGWTR_EL2_INIT_VAL); 356 } 357 #else 358 /* Initialize EL1 context registers */ 359 setup_el1_context(ctx, ep); 360 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 361 362 manage_extensions_nonsecure(ctx); 363 } 364 365 /******************************************************************************* 366 * The following function performs initialization of the cpu_context 'ctx' 367 * for first use that is common to all security states, and sets the 368 * initial entrypoint state as specified by the entry_point_info structure. 369 * 370 * The EE and ST attributes are used to configure the endianness and secure 371 * timer availability for the new execution context. 372 ******************************************************************************/ 373 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 374 { 375 u_register_t scr_el3; 376 u_register_t mdcr_el3; 377 el3_state_t *state; 378 gp_regs_t *gp_regs; 379 380 state = get_el3state_ctx(ctx); 381 382 /* Clear any residual register values from the context */ 383 zeromem(ctx, sizeof(*ctx)); 384 385 /* 386 * The lower-EL context is zeroed so that no stale values leak to a world. 387 * It is assumed that an all-zero lower-EL context is good enough for it 388 * to boot correctly. However, there are very few registers where this 389 * is not true and some values need to be recreated. 390 */ 391 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 392 el2_sysregs_t *el2_ctx = get_el2_sysregs_ctx(ctx); 393 394 /* 395 * These bits are set in the gicv3 driver. Losing them (especially the 396 * SRE bit) is problematic for all worlds. Henceforth recreate them. 397 */ 398 u_register_t icc_sre_el2_val = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | 399 ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT; 400 write_el2_ctx_common(el2_ctx, icc_sre_el2, icc_sre_el2_val); 401 402 /* 403 * The actlr_el2 register can be initialized in platform's reset handler 404 * and it may contain access control bits (e.g. CLUSTERPMUEN bit). 405 */ 406 write_el2_ctx_common(el2_ctx, actlr_el2, read_actlr_el2()); 407 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 408 409 /* Start with a clean SCR_EL3 copy as all relevant values are set */ 410 scr_el3 = SCR_RESET_VAL; 411 412 /* 413 * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at 414 * EL2, EL1 and EL0 are not trapped to EL3. 415 * 416 * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at 417 * EL2, EL1 and EL0 are not trapped to EL3. 418 * 419 * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from 420 * both Security states and both Execution states. 421 * 422 * SCR_EL3.SIF: Set to one to disable secure instruction execution from 423 * Non-secure memory. 424 */ 425 scr_el3 &= ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT); 426 427 scr_el3 |= SCR_SIF_BIT; 428 429 /* 430 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 431 * Exception level as specified by SPSR. 432 */ 433 if (GET_RW(ep->spsr) == MODE_RW_64) { 434 scr_el3 |= SCR_RW_BIT; 435 } 436 437 /* 438 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 439 * Secure timer registers to EL3, from AArch64 state only, if specified 440 * by the entrypoint attributes. If SEL2 is present and enabled, the ST 441 * bit always behaves as 1 (i.e. secure physical timer register access 442 * is not trapped) 443 */ 444 if (EP_GET_ST(ep->h.attr) != 0U) { 445 scr_el3 |= SCR_ST_BIT; 446 } 447 448 /* 449 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting 450 * SCR_EL3.HXEn. 451 */ 452 if (is_feat_hcx_supported()) { 453 scr_el3 |= SCR_HXEn_BIT; 454 } 455 456 /* 457 * If FEAT_LS64_ACCDATA is enabled, enable access to ACCDATA_EL1 by 458 * setting SCR_EL3.ADEn and allow the ST64BV0 instruction by setting 459 * SCR_EL3.EnAS0. 460 */ 461 if (is_feat_ls64_accdata_supported()) { 462 scr_el3 |= SCR_ADEn_BIT | SCR_EnAS0_BIT; 463 } 464 465 /* 466 * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS 467 * registers are trapped to EL3. 468 */ 469 if (is_feat_rng_trap_supported()) { 470 scr_el3 |= SCR_TRNDR_BIT; 471 } 472 473 #if FAULT_INJECTION_SUPPORT 474 /* Enable fault injection from lower ELs */ 475 scr_el3 |= SCR_FIEN_BIT; 476 #endif 477 478 /* 479 * Enable Pointer Authentication globally for all the worlds. 480 * 481 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 482 * other than EL3 483 * 484 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 485 * than EL3 486 */ 487 if (is_ctx_pauth_supported()) { 488 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 489 } 490 491 /* 492 * SCR_EL3.PIEN: Enable permission indirection and overlay 493 * registers for AArch64 if present. 494 */ 495 if (is_feat_sxpie_supported() || is_feat_sxpoe_supported()) { 496 scr_el3 |= SCR_PIEN_BIT; 497 } 498 499 /* 500 * SCR_EL3.GCSEn: Enable GCS registers for AArch64 if present. 501 */ 502 if ((is_feat_gcs_supported()) && (GET_RW(ep->spsr) == MODE_RW_64)) { 503 scr_el3 |= SCR_GCSEn_BIT; 504 } 505 506 /* 507 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 508 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 509 * next mode is Hyp. 510 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 511 * same conditions as HVC instructions and when the processor supports 512 * ARMv8.6-FGT. 513 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 514 * CNTPOFF_EL2 register under the same conditions as HVC instructions 515 * and when the processor supports ECV. 516 */ 517 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 518 || ((GET_RW(ep->spsr) != MODE_RW_64) 519 && (GET_M32(ep->spsr) == MODE32_hyp))) { 520 scr_el3 |= SCR_HCE_BIT; 521 522 if (is_feat_fgt_supported()) { 523 scr_el3 |= SCR_FGTEN_BIT; 524 } 525 526 if (is_feat_ecv_supported()) { 527 scr_el3 |= SCR_ECVEN_BIT; 528 } 529 } 530 531 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 532 if (is_feat_twed_supported()) { 533 /* Set delay in SCR_EL3 */ 534 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 535 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK) 536 << SCR_TWEDEL_SHIFT); 537 538 /* Enable WFE delay */ 539 scr_el3 |= SCR_TWEDEn_BIT; 540 } 541 542 #if IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2 543 /* Enable S-EL2 if FEAT_SEL2 is implemented for all the contexts. */ 544 if (is_feat_sel2_supported()) { 545 scr_el3 |= SCR_EEL2_BIT; 546 } 547 #endif /* (IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2) */ 548 549 if (is_feat_mec_supported()) { 550 scr_el3 |= SCR_MECEn_BIT; 551 } 552 553 /* 554 * Populate EL3 state so that we've the right context 555 * before doing ERET 556 */ 557 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 558 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 559 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 560 561 /* Start with a clean MDCR_EL3 copy as all relevant values are set */ 562 mdcr_el3 = MDCR_EL3_RESET_VAL; 563 564 /* --------------------------------------------------------------------- 565 * Initialise MDCR_EL3, setting all fields rather than relying on hw. 566 * Some fields are architecturally UNKNOWN on reset. 567 * 568 * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug. 569 * Debug exceptions, other than Breakpoint Instruction exceptions, are 570 * disabled from all ELs in Secure state. 571 * 572 * MDCR_EL3.SPD32: Set to 0b10 to disable AArch32 Secure self-hosted 573 * privileged debug from S-EL1. 574 * 575 * MDCR_EL3.TDOSA: Set to zero so that EL2 and EL2 System register 576 * access to the powerdown debug registers do not trap to EL3. 577 * 578 * MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the 579 * debug registers, other than those registers that are controlled by 580 * MDCR_EL3.TDOSA. 581 */ 582 mdcr_el3 |= ((MDCR_SDD_BIT | MDCR_SPD32(MDCR_SPD32_DISABLE)) 583 & ~(MDCR_TDA_BIT | MDCR_TDOSA_BIT)) ; 584 write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3); 585 586 #if IMAGE_BL31 587 /* Enable FEAT_TRF for Non-Secure and prohibit for Secure state. */ 588 if (is_feat_trf_supported()) { 589 trf_enable(ctx); 590 } 591 592 if (is_feat_tcr2_supported()) { 593 tcr2_enable(ctx); 594 } 595 596 pmuv3_enable(ctx); 597 #endif /* IMAGE_BL31 */ 598 599 /* 600 * Store the X0-X7 value from the entrypoint into the context 601 * Use memcpy as we are in control of the layout of the structures 602 */ 603 gp_regs = get_gpregs_ctx(ctx); 604 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 605 } 606 607 /******************************************************************************* 608 * Context management library initialization routine. This library is used by 609 * runtime services to share pointers to 'cpu_context' structures for secure 610 * non-secure and realm states. Management of the structures and their associated 611 * memory is not done by the context management library e.g. the PSCI service 612 * manages the cpu context used for entry from and exit to the non-secure state. 613 * The Secure payload dispatcher service manages the context(s) corresponding to 614 * the secure state. It also uses this library to get access to the non-secure 615 * state cpu context pointers. 616 * Lastly, this library provides the API to make SP_EL3 point to the cpu context 617 * which will be used for programming an entry into a lower EL. The same context 618 * will be used to save state upon exception entry from that EL. 619 ******************************************************************************/ 620 void __init cm_init(void) 621 { 622 /* 623 * The context management library has only global data to initialize, but 624 * that will be done when the BSS is zeroed out. 625 */ 626 } 627 628 /******************************************************************************* 629 * This is the high-level function used to initialize the cpu_context 'ctx' for 630 * first use. It performs initializations that are common to all security states 631 * and initializations specific to the security state specified in 'ep' 632 ******************************************************************************/ 633 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 634 { 635 unsigned int security_state; 636 637 assert(ctx != NULL); 638 639 /* 640 * Perform initializations that are common 641 * to all security states 642 */ 643 setup_context_common(ctx, ep); 644 645 security_state = GET_SECURITY_STATE(ep->h.attr); 646 647 /* Perform security state specific initializations */ 648 switch (security_state) { 649 case SECURE: 650 setup_secure_context(ctx, ep); 651 break; 652 #if ENABLE_RME 653 case REALM: 654 setup_realm_context(ctx, ep); 655 break; 656 #endif 657 case NON_SECURE: 658 setup_ns_context(ctx, ep); 659 break; 660 default: 661 ERROR("Invalid security state\n"); 662 panic(); 663 break; 664 } 665 } 666 667 /******************************************************************************* 668 * Enable architecture extensions for EL3 execution. This function only updates 669 * registers in-place which are expected to either never change or be 670 * overwritten by el3_exit. Expects the core_pos of the current core as argument. 671 ******************************************************************************/ 672 #if IMAGE_BL31 673 void cm_manage_extensions_el3(unsigned int my_idx) 674 { 675 if (is_feat_sve_supported()) { 676 sve_init_el3(); 677 } 678 679 if (is_feat_amu_supported()) { 680 amu_init_el3(my_idx); 681 } 682 683 if (is_feat_sme_supported()) { 684 sme_init_el3(); 685 } 686 687 pmuv3_init_el3(); 688 } 689 #endif /* IMAGE_BL31 */ 690 691 /****************************************************************************** 692 * Function to initialise the registers with the RESET values in the context 693 * memory, which are maintained per world. 694 ******************************************************************************/ 695 #if IMAGE_BL31 696 void cm_el3_arch_init_per_world(per_world_context_t *per_world_ctx) 697 { 698 /* 699 * Initialise CPTR_EL3, setting all fields rather than relying on hw. 700 * 701 * CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers 702 * by Advanced SIMD, floating-point or SVE instructions (if 703 * implemented) do not trap to EL3. 704 * 705 * CPTR_EL3.TCPAC: Set to zero so that accesses to CPACR_EL1, 706 * CPTR_EL2,CPACR, or HCPTR do not trap to EL3. 707 */ 708 uint64_t cptr_el3 = CPTR_EL3_RESET_VAL & ~(TCPAC_BIT | TFP_BIT); 709 710 per_world_ctx->ctx_cptr_el3 = cptr_el3; 711 712 /* 713 * Initialize MPAM3_EL3 to its default reset value 714 * 715 * MPAM3_EL3_RESET_VAL sets the MPAM3_EL3.TRAPLOWER bit that forces 716 * all lower ELn MPAM3_EL3 register access to, trap to EL3 717 */ 718 719 per_world_ctx->ctx_mpam3_el3 = MPAM3_EL3_RESET_VAL; 720 } 721 #endif /* IMAGE_BL31 */ 722 723 /******************************************************************************* 724 * Initialise per_world_context for Non-Secure world. 725 * This function enables the architecture extensions, which have same value 726 * across the cores for the non-secure world. 727 ******************************************************************************/ 728 #if IMAGE_BL31 729 void manage_extensions_nonsecure_per_world(void) 730 { 731 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_NS]); 732 733 if (is_feat_sme_supported()) { 734 sme_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 735 } 736 737 if (is_feat_sve_supported()) { 738 sve_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 739 } 740 741 if (is_feat_amu_supported()) { 742 amu_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 743 } 744 745 if (is_feat_sys_reg_trace_supported()) { 746 sys_reg_trace_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 747 } 748 749 if (is_feat_mpam_supported()) { 750 mpam_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 751 } 752 753 if (is_feat_fpmr_supported()) { 754 fpmr_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 755 } 756 } 757 #endif /* IMAGE_BL31 */ 758 759 /******************************************************************************* 760 * Initialise per_world_context for Secure world. 761 * This function enables the architecture extensions, which have same value 762 * across the cores for the secure world. 763 ******************************************************************************/ 764 static void manage_extensions_secure_per_world(void) 765 { 766 #if IMAGE_BL31 767 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 768 769 if (is_feat_sme_supported()) { 770 771 if (ENABLE_SME_FOR_SWD) { 772 /* 773 * Enable SME, SVE, FPU/SIMD in secure context, SPM must ensure 774 * SME, SVE, and FPU/SIMD context properly managed. 775 */ 776 sme_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 777 } else { 778 /* 779 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 780 * world can safely use the associated registers. 781 */ 782 sme_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 783 } 784 } 785 if (is_feat_sve_supported()) { 786 if (ENABLE_SVE_FOR_SWD) { 787 /* 788 * Enable SVE and FPU in secure context, SPM must ensure 789 * that the SVE and FPU register contexts are properly managed. 790 */ 791 sve_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 792 } else { 793 /* 794 * Disable SVE and FPU in secure context so non-secure world 795 * can safely use them. 796 */ 797 sve_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 798 } 799 } 800 801 /* NS can access this but Secure shouldn't */ 802 if (is_feat_sys_reg_trace_supported()) { 803 sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 804 } 805 806 has_secure_perworld_init = true; 807 #endif /* IMAGE_BL31 */ 808 } 809 810 /******************************************************************************* 811 * Enable architecture extensions on first entry to Non-secure world. 812 ******************************************************************************/ 813 static void manage_extensions_nonsecure(cpu_context_t *ctx) 814 { 815 #if IMAGE_BL31 816 /* NOTE: registers are not context switched */ 817 if (is_feat_amu_supported()) { 818 amu_enable(ctx); 819 } 820 821 if (is_feat_sme_supported()) { 822 sme_enable(ctx); 823 } 824 825 if (is_feat_fgt2_supported()) { 826 fgt2_enable(ctx); 827 } 828 829 if (is_feat_debugv8p9_supported()) { 830 debugv8p9_extended_bp_wp_enable(ctx); 831 } 832 833 /* 834 * SPE, TRBE, and BRBE have multi-field enables that affect which world 835 * they apply to. Despite this, it is useful to ignore these for 836 * simplicity in determining the feature's per world enablement status. 837 * This is only possible when context is written per-world. Relied on 838 * by SMCCC_ARCH_FEATURE_AVAILABILITY 839 */ 840 if (is_feat_spe_supported()) { 841 spe_enable(ctx); 842 } 843 844 if (!check_if_trbe_disable_affected_core()) { 845 if (is_feat_trbe_supported()) { 846 trbe_enable(ctx); 847 } 848 } 849 850 if (is_feat_brbe_supported()) { 851 brbe_enable(ctx); 852 } 853 #endif /* IMAGE_BL31 */ 854 } 855 856 #if INIT_UNUSED_NS_EL2 857 /******************************************************************************* 858 * Enable architecture extensions in-place at EL2 on first entry to Non-secure 859 * world when EL2 is empty and unused. 860 ******************************************************************************/ 861 static void manage_extensions_nonsecure_el2_unused(void) 862 { 863 #if IMAGE_BL31 864 if (is_feat_spe_supported()) { 865 spe_init_el2_unused(); 866 } 867 868 if (is_feat_amu_supported()) { 869 amu_init_el2_unused(); 870 } 871 872 if (is_feat_mpam_supported()) { 873 mpam_init_el2_unused(); 874 } 875 876 if (is_feat_trbe_supported()) { 877 trbe_init_el2_unused(); 878 } 879 880 if (is_feat_sys_reg_trace_supported()) { 881 sys_reg_trace_init_el2_unused(); 882 } 883 884 if (is_feat_trf_supported()) { 885 trf_init_el2_unused(); 886 } 887 888 pmuv3_init_el2_unused(); 889 890 if (is_feat_sve_supported()) { 891 sve_init_el2_unused(); 892 } 893 894 if (is_feat_sme_supported()) { 895 sme_init_el2_unused(); 896 } 897 898 if (is_feat_mops_supported() && is_feat_hcx_supported()) { 899 write_hcrx_el2(read_hcrx_el2() | HCRX_EL2_MSCEn_BIT); 900 } 901 902 if (is_feat_pauth_supported()) { 903 pauth_enable_el2(); 904 } 905 #endif /* IMAGE_BL31 */ 906 } 907 #endif /* INIT_UNUSED_NS_EL2 */ 908 909 /******************************************************************************* 910 * Enable architecture extensions on first entry to Secure world. 911 ******************************************************************************/ 912 static void manage_extensions_secure(cpu_context_t *ctx) 913 { 914 #if IMAGE_BL31 915 if (is_feat_sme_supported()) { 916 if (ENABLE_SME_FOR_SWD) { 917 /* 918 * Enable SME, SVE, FPU/SIMD in secure context, secure manager 919 * must ensure SME, SVE, and FPU/SIMD context properly managed. 920 */ 921 sme_init_el3(); 922 sme_enable(ctx); 923 } else { 924 /* 925 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 926 * world can safely use the associated registers. 927 */ 928 sme_disable(ctx); 929 } 930 } 931 932 /* 933 * SPE and TRBE cannot be fully disabled from EL3 registers alone, only 934 * sysreg access can. In case the EL1 controls leave them active on 935 * context switch, we want the owning security state to be NS so Secure 936 * can't be DOSed. 937 */ 938 if (is_feat_spe_supported()) { 939 spe_disable(ctx); 940 } 941 942 if (is_feat_trbe_supported()) { 943 trbe_disable(ctx); 944 } 945 #endif /* IMAGE_BL31 */ 946 } 947 948 /******************************************************************************* 949 * The following function initializes the cpu_context for the current CPU 950 * for first use, and sets the initial entrypoint state as specified by the 951 * entry_point_info structure. 952 ******************************************************************************/ 953 void cm_init_my_context(const entry_point_info_t *ep) 954 { 955 cpu_context_t *ctx; 956 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 957 cm_setup_context(ctx, ep); 958 } 959 960 /* EL2 present but unused, need to disable safely. SCTLR_EL2 can be ignored */ 961 static void init_nonsecure_el2_unused(cpu_context_t *ctx) 962 { 963 #if INIT_UNUSED_NS_EL2 964 u_register_t hcr_el2 = HCR_RESET_VAL; 965 u_register_t mdcr_el2; 966 u_register_t scr_el3; 967 968 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 969 970 /* Set EL2 register width: Set HCR_EL2.RW to match SCR_EL3.RW */ 971 if ((scr_el3 & SCR_RW_BIT) != 0U) { 972 hcr_el2 |= HCR_RW_BIT; 973 } 974 975 write_hcr_el2(hcr_el2); 976 977 /* 978 * Initialise CPTR_EL2 setting all fields rather than relying on the hw. 979 * All fields have architecturally UNKNOWN reset values. 980 */ 981 write_cptr_el2(CPTR_EL2_RESET_VAL); 982 983 /* 984 * Initialise CNTHCTL_EL2. All fields are architecturally UNKNOWN on 985 * reset and are set to zero except for field(s) listed below. 986 * 987 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to Hyp mode of 988 * Non-secure EL0 and EL1 accesses to the physical timer registers. 989 * 990 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to Hyp mode of 991 * Non-secure EL0 and EL1 accesses to the physical counter registers. 992 */ 993 write_cnthctl_el2(CNTHCTL_RESET_VAL | EL1PCEN_BIT | EL1PCTEN_BIT); 994 995 /* 996 * Initialise CNTVOFF_EL2 to zero as it resets to an architecturally 997 * UNKNOWN value. 998 */ 999 write_cntvoff_el2(0); 1000 1001 /* 1002 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and MPIDR_EL1 1003 * respectively. 1004 */ 1005 write_vpidr_el2(read_midr_el1()); 1006 write_vmpidr_el2(read_mpidr_el1()); 1007 1008 /* 1009 * Initialise VTTBR_EL2. All fields are architecturally UNKNOWN on reset. 1010 * 1011 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 2 address 1012 * translation is disabled, cache maintenance operations depend on the 1013 * VMID. 1014 * 1015 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address translation is 1016 * disabled. 1017 */ 1018 write_vttbr_el2(VTTBR_RESET_VAL & 1019 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) | 1020 (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 1021 1022 /* 1023 * Initialise MDCR_EL2, setting all fields rather than relying on hw. 1024 * Some fields are architecturally UNKNOWN on reset. 1025 * 1026 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and EL1 System 1027 * register accesses to the Debug ROM registers are not trapped to EL2. 1028 * 1029 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 System register 1030 * accesses to the powerdown debug registers are not trapped to EL2. 1031 * 1032 * MDCR_EL2.TDA: Set to zero so that System register accesses to the 1033 * debug registers do not trap to EL2. 1034 * 1035 * MDCR_EL2.TDE: Set to zero so that debug exceptions are not routed to 1036 * EL2. 1037 */ 1038 mdcr_el2 = MDCR_EL2_RESET_VAL & 1039 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | MDCR_EL2_TDA_BIT | 1040 MDCR_EL2_TDE_BIT); 1041 1042 write_mdcr_el2(mdcr_el2); 1043 1044 /* 1045 * Initialise HSTR_EL2. All fields are architecturally UNKNOWN on reset. 1046 * 1047 * HSTR_EL2.T<n>: Set all these fields to zero so that Non-secure EL0 or 1048 * EL1 accesses to System registers do not trap to EL2. 1049 */ 1050 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 1051 1052 /* 1053 * Initialise CNTHP_CTL_EL2. All fields are architecturally UNKNOWN on 1054 * reset. 1055 * 1056 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 physical timer 1057 * and prevent timer interrupts. 1058 */ 1059 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & ~(CNTHP_CTL_ENABLE_BIT)); 1060 1061 manage_extensions_nonsecure_el2_unused(); 1062 #endif /* INIT_UNUSED_NS_EL2 */ 1063 } 1064 1065 /******************************************************************************* 1066 * Prepare the CPU system registers for first entry into realm, secure, or 1067 * normal world. 1068 * 1069 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 1070 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 1071 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 1072 * For all entries, the EL1 registers are initialized from the cpu_context 1073 ******************************************************************************/ 1074 void cm_prepare_el3_exit(uint32_t security_state) 1075 { 1076 u_register_t sctlr_el2, scr_el3; 1077 cpu_context_t *ctx = cm_get_context(security_state); 1078 1079 assert(ctx != NULL); 1080 1081 if (security_state == NON_SECURE) { 1082 uint64_t el2_implemented = el_implemented(2); 1083 1084 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 1085 CTX_SCR_EL3); 1086 1087 if (el2_implemented != EL_IMPL_NONE) { 1088 1089 /* 1090 * If context is not being used for EL2, initialize 1091 * HCRX_EL2 with its init value here. 1092 */ 1093 if (is_feat_hcx_supported()) { 1094 write_hcrx_el2(HCRX_EL2_INIT_VAL); 1095 } 1096 1097 /* 1098 * Initialize Fine-grained trap registers introduced 1099 * by FEAT_FGT so all traps are initially disabled when 1100 * switching to EL2 or a lower EL, preventing undesired 1101 * behavior. 1102 */ 1103 if (is_feat_fgt_supported()) { 1104 /* 1105 * Initialize HFG*_EL2 registers with a default 1106 * value so legacy systems unaware of FEAT_FGT 1107 * do not get trapped due to their lack of 1108 * initialization for this feature. 1109 */ 1110 write_hfgitr_el2(HFGITR_EL2_INIT_VAL); 1111 write_hfgrtr_el2(HFGRTR_EL2_INIT_VAL); 1112 write_hfgwtr_el2(HFGWTR_EL2_INIT_VAL); 1113 } 1114 1115 /* Condition to ensure EL2 is being used. */ 1116 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 1117 /* Initialize SCTLR_EL2 register with reset value. */ 1118 sctlr_el2 = SCTLR_EL2_RES1; 1119 1120 /* 1121 * If workaround of errata 764081 for Cortex-A75 1122 * is used then set SCTLR_EL2.IESB to enable 1123 * Implicit Error Synchronization Barrier. 1124 */ 1125 if (errata_a75_764081_applies()) { 1126 sctlr_el2 |= SCTLR_IESB_BIT; 1127 } 1128 1129 write_sctlr_el2(sctlr_el2); 1130 } else { 1131 /* 1132 * (scr_el3 & SCR_HCE_BIT==0) 1133 * EL2 implemented but unused. 1134 */ 1135 init_nonsecure_el2_unused(ctx); 1136 } 1137 } 1138 } 1139 #if (!CTX_INCLUDE_EL2_REGS) 1140 /* Restore EL1 system registers, only when CTX_INCLUDE_EL2_REGS=0 */ 1141 cm_el1_sysregs_context_restore(security_state); 1142 #endif 1143 cm_set_next_eret_context(security_state); 1144 } 1145 1146 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 1147 1148 static void el2_sysregs_context_save_fgt(el2_sysregs_t *ctx) 1149 { 1150 write_el2_ctx_fgt(ctx, hdfgrtr_el2, read_hdfgrtr_el2()); 1151 if (is_feat_amu_supported()) { 1152 write_el2_ctx_fgt(ctx, hafgrtr_el2, read_hafgrtr_el2()); 1153 } 1154 write_el2_ctx_fgt(ctx, hdfgwtr_el2, read_hdfgwtr_el2()); 1155 write_el2_ctx_fgt(ctx, hfgitr_el2, read_hfgitr_el2()); 1156 write_el2_ctx_fgt(ctx, hfgrtr_el2, read_hfgrtr_el2()); 1157 write_el2_ctx_fgt(ctx, hfgwtr_el2, read_hfgwtr_el2()); 1158 } 1159 1160 static void el2_sysregs_context_restore_fgt(el2_sysregs_t *ctx) 1161 { 1162 write_hdfgrtr_el2(read_el2_ctx_fgt(ctx, hdfgrtr_el2)); 1163 if (is_feat_amu_supported()) { 1164 write_hafgrtr_el2(read_el2_ctx_fgt(ctx, hafgrtr_el2)); 1165 } 1166 write_hdfgwtr_el2(read_el2_ctx_fgt(ctx, hdfgwtr_el2)); 1167 write_hfgitr_el2(read_el2_ctx_fgt(ctx, hfgitr_el2)); 1168 write_hfgrtr_el2(read_el2_ctx_fgt(ctx, hfgrtr_el2)); 1169 write_hfgwtr_el2(read_el2_ctx_fgt(ctx, hfgwtr_el2)); 1170 } 1171 1172 static void el2_sysregs_context_save_fgt2(el2_sysregs_t *ctx) 1173 { 1174 write_el2_ctx_fgt2(ctx, hdfgrtr2_el2, read_hdfgrtr2_el2()); 1175 write_el2_ctx_fgt2(ctx, hdfgwtr2_el2, read_hdfgwtr2_el2()); 1176 write_el2_ctx_fgt2(ctx, hfgitr2_el2, read_hfgitr2_el2()); 1177 write_el2_ctx_fgt2(ctx, hfgrtr2_el2, read_hfgrtr2_el2()); 1178 write_el2_ctx_fgt2(ctx, hfgwtr2_el2, read_hfgwtr2_el2()); 1179 } 1180 1181 static void el2_sysregs_context_restore_fgt2(el2_sysregs_t *ctx) 1182 { 1183 write_hdfgrtr2_el2(read_el2_ctx_fgt2(ctx, hdfgrtr2_el2)); 1184 write_hdfgwtr2_el2(read_el2_ctx_fgt2(ctx, hdfgwtr2_el2)); 1185 write_hfgitr2_el2(read_el2_ctx_fgt2(ctx, hfgitr2_el2)); 1186 write_hfgrtr2_el2(read_el2_ctx_fgt2(ctx, hfgrtr2_el2)); 1187 write_hfgwtr2_el2(read_el2_ctx_fgt2(ctx, hfgwtr2_el2)); 1188 } 1189 1190 static void el2_sysregs_context_save_mpam(el2_sysregs_t *ctx) 1191 { 1192 u_register_t mpam_idr = read_mpamidr_el1(); 1193 1194 write_el2_ctx_mpam(ctx, mpam2_el2, read_mpam2_el2()); 1195 1196 /* 1197 * The context registers that we intend to save would be part of the 1198 * PE's system register frame only if MPAMIDR_EL1.HAS_HCR == 1. 1199 */ 1200 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1201 return; 1202 } 1203 1204 /* 1205 * MPAMHCR_EL2, MPAMVPMV_EL2 and MPAMVPM0_EL2 are always present if 1206 * MPAMIDR_HAS_HCR_BIT == 1. 1207 */ 1208 write_el2_ctx_mpam(ctx, mpamhcr_el2, read_mpamhcr_el2()); 1209 write_el2_ctx_mpam(ctx, mpamvpm0_el2, read_mpamvpm0_el2()); 1210 write_el2_ctx_mpam(ctx, mpamvpmv_el2, read_mpamvpmv_el2()); 1211 1212 /* 1213 * The number of MPAMVPM registers is implementation defined, their 1214 * number is stored in the MPAMIDR_EL1 register. 1215 */ 1216 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1217 case 7: 1218 write_el2_ctx_mpam(ctx, mpamvpm7_el2, read_mpamvpm7_el2()); 1219 __fallthrough; 1220 case 6: 1221 write_el2_ctx_mpam(ctx, mpamvpm6_el2, read_mpamvpm6_el2()); 1222 __fallthrough; 1223 case 5: 1224 write_el2_ctx_mpam(ctx, mpamvpm5_el2, read_mpamvpm5_el2()); 1225 __fallthrough; 1226 case 4: 1227 write_el2_ctx_mpam(ctx, mpamvpm4_el2, read_mpamvpm4_el2()); 1228 __fallthrough; 1229 case 3: 1230 write_el2_ctx_mpam(ctx, mpamvpm3_el2, read_mpamvpm3_el2()); 1231 __fallthrough; 1232 case 2: 1233 write_el2_ctx_mpam(ctx, mpamvpm2_el2, read_mpamvpm2_el2()); 1234 __fallthrough; 1235 case 1: 1236 write_el2_ctx_mpam(ctx, mpamvpm1_el2, read_mpamvpm1_el2()); 1237 break; 1238 } 1239 } 1240 1241 static void el2_sysregs_context_restore_mpam(el2_sysregs_t *ctx) 1242 { 1243 u_register_t mpam_idr = read_mpamidr_el1(); 1244 1245 write_mpam2_el2(read_el2_ctx_mpam(ctx, mpam2_el2)); 1246 1247 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1248 return; 1249 } 1250 1251 write_mpamhcr_el2(read_el2_ctx_mpam(ctx, mpamhcr_el2)); 1252 write_mpamvpm0_el2(read_el2_ctx_mpam(ctx, mpamvpm0_el2)); 1253 write_mpamvpmv_el2(read_el2_ctx_mpam(ctx, mpamvpmv_el2)); 1254 1255 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1256 case 7: 1257 write_mpamvpm7_el2(read_el2_ctx_mpam(ctx, mpamvpm7_el2)); 1258 __fallthrough; 1259 case 6: 1260 write_mpamvpm6_el2(read_el2_ctx_mpam(ctx, mpamvpm6_el2)); 1261 __fallthrough; 1262 case 5: 1263 write_mpamvpm5_el2(read_el2_ctx_mpam(ctx, mpamvpm5_el2)); 1264 __fallthrough; 1265 case 4: 1266 write_mpamvpm4_el2(read_el2_ctx_mpam(ctx, mpamvpm4_el2)); 1267 __fallthrough; 1268 case 3: 1269 write_mpamvpm3_el2(read_el2_ctx_mpam(ctx, mpamvpm3_el2)); 1270 __fallthrough; 1271 case 2: 1272 write_mpamvpm2_el2(read_el2_ctx_mpam(ctx, mpamvpm2_el2)); 1273 __fallthrough; 1274 case 1: 1275 write_mpamvpm1_el2(read_el2_ctx_mpam(ctx, mpamvpm1_el2)); 1276 break; 1277 } 1278 } 1279 1280 /* --------------------------------------------------------------------------- 1281 * The following registers are not added: 1282 * ICH_AP0R<n>_EL2 1283 * ICH_AP1R<n>_EL2 1284 * ICH_LR<n>_EL2 1285 * 1286 * NOTE: For a system with S-EL2 present but not enabled, accessing 1287 * ICC_SRE_EL2 is undefined from EL3. To workaround this change the 1288 * SCR_EL3.NS = 1 before accessing this register. 1289 * --------------------------------------------------------------------------- 1290 */ 1291 static void el2_sysregs_context_save_gic(el2_sysregs_t *ctx, uint32_t security_state) 1292 { 1293 u_register_t scr_el3 = read_scr_el3(); 1294 1295 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1296 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1297 #else 1298 write_scr_el3(scr_el3 | SCR_NS_BIT); 1299 isb(); 1300 1301 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1302 1303 write_scr_el3(scr_el3); 1304 isb(); 1305 #endif 1306 write_el2_ctx_common(ctx, ich_hcr_el2, read_ich_hcr_el2()); 1307 1308 if (errata_ich_vmcr_el2_applies()) { 1309 if (security_state == SECURE) { 1310 write_scr_el3(scr_el3 & ~SCR_NS_BIT); 1311 } else { 1312 write_scr_el3(scr_el3 | SCR_NS_BIT); 1313 } 1314 isb(); 1315 } 1316 1317 write_el2_ctx_common(ctx, ich_vmcr_el2, read_ich_vmcr_el2()); 1318 1319 if (errata_ich_vmcr_el2_applies()) { 1320 write_scr_el3(scr_el3); 1321 isb(); 1322 } 1323 } 1324 1325 static void el2_sysregs_context_restore_gic(el2_sysregs_t *ctx, uint32_t security_state) 1326 { 1327 u_register_t scr_el3 = read_scr_el3(); 1328 1329 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1330 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1331 #else 1332 write_scr_el3(scr_el3 | SCR_NS_BIT); 1333 isb(); 1334 1335 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1336 1337 write_scr_el3(scr_el3); 1338 isb(); 1339 #endif 1340 write_ich_hcr_el2(read_el2_ctx_common(ctx, ich_hcr_el2)); 1341 1342 if (errata_ich_vmcr_el2_applies()) { 1343 if (security_state == SECURE) { 1344 write_scr_el3(scr_el3 & ~SCR_NS_BIT); 1345 } else { 1346 write_scr_el3(scr_el3 | SCR_NS_BIT); 1347 } 1348 isb(); 1349 } 1350 1351 write_ich_vmcr_el2(read_el2_ctx_common(ctx, ich_vmcr_el2)); 1352 1353 if (errata_ich_vmcr_el2_applies()) { 1354 write_scr_el3(scr_el3); 1355 isb(); 1356 } 1357 } 1358 1359 /* ----------------------------------------------------- 1360 * The following registers are not added: 1361 * AMEVCNTVOFF0<n>_EL2 1362 * AMEVCNTVOFF1<n>_EL2 1363 * ----------------------------------------------------- 1364 */ 1365 static void el2_sysregs_context_save_common(el2_sysregs_t *ctx) 1366 { 1367 write_el2_ctx_common(ctx, actlr_el2, read_actlr_el2()); 1368 write_el2_ctx_common(ctx, afsr0_el2, read_afsr0_el2()); 1369 write_el2_ctx_common(ctx, afsr1_el2, read_afsr1_el2()); 1370 write_el2_ctx_common(ctx, amair_el2, read_amair_el2()); 1371 write_el2_ctx_common(ctx, cnthctl_el2, read_cnthctl_el2()); 1372 write_el2_ctx_common(ctx, cntvoff_el2, read_cntvoff_el2()); 1373 write_el2_ctx_common(ctx, cptr_el2, read_cptr_el2()); 1374 if (CTX_INCLUDE_AARCH32_REGS) { 1375 write_el2_ctx_common(ctx, dbgvcr32_el2, read_dbgvcr32_el2()); 1376 } 1377 write_el2_ctx_common(ctx, elr_el2, read_elr_el2()); 1378 write_el2_ctx_common(ctx, esr_el2, read_esr_el2()); 1379 write_el2_ctx_common(ctx, far_el2, read_far_el2()); 1380 write_el2_ctx_common(ctx, hacr_el2, read_hacr_el2()); 1381 write_el2_ctx_common(ctx, hcr_el2, read_hcr_el2()); 1382 write_el2_ctx_common(ctx, hpfar_el2, read_hpfar_el2()); 1383 write_el2_ctx_common(ctx, hstr_el2, read_hstr_el2()); 1384 write_el2_ctx_common(ctx, mair_el2, read_mair_el2()); 1385 write_el2_ctx_common(ctx, mdcr_el2, read_mdcr_el2()); 1386 write_el2_ctx_common(ctx, sctlr_el2, read_sctlr_el2()); 1387 write_el2_ctx_common(ctx, spsr_el2, read_spsr_el2()); 1388 write_el2_ctx_common(ctx, sp_el2, read_sp_el2()); 1389 write_el2_ctx_common(ctx, tcr_el2, read_tcr_el2()); 1390 write_el2_ctx_common(ctx, tpidr_el2, read_tpidr_el2()); 1391 write_el2_ctx_common(ctx, vbar_el2, read_vbar_el2()); 1392 write_el2_ctx_common(ctx, vmpidr_el2, read_vmpidr_el2()); 1393 write_el2_ctx_common(ctx, vpidr_el2, read_vpidr_el2()); 1394 write_el2_ctx_common(ctx, vtcr_el2, read_vtcr_el2()); 1395 1396 write_el2_ctx_common_sysreg128(ctx, ttbr0_el2, read_ttbr0_el2()); 1397 write_el2_ctx_common_sysreg128(ctx, vttbr_el2, read_vttbr_el2()); 1398 } 1399 1400 static void el2_sysregs_context_restore_common(el2_sysregs_t *ctx) 1401 { 1402 write_actlr_el2(read_el2_ctx_common(ctx, actlr_el2)); 1403 write_afsr0_el2(read_el2_ctx_common(ctx, afsr0_el2)); 1404 write_afsr1_el2(read_el2_ctx_common(ctx, afsr1_el2)); 1405 write_amair_el2(read_el2_ctx_common(ctx, amair_el2)); 1406 write_cnthctl_el2(read_el2_ctx_common(ctx, cnthctl_el2)); 1407 write_cntvoff_el2(read_el2_ctx_common(ctx, cntvoff_el2)); 1408 write_cptr_el2(read_el2_ctx_common(ctx, cptr_el2)); 1409 if (CTX_INCLUDE_AARCH32_REGS) { 1410 write_dbgvcr32_el2(read_el2_ctx_common(ctx, dbgvcr32_el2)); 1411 } 1412 write_elr_el2(read_el2_ctx_common(ctx, elr_el2)); 1413 write_esr_el2(read_el2_ctx_common(ctx, esr_el2)); 1414 write_far_el2(read_el2_ctx_common(ctx, far_el2)); 1415 write_hacr_el2(read_el2_ctx_common(ctx, hacr_el2)); 1416 write_hcr_el2(read_el2_ctx_common(ctx, hcr_el2)); 1417 write_hpfar_el2(read_el2_ctx_common(ctx, hpfar_el2)); 1418 write_hstr_el2(read_el2_ctx_common(ctx, hstr_el2)); 1419 write_mair_el2(read_el2_ctx_common(ctx, mair_el2)); 1420 write_mdcr_el2(read_el2_ctx_common(ctx, mdcr_el2)); 1421 write_sctlr_el2(read_el2_ctx_common(ctx, sctlr_el2)); 1422 write_spsr_el2(read_el2_ctx_common(ctx, spsr_el2)); 1423 write_sp_el2(read_el2_ctx_common(ctx, sp_el2)); 1424 write_tcr_el2(read_el2_ctx_common(ctx, tcr_el2)); 1425 write_tpidr_el2(read_el2_ctx_common(ctx, tpidr_el2)); 1426 write_ttbr0_el2(read_el2_ctx_common(ctx, ttbr0_el2)); 1427 write_vbar_el2(read_el2_ctx_common(ctx, vbar_el2)); 1428 write_vmpidr_el2(read_el2_ctx_common(ctx, vmpidr_el2)); 1429 write_vpidr_el2(read_el2_ctx_common(ctx, vpidr_el2)); 1430 write_vtcr_el2(read_el2_ctx_common(ctx, vtcr_el2)); 1431 write_vttbr_el2(read_el2_ctx_common(ctx, vttbr_el2)); 1432 } 1433 1434 /******************************************************************************* 1435 * Save EL2 sysreg context 1436 ******************************************************************************/ 1437 void cm_el2_sysregs_context_save(uint32_t security_state) 1438 { 1439 cpu_context_t *ctx; 1440 el2_sysregs_t *el2_sysregs_ctx; 1441 1442 ctx = cm_get_context(security_state); 1443 assert(ctx != NULL); 1444 1445 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1446 1447 el2_sysregs_context_save_common(el2_sysregs_ctx); 1448 el2_sysregs_context_save_gic(el2_sysregs_ctx, security_state); 1449 1450 if (is_feat_mte2_supported()) { 1451 write_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2, read_tfsr_el2()); 1452 } 1453 1454 if (is_feat_mpam_supported()) { 1455 el2_sysregs_context_save_mpam(el2_sysregs_ctx); 1456 } 1457 1458 if (is_feat_fgt_supported()) { 1459 el2_sysregs_context_save_fgt(el2_sysregs_ctx); 1460 } 1461 1462 if (is_feat_fgt2_supported()) { 1463 el2_sysregs_context_save_fgt2(el2_sysregs_ctx); 1464 } 1465 1466 if (is_feat_ecv_v2_supported()) { 1467 write_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2, read_cntpoff_el2()); 1468 } 1469 1470 if (is_feat_vhe_supported()) { 1471 write_el2_ctx_vhe(el2_sysregs_ctx, contextidr_el2, 1472 read_contextidr_el2()); 1473 write_el2_ctx_vhe_sysreg128(el2_sysregs_ctx, ttbr1_el2, read_ttbr1_el2()); 1474 } 1475 1476 if (is_feat_ras_supported()) { 1477 write_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2, read_vdisr_el2()); 1478 write_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2, read_vsesr_el2()); 1479 } 1480 1481 if (is_feat_nv2_supported()) { 1482 write_el2_ctx_neve(el2_sysregs_ctx, vncr_el2, read_vncr_el2()); 1483 } 1484 1485 if (is_feat_trf_supported()) { 1486 write_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2, read_trfcr_el2()); 1487 } 1488 1489 if (is_feat_csv2_2_supported()) { 1490 write_el2_ctx_csv2_2(el2_sysregs_ctx, scxtnum_el2, 1491 read_scxtnum_el2()); 1492 } 1493 1494 if (is_feat_hcx_supported()) { 1495 write_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2, read_hcrx_el2()); 1496 } 1497 1498 if (is_feat_tcr2_supported()) { 1499 write_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2, read_tcr2_el2()); 1500 } 1501 1502 if (is_feat_sxpie_supported()) { 1503 write_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2, read_pire0_el2()); 1504 write_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2, read_pir_el2()); 1505 } 1506 1507 if (is_feat_sxpoe_supported()) { 1508 write_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2, read_por_el2()); 1509 } 1510 1511 if (is_feat_brbe_supported()) { 1512 write_el2_ctx_brbe(el2_sysregs_ctx, brbcr_el2, read_brbcr_el2()); 1513 } 1514 1515 if (is_feat_s2pie_supported()) { 1516 write_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2, read_s2pir_el2()); 1517 } 1518 1519 if (is_feat_gcs_supported()) { 1520 write_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2, read_gcscr_el2()); 1521 write_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2, read_gcspr_el2()); 1522 } 1523 1524 if (is_feat_sctlr2_supported()) { 1525 write_el2_ctx_sctlr2(el2_sysregs_ctx, sctlr2_el2, read_sctlr2_el2()); 1526 } 1527 } 1528 1529 /******************************************************************************* 1530 * Restore EL2 sysreg context 1531 ******************************************************************************/ 1532 void cm_el2_sysregs_context_restore(uint32_t security_state) 1533 { 1534 cpu_context_t *ctx; 1535 el2_sysregs_t *el2_sysregs_ctx; 1536 1537 ctx = cm_get_context(security_state); 1538 assert(ctx != NULL); 1539 1540 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1541 1542 el2_sysregs_context_restore_common(el2_sysregs_ctx); 1543 el2_sysregs_context_restore_gic(el2_sysregs_ctx, security_state); 1544 1545 if (is_feat_mte2_supported()) { 1546 write_tfsr_el2(read_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2)); 1547 } 1548 1549 if (is_feat_mpam_supported()) { 1550 el2_sysregs_context_restore_mpam(el2_sysregs_ctx); 1551 } 1552 1553 if (is_feat_fgt_supported()) { 1554 el2_sysregs_context_restore_fgt(el2_sysregs_ctx); 1555 } 1556 1557 if (is_feat_fgt2_supported()) { 1558 el2_sysregs_context_restore_fgt2(el2_sysregs_ctx); 1559 } 1560 1561 if (is_feat_ecv_v2_supported()) { 1562 write_cntpoff_el2(read_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2)); 1563 } 1564 1565 if (is_feat_vhe_supported()) { 1566 write_contextidr_el2(read_el2_ctx_vhe(el2_sysregs_ctx, 1567 contextidr_el2)); 1568 write_ttbr1_el2(read_el2_ctx_vhe(el2_sysregs_ctx, ttbr1_el2)); 1569 } 1570 1571 if (is_feat_ras_supported()) { 1572 write_vdisr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2)); 1573 write_vsesr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2)); 1574 } 1575 1576 if (is_feat_nv2_supported()) { 1577 write_vncr_el2(read_el2_ctx_neve(el2_sysregs_ctx, vncr_el2)); 1578 } 1579 1580 if (is_feat_trf_supported()) { 1581 write_trfcr_el2(read_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2)); 1582 } 1583 1584 if (is_feat_csv2_2_supported()) { 1585 write_scxtnum_el2(read_el2_ctx_csv2_2(el2_sysregs_ctx, 1586 scxtnum_el2)); 1587 } 1588 1589 if (is_feat_hcx_supported()) { 1590 write_hcrx_el2(read_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2)); 1591 } 1592 1593 if (is_feat_tcr2_supported()) { 1594 write_tcr2_el2(read_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2)); 1595 } 1596 1597 if (is_feat_sxpie_supported()) { 1598 write_pire0_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2)); 1599 write_pir_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2)); 1600 } 1601 1602 if (is_feat_sxpoe_supported()) { 1603 write_por_el2(read_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2)); 1604 } 1605 1606 if (is_feat_s2pie_supported()) { 1607 write_s2pir_el2(read_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2)); 1608 } 1609 1610 if (is_feat_gcs_supported()) { 1611 write_gcscr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2)); 1612 write_gcspr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2)); 1613 } 1614 1615 if (is_feat_sctlr2_supported()) { 1616 write_sctlr2_el2(read_el2_ctx_sctlr2(el2_sysregs_ctx, sctlr2_el2)); 1617 } 1618 1619 if (is_feat_brbe_supported()) { 1620 write_brbcr_el2(read_el2_ctx_brbe(el2_sysregs_ctx, brbcr_el2)); 1621 } 1622 } 1623 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 1624 1625 /******************************************************************************* 1626 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS 1627 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly 1628 * updating EL1 and EL2 registers. Otherwise, it calls the generic 1629 * cm_prepare_el3_exit function. 1630 ******************************************************************************/ 1631 void cm_prepare_el3_exit_ns(void) 1632 { 1633 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 1634 #if ENABLE_ASSERTIONS 1635 cpu_context_t *ctx = cm_get_context(NON_SECURE); 1636 assert(ctx != NULL); 1637 1638 /* Assert that EL2 is used. */ 1639 u_register_t scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 1640 assert(((scr_el3 & SCR_HCE_BIT) != 0UL) && 1641 (el_implemented(2U) != EL_IMPL_NONE)); 1642 #endif /* ENABLE_ASSERTIONS */ 1643 1644 /* Restore EL2 sysreg contexts */ 1645 cm_el2_sysregs_context_restore(NON_SECURE); 1646 cm_set_next_eret_context(NON_SECURE); 1647 #else 1648 cm_prepare_el3_exit(NON_SECURE); 1649 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 1650 } 1651 1652 #if ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) 1653 /******************************************************************************* 1654 * The next set of six functions are used by runtime services to save and restore 1655 * EL1 context on the 'cpu_context' structure for the specified security state. 1656 ******************************************************************************/ 1657 static void el1_sysregs_context_save(el1_sysregs_t *ctx) 1658 { 1659 write_el1_ctx_common(ctx, spsr_el1, read_spsr_el1()); 1660 write_el1_ctx_common(ctx, elr_el1, read_elr_el1()); 1661 1662 #if (!ERRATA_SPECULATIVE_AT) 1663 write_el1_ctx_common(ctx, sctlr_el1, read_sctlr_el1()); 1664 write_el1_ctx_common(ctx, tcr_el1, read_tcr_el1()); 1665 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1666 1667 write_el1_ctx_common(ctx, cpacr_el1, read_cpacr_el1()); 1668 write_el1_ctx_common(ctx, csselr_el1, read_csselr_el1()); 1669 write_el1_ctx_common(ctx, sp_el1, read_sp_el1()); 1670 write_el1_ctx_common(ctx, esr_el1, read_esr_el1()); 1671 write_el1_ctx_common(ctx, mair_el1, read_mair_el1()); 1672 write_el1_ctx_common(ctx, amair_el1, read_amair_el1()); 1673 write_el1_ctx_common(ctx, actlr_el1, read_actlr_el1()); 1674 write_el1_ctx_common(ctx, tpidr_el1, read_tpidr_el1()); 1675 write_el1_ctx_common(ctx, tpidr_el0, read_tpidr_el0()); 1676 write_el1_ctx_common(ctx, tpidrro_el0, read_tpidrro_el0()); 1677 write_el1_ctx_common(ctx, far_el1, read_far_el1()); 1678 write_el1_ctx_common(ctx, afsr0_el1, read_afsr0_el1()); 1679 write_el1_ctx_common(ctx, afsr1_el1, read_afsr1_el1()); 1680 write_el1_ctx_common(ctx, contextidr_el1, read_contextidr_el1()); 1681 write_el1_ctx_common(ctx, vbar_el1, read_vbar_el1()); 1682 write_el1_ctx_common(ctx, mdccint_el1, read_mdccint_el1()); 1683 write_el1_ctx_common(ctx, mdscr_el1, read_mdscr_el1()); 1684 1685 write_el1_ctx_common_sysreg128(ctx, par_el1, read_par_el1()); 1686 write_el1_ctx_common_sysreg128(ctx, ttbr0_el1, read_ttbr0_el1()); 1687 write_el1_ctx_common_sysreg128(ctx, ttbr1_el1, read_ttbr1_el1()); 1688 1689 if (CTX_INCLUDE_AARCH32_REGS) { 1690 /* Save Aarch32 registers */ 1691 write_el1_ctx_aarch32(ctx, spsr_abt, read_spsr_abt()); 1692 write_el1_ctx_aarch32(ctx, spsr_und, read_spsr_und()); 1693 write_el1_ctx_aarch32(ctx, spsr_irq, read_spsr_irq()); 1694 write_el1_ctx_aarch32(ctx, spsr_fiq, read_spsr_fiq()); 1695 write_el1_ctx_aarch32(ctx, dacr32_el2, read_dacr32_el2()); 1696 write_el1_ctx_aarch32(ctx, ifsr32_el2, read_ifsr32_el2()); 1697 } 1698 1699 if (NS_TIMER_SWITCH) { 1700 /* Save NS Timer registers */ 1701 write_el1_ctx_arch_timer(ctx, cntp_ctl_el0, read_cntp_ctl_el0()); 1702 write_el1_ctx_arch_timer(ctx, cntp_cval_el0, read_cntp_cval_el0()); 1703 write_el1_ctx_arch_timer(ctx, cntv_ctl_el0, read_cntv_ctl_el0()); 1704 write_el1_ctx_arch_timer(ctx, cntv_cval_el0, read_cntv_cval_el0()); 1705 write_el1_ctx_arch_timer(ctx, cntkctl_el1, read_cntkctl_el1()); 1706 } 1707 1708 if (is_feat_mte2_supported()) { 1709 write_el1_ctx_mte2(ctx, tfsre0_el1, read_tfsre0_el1()); 1710 write_el1_ctx_mte2(ctx, tfsr_el1, read_tfsr_el1()); 1711 write_el1_ctx_mte2(ctx, rgsr_el1, read_rgsr_el1()); 1712 write_el1_ctx_mte2(ctx, gcr_el1, read_gcr_el1()); 1713 } 1714 1715 if (is_feat_ras_supported()) { 1716 write_el1_ctx_ras(ctx, disr_el1, read_disr_el1()); 1717 } 1718 1719 if (is_feat_s1pie_supported()) { 1720 write_el1_ctx_s1pie(ctx, pire0_el1, read_pire0_el1()); 1721 write_el1_ctx_s1pie(ctx, pir_el1, read_pir_el1()); 1722 } 1723 1724 if (is_feat_s1poe_supported()) { 1725 write_el1_ctx_s1poe(ctx, por_el1, read_por_el1()); 1726 } 1727 1728 if (is_feat_s2poe_supported()) { 1729 write_el1_ctx_s2poe(ctx, s2por_el1, read_s2por_el1()); 1730 } 1731 1732 if (is_feat_tcr2_supported()) { 1733 write_el1_ctx_tcr2(ctx, tcr2_el1, read_tcr2_el1()); 1734 } 1735 1736 if (is_feat_trf_supported()) { 1737 write_el1_ctx_trf(ctx, trfcr_el1, read_trfcr_el1()); 1738 } 1739 1740 if (is_feat_csv2_2_supported()) { 1741 write_el1_ctx_csv2_2(ctx, scxtnum_el0, read_scxtnum_el0()); 1742 write_el1_ctx_csv2_2(ctx, scxtnum_el1, read_scxtnum_el1()); 1743 } 1744 1745 if (is_feat_gcs_supported()) { 1746 write_el1_ctx_gcs(ctx, gcscr_el1, read_gcscr_el1()); 1747 write_el1_ctx_gcs(ctx, gcscre0_el1, read_gcscre0_el1()); 1748 write_el1_ctx_gcs(ctx, gcspr_el1, read_gcspr_el1()); 1749 write_el1_ctx_gcs(ctx, gcspr_el0, read_gcspr_el0()); 1750 } 1751 1752 if (is_feat_the_supported()) { 1753 write_el1_ctx_the_sysreg128(ctx, rcwmask_el1, read_rcwmask_el1()); 1754 write_el1_ctx_the_sysreg128(ctx, rcwsmask_el1, read_rcwsmask_el1()); 1755 } 1756 1757 if (is_feat_sctlr2_supported()) { 1758 write_el1_ctx_sctlr2(ctx, sctlr2_el1, read_sctlr2_el1()); 1759 } 1760 1761 if (is_feat_ls64_accdata_supported()) { 1762 write_el1_ctx_ls64(ctx, accdata_el1, read_accdata_el1()); 1763 } 1764 } 1765 1766 static void el1_sysregs_context_restore(el1_sysregs_t *ctx) 1767 { 1768 write_spsr_el1(read_el1_ctx_common(ctx, spsr_el1)); 1769 write_elr_el1(read_el1_ctx_common(ctx, elr_el1)); 1770 1771 #if (!ERRATA_SPECULATIVE_AT) 1772 write_sctlr_el1(read_el1_ctx_common(ctx, sctlr_el1)); 1773 write_tcr_el1(read_el1_ctx_common(ctx, tcr_el1)); 1774 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1775 1776 write_cpacr_el1(read_el1_ctx_common(ctx, cpacr_el1)); 1777 write_csselr_el1(read_el1_ctx_common(ctx, csselr_el1)); 1778 write_sp_el1(read_el1_ctx_common(ctx, sp_el1)); 1779 write_esr_el1(read_el1_ctx_common(ctx, esr_el1)); 1780 write_ttbr0_el1(read_el1_ctx_common(ctx, ttbr0_el1)); 1781 write_ttbr1_el1(read_el1_ctx_common(ctx, ttbr1_el1)); 1782 write_mair_el1(read_el1_ctx_common(ctx, mair_el1)); 1783 write_amair_el1(read_el1_ctx_common(ctx, amair_el1)); 1784 write_actlr_el1(read_el1_ctx_common(ctx, actlr_el1)); 1785 write_tpidr_el1(read_el1_ctx_common(ctx, tpidr_el1)); 1786 write_tpidr_el0(read_el1_ctx_common(ctx, tpidr_el0)); 1787 write_tpidrro_el0(read_el1_ctx_common(ctx, tpidrro_el0)); 1788 write_par_el1(read_el1_ctx_common(ctx, par_el1)); 1789 write_far_el1(read_el1_ctx_common(ctx, far_el1)); 1790 write_afsr0_el1(read_el1_ctx_common(ctx, afsr0_el1)); 1791 write_afsr1_el1(read_el1_ctx_common(ctx, afsr1_el1)); 1792 write_contextidr_el1(read_el1_ctx_common(ctx, contextidr_el1)); 1793 write_vbar_el1(read_el1_ctx_common(ctx, vbar_el1)); 1794 write_mdccint_el1(read_el1_ctx_common(ctx, mdccint_el1)); 1795 write_mdscr_el1(read_el1_ctx_common(ctx, mdscr_el1)); 1796 1797 if (CTX_INCLUDE_AARCH32_REGS) { 1798 /* Restore Aarch32 registers */ 1799 write_spsr_abt(read_el1_ctx_aarch32(ctx, spsr_abt)); 1800 write_spsr_und(read_el1_ctx_aarch32(ctx, spsr_und)); 1801 write_spsr_irq(read_el1_ctx_aarch32(ctx, spsr_irq)); 1802 write_spsr_fiq(read_el1_ctx_aarch32(ctx, spsr_fiq)); 1803 write_dacr32_el2(read_el1_ctx_aarch32(ctx, dacr32_el2)); 1804 write_ifsr32_el2(read_el1_ctx_aarch32(ctx, ifsr32_el2)); 1805 } 1806 1807 if (NS_TIMER_SWITCH) { 1808 /* Restore NS Timer registers */ 1809 write_cntp_ctl_el0(read_el1_ctx_arch_timer(ctx, cntp_ctl_el0)); 1810 write_cntp_cval_el0(read_el1_ctx_arch_timer(ctx, cntp_cval_el0)); 1811 write_cntv_ctl_el0(read_el1_ctx_arch_timer(ctx, cntv_ctl_el0)); 1812 write_cntv_cval_el0(read_el1_ctx_arch_timer(ctx, cntv_cval_el0)); 1813 write_cntkctl_el1(read_el1_ctx_arch_timer(ctx, cntkctl_el1)); 1814 } 1815 1816 if (is_feat_mte2_supported()) { 1817 write_tfsre0_el1(read_el1_ctx_mte2(ctx, tfsre0_el1)); 1818 write_tfsr_el1(read_el1_ctx_mte2(ctx, tfsr_el1)); 1819 write_rgsr_el1(read_el1_ctx_mte2(ctx, rgsr_el1)); 1820 write_gcr_el1(read_el1_ctx_mte2(ctx, gcr_el1)); 1821 } 1822 1823 if (is_feat_ras_supported()) { 1824 write_disr_el1(read_el1_ctx_ras(ctx, disr_el1)); 1825 } 1826 1827 if (is_feat_s1pie_supported()) { 1828 write_pire0_el1(read_el1_ctx_s1pie(ctx, pire0_el1)); 1829 write_pir_el1(read_el1_ctx_s1pie(ctx, pir_el1)); 1830 } 1831 1832 if (is_feat_s1poe_supported()) { 1833 write_por_el1(read_el1_ctx_s1poe(ctx, por_el1)); 1834 } 1835 1836 if (is_feat_s2poe_supported()) { 1837 write_s2por_el1(read_el1_ctx_s2poe(ctx, s2por_el1)); 1838 } 1839 1840 if (is_feat_tcr2_supported()) { 1841 write_tcr2_el1(read_el1_ctx_tcr2(ctx, tcr2_el1)); 1842 } 1843 1844 if (is_feat_trf_supported()) { 1845 write_trfcr_el1(read_el1_ctx_trf(ctx, trfcr_el1)); 1846 } 1847 1848 if (is_feat_csv2_2_supported()) { 1849 write_scxtnum_el0(read_el1_ctx_csv2_2(ctx, scxtnum_el0)); 1850 write_scxtnum_el1(read_el1_ctx_csv2_2(ctx, scxtnum_el1)); 1851 } 1852 1853 if (is_feat_gcs_supported()) { 1854 write_gcscr_el1(read_el1_ctx_gcs(ctx, gcscr_el1)); 1855 write_gcscre0_el1(read_el1_ctx_gcs(ctx, gcscre0_el1)); 1856 write_gcspr_el1(read_el1_ctx_gcs(ctx, gcspr_el1)); 1857 write_gcspr_el0(read_el1_ctx_gcs(ctx, gcspr_el0)); 1858 } 1859 1860 if (is_feat_the_supported()) { 1861 write_rcwmask_el1(read_el1_ctx_the(ctx, rcwmask_el1)); 1862 write_rcwsmask_el1(read_el1_ctx_the(ctx, rcwsmask_el1)); 1863 } 1864 1865 if (is_feat_sctlr2_supported()) { 1866 write_sctlr2_el1(read_el1_ctx_sctlr2(ctx, sctlr2_el1)); 1867 } 1868 1869 if (is_feat_ls64_accdata_supported()) { 1870 write_accdata_el1(read_el1_ctx_ls64(ctx, accdata_el1)); 1871 } 1872 } 1873 1874 /******************************************************************************* 1875 * The next couple of functions are used by runtime services to save and restore 1876 * EL1 context on the 'cpu_context' structure for the specified security state. 1877 ******************************************************************************/ 1878 void cm_el1_sysregs_context_save(uint32_t security_state) 1879 { 1880 cpu_context_t *ctx; 1881 1882 ctx = cm_get_context(security_state); 1883 assert(ctx != NULL); 1884 1885 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 1886 1887 #if IMAGE_BL31 1888 if (security_state == SECURE) { 1889 PUBLISH_EVENT(cm_exited_secure_world); 1890 } else { 1891 PUBLISH_EVENT(cm_exited_normal_world); 1892 } 1893 #endif 1894 } 1895 1896 void cm_el1_sysregs_context_restore(uint32_t security_state) 1897 { 1898 cpu_context_t *ctx; 1899 1900 ctx = cm_get_context(security_state); 1901 assert(ctx != NULL); 1902 1903 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 1904 1905 #if IMAGE_BL31 1906 if (security_state == SECURE) { 1907 PUBLISH_EVENT(cm_entering_secure_world); 1908 } else { 1909 PUBLISH_EVENT(cm_entering_normal_world); 1910 } 1911 #endif 1912 } 1913 1914 #endif /* ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) */ 1915 1916 /******************************************************************************* 1917 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 1918 * given security state with the given entrypoint 1919 ******************************************************************************/ 1920 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 1921 { 1922 cpu_context_t *ctx; 1923 el3_state_t *state; 1924 1925 ctx = cm_get_context(security_state); 1926 assert(ctx != NULL); 1927 1928 /* Populate EL3 state so that ERET jumps to the correct entry */ 1929 state = get_el3state_ctx(ctx); 1930 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1931 } 1932 1933 /******************************************************************************* 1934 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 1935 * pertaining to the given security state 1936 ******************************************************************************/ 1937 void cm_set_elr_spsr_el3(uint32_t security_state, 1938 uintptr_t entrypoint, uint32_t spsr) 1939 { 1940 cpu_context_t *ctx; 1941 el3_state_t *state; 1942 1943 ctx = cm_get_context(security_state); 1944 assert(ctx != NULL); 1945 1946 /* Populate EL3 state so that ERET jumps to the correct entry */ 1947 state = get_el3state_ctx(ctx); 1948 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1949 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 1950 } 1951 1952 /******************************************************************************* 1953 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 1954 * pertaining to the given security state using the value and bit position 1955 * specified in the parameters. It preserves all other bits. 1956 ******************************************************************************/ 1957 void cm_write_scr_el3_bit(uint32_t security_state, 1958 uint32_t bit_pos, 1959 uint32_t value) 1960 { 1961 cpu_context_t *ctx; 1962 el3_state_t *state; 1963 u_register_t scr_el3; 1964 1965 ctx = cm_get_context(security_state); 1966 assert(ctx != NULL); 1967 1968 /* Ensure that the bit position is a valid one */ 1969 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 1970 1971 /* Ensure that the 'value' is only a bit wide */ 1972 assert(value <= 1U); 1973 1974 /* 1975 * Get the SCR_EL3 value from the cpu context, clear the desired bit 1976 * and set it to its new value. 1977 */ 1978 state = get_el3state_ctx(ctx); 1979 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 1980 scr_el3 &= ~(1UL << bit_pos); 1981 scr_el3 |= (u_register_t)value << bit_pos; 1982 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 1983 } 1984 1985 /******************************************************************************* 1986 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 1987 * given security state. 1988 ******************************************************************************/ 1989 u_register_t cm_get_scr_el3(uint32_t security_state) 1990 { 1991 const cpu_context_t *ctx; 1992 const el3_state_t *state; 1993 1994 ctx = cm_get_context(security_state); 1995 assert(ctx != NULL); 1996 1997 /* Populate EL3 state so that ERET jumps to the correct entry */ 1998 state = get_el3state_ctx(ctx); 1999 return read_ctx_reg(state, CTX_SCR_EL3); 2000 } 2001 2002 /******************************************************************************* 2003 * This function is used to program the context that's used for exception 2004 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 2005 * the required security state 2006 ******************************************************************************/ 2007 void cm_set_next_eret_context(uint32_t security_state) 2008 { 2009 cpu_context_t *ctx; 2010 2011 ctx = cm_get_context(security_state); 2012 assert(ctx != NULL); 2013 2014 cm_set_next_context(ctx); 2015 } 2016