1 /* 2 * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <stdbool.h> 10 #include <string.h> 11 12 #include <platform_def.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <arch_features.h> 17 #include <bl31/interrupt_mgmt.h> 18 #include <common/bl_common.h> 19 #include <common/debug.h> 20 #include <context.h> 21 #include <drivers/arm/gicv3.h> 22 #include <lib/el3_runtime/context_mgmt.h> 23 #include <lib/el3_runtime/pubsub_events.h> 24 #include <lib/extensions/amu.h> 25 #include <lib/extensions/brbe.h> 26 #include <lib/extensions/mpam.h> 27 #include <lib/extensions/pmuv3.h> 28 #include <lib/extensions/sme.h> 29 #include <lib/extensions/spe.h> 30 #include <lib/extensions/sve.h> 31 #include <lib/extensions/sys_reg_trace.h> 32 #include <lib/extensions/trbe.h> 33 #include <lib/extensions/trf.h> 34 #include <lib/utils.h> 35 36 #if ENABLE_FEAT_TWED 37 /* Make sure delay value fits within the range(0-15) */ 38 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check); 39 #endif /* ENABLE_FEAT_TWED */ 40 41 static void manage_extensions_nonsecure(cpu_context_t *ctx); 42 static void manage_extensions_secure(cpu_context_t *ctx); 43 44 static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep) 45 { 46 u_register_t sctlr_elx, actlr_elx; 47 48 /* 49 * Initialise SCTLR_EL1 to the reset value corresponding to the target 50 * execution state setting all fields rather than relying on the hw. 51 * Some fields have architecturally UNKNOWN reset values and these are 52 * set to zero. 53 * 54 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 55 * 56 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 57 * required by PSCI specification) 58 */ 59 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 60 if (GET_RW(ep->spsr) == MODE_RW_64) { 61 sctlr_elx |= SCTLR_EL1_RES1; 62 } else { 63 /* 64 * If the target execution state is AArch32 then the following 65 * fields need to be set. 66 * 67 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 68 * instructions are not trapped to EL1. 69 * 70 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 71 * instructions are not trapped to EL1. 72 * 73 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 74 * CP15DMB, CP15DSB, and CP15ISB instructions. 75 */ 76 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 77 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 78 } 79 80 #if ERRATA_A75_764081 81 /* 82 * If workaround of errata 764081 for Cortex-A75 is used then set 83 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 84 */ 85 sctlr_elx |= SCTLR_IESB_BIT; 86 #endif 87 /* Store the initialised SCTLR_EL1 value in the cpu_context */ 88 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); 89 90 /* 91 * Base the context ACTLR_EL1 on the current value, as it is 92 * implementation defined. The context restore process will write 93 * the value from the context to the actual register and can cause 94 * problems for processor cores that don't expect certain bits to 95 * be zero. 96 */ 97 actlr_elx = read_actlr_el1(); 98 write_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx)); 99 } 100 101 /****************************************************************************** 102 * This function performs initializations that are specific to SECURE state 103 * and updates the cpu context specified by 'ctx'. 104 *****************************************************************************/ 105 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep) 106 { 107 u_register_t scr_el3; 108 el3_state_t *state; 109 110 state = get_el3state_ctx(ctx); 111 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 112 113 #if defined(IMAGE_BL31) && !defined(SPD_spmd) 114 /* 115 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 116 * indicated by the interrupt routing model for BL31. 117 */ 118 scr_el3 |= get_scr_el3_from_routing_model(SECURE); 119 #endif 120 121 #if !CTX_INCLUDE_MTE_REGS || ENABLE_ASSERTIONS 122 /* Get Memory Tagging Extension support level */ 123 unsigned int mte = get_armv8_5_mte_support(); 124 #endif 125 /* 126 * Allow access to Allocation Tags when CTX_INCLUDE_MTE_REGS 127 * is set, or when MTE is only implemented at EL0. 128 */ 129 #if CTX_INCLUDE_MTE_REGS 130 assert((mte == MTE_IMPLEMENTED_ELX) || (mte == MTE_IMPLEMENTED_ASY)); 131 scr_el3 |= SCR_ATA_BIT; 132 #else 133 if (mte == MTE_IMPLEMENTED_EL0) { 134 scr_el3 |= SCR_ATA_BIT; 135 } 136 #endif /* CTX_INCLUDE_MTE_REGS */ 137 138 /* Enable S-EL2 if the next EL is EL2 and S-EL2 is present */ 139 if ((GET_EL(ep->spsr) == MODE_EL2) && is_feat_sel2_supported()) { 140 if (GET_RW(ep->spsr) != MODE_RW_64) { 141 ERROR("S-EL2 can not be used in AArch32\n."); 142 panic(); 143 } 144 145 scr_el3 |= SCR_EEL2_BIT; 146 } 147 148 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 149 150 /* 151 * Initialize EL1 context registers unless SPMC is running 152 * at S-EL2. 153 */ 154 #if !SPMD_SPM_AT_SEL2 155 setup_el1_context(ctx, ep); 156 #endif 157 158 manage_extensions_secure(ctx); 159 } 160 161 #if ENABLE_RME 162 /****************************************************************************** 163 * This function performs initializations that are specific to REALM state 164 * and updates the cpu context specified by 'ctx'. 165 *****************************************************************************/ 166 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep) 167 { 168 u_register_t scr_el3; 169 el3_state_t *state; 170 171 state = get_el3state_ctx(ctx); 172 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 173 174 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT; 175 176 if (is_feat_csv2_2_supported()) { 177 /* Enable access to the SCXTNUM_ELx registers. */ 178 scr_el3 |= SCR_EnSCXT_BIT; 179 } 180 181 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 182 } 183 #endif /* ENABLE_RME */ 184 185 /****************************************************************************** 186 * This function performs initializations that are specific to NON-SECURE state 187 * and updates the cpu context specified by 'ctx'. 188 *****************************************************************************/ 189 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep) 190 { 191 u_register_t scr_el3; 192 el3_state_t *state; 193 194 state = get_el3state_ctx(ctx); 195 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 196 197 /* SCR_NS: Set the NS bit */ 198 scr_el3 |= SCR_NS_BIT; 199 200 #if !CTX_INCLUDE_PAUTH_REGS 201 /* 202 * If the pointer authentication registers aren't saved during world 203 * switches the value of the registers can be leaked from the Secure to 204 * the Non-secure world. To prevent this, rather than enabling pointer 205 * authentication everywhere, we only enable it in the Non-secure world. 206 * 207 * If the Secure world wants to use pointer authentication, 208 * CTX_INCLUDE_PAUTH_REGS must be set to 1. 209 */ 210 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 211 #endif /* !CTX_INCLUDE_PAUTH_REGS */ 212 213 /* Allow access to Allocation Tags when MTE is implemented. */ 214 scr_el3 |= SCR_ATA_BIT; 215 216 #if HANDLE_EA_EL3_FIRST_NS 217 /* SCR_EL3.EA: Route External Abort and SError Interrupt to EL3. */ 218 scr_el3 |= SCR_EA_BIT; 219 #endif 220 221 #if RAS_TRAP_NS_ERR_REC_ACCESS 222 /* 223 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 224 * and RAS ERX registers from EL1 and EL2(from any security state) 225 * are trapped to EL3. 226 * Set here to trap only for NS EL1/EL2 227 * 228 */ 229 scr_el3 |= SCR_TERR_BIT; 230 #endif 231 232 if (is_feat_csv2_2_supported()) { 233 /* Enable access to the SCXTNUM_ELx registers. */ 234 scr_el3 |= SCR_EnSCXT_BIT; 235 } 236 237 #ifdef IMAGE_BL31 238 /* 239 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 240 * indicated by the interrupt routing model for BL31. 241 */ 242 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE); 243 #endif 244 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 245 246 /* Initialize EL1 context registers */ 247 setup_el1_context(ctx, ep); 248 249 /* Initialize EL2 context registers */ 250 #if CTX_INCLUDE_EL2_REGS 251 252 /* 253 * Initialize SCTLR_EL2 context register using Endianness value 254 * taken from the entrypoint attribute. 255 */ 256 u_register_t sctlr_el2 = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 257 sctlr_el2 |= SCTLR_EL2_RES1; 258 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_SCTLR_EL2, 259 sctlr_el2); 260 261 /* 262 * Program the ICC_SRE_EL2 to make sure the correct bits are set 263 * when restoring NS context. 264 */ 265 u_register_t icc_sre_el2 = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | 266 ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT; 267 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_ICC_SRE_EL2, 268 icc_sre_el2); 269 270 if (is_feat_hcx_supported()) { 271 /* 272 * Initialize register HCRX_EL2 with its init value. 273 * As the value of HCRX_EL2 is UNKNOWN on reset, there is a 274 * chance that this can lead to unexpected behavior in lower 275 * ELs that have not been updated since the introduction of 276 * this feature if not properly initialized, especially when 277 * it comes to those bits that enable/disable traps. 278 */ 279 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_HCRX_EL2, 280 HCRX_EL2_INIT_VAL); 281 } 282 283 if (is_feat_fgt_supported()) { 284 /* 285 * Initialize HFG*_EL2 registers with a default value so legacy 286 * systems unaware of FEAT_FGT do not get trapped due to their lack 287 * of initialization for this feature. 288 */ 289 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_HFGITR_EL2, 290 HFGITR_EL2_INIT_VAL); 291 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_HFGRTR_EL2, 292 HFGRTR_EL2_INIT_VAL); 293 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_HFGWTR_EL2, 294 HFGWTR_EL2_INIT_VAL); 295 } 296 #endif /* CTX_INCLUDE_EL2_REGS */ 297 298 manage_extensions_nonsecure(ctx); 299 } 300 301 /******************************************************************************* 302 * The following function performs initialization of the cpu_context 'ctx' 303 * for first use that is common to all security states, and sets the 304 * initial entrypoint state as specified by the entry_point_info structure. 305 * 306 * The EE and ST attributes are used to configure the endianness and secure 307 * timer availability for the new execution context. 308 ******************************************************************************/ 309 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 310 { 311 u_register_t scr_el3; 312 el3_state_t *state; 313 gp_regs_t *gp_regs; 314 315 /* Clear any residual register values from the context */ 316 zeromem(ctx, sizeof(*ctx)); 317 318 /* 319 * SCR_EL3 was initialised during reset sequence in macro 320 * el3_arch_init_common. This code modifies the SCR_EL3 fields that 321 * affect the next EL. 322 * 323 * The following fields are initially set to zero and then updated to 324 * the required value depending on the state of the SPSR_EL3 and the 325 * Security state and entrypoint attributes of the next EL. 326 */ 327 scr_el3 = read_scr(); 328 scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_EA_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT | 329 SCR_ST_BIT | SCR_HCE_BIT | SCR_NSE_BIT); 330 331 /* 332 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 333 * Exception level as specified by SPSR. 334 */ 335 if (GET_RW(ep->spsr) == MODE_RW_64) { 336 scr_el3 |= SCR_RW_BIT; 337 } 338 339 /* 340 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 341 * Secure timer registers to EL3, from AArch64 state only, if specified 342 * by the entrypoint attributes. If SEL2 is present and enabled, the ST 343 * bit always behaves as 1 (i.e. secure physical timer register access 344 * is not trapped) 345 */ 346 if (EP_GET_ST(ep->h.attr) != 0U) { 347 scr_el3 |= SCR_ST_BIT; 348 } 349 350 /* 351 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting 352 * SCR_EL3.HXEn. 353 */ 354 if (is_feat_hcx_supported()) { 355 scr_el3 |= SCR_HXEn_BIT; 356 } 357 358 /* 359 * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS 360 * registers are trapped to EL3. 361 */ 362 #if ENABLE_FEAT_RNG_TRAP 363 scr_el3 |= SCR_TRNDR_BIT; 364 #endif 365 366 #if FAULT_INJECTION_SUPPORT 367 /* Enable fault injection from lower ELs */ 368 scr_el3 |= SCR_FIEN_BIT; 369 #endif 370 371 /* 372 * SCR_EL3.TCR2EN: Enable access to TCR2_ELx for AArch64 if present. 373 */ 374 if (is_feat_tcr2_supported() && (GET_RW(ep->spsr) == MODE_RW_64)) { 375 scr_el3 |= SCR_TCR2EN_BIT; 376 } 377 378 /* 379 * SCR_EL3.PIEN: Enable permission indirection and overlay 380 * registers for AArch64 if present. 381 */ 382 if (is_feat_sxpie_supported() || is_feat_sxpoe_supported()) { 383 scr_el3 |= SCR_PIEN_BIT; 384 } 385 386 /* 387 * SCR_EL3.GCSEn: Enable GCS registers for AArch64 if present. 388 */ 389 if ((is_feat_gcs_supported()) && (GET_RW(ep->spsr) == MODE_RW_64)) { 390 scr_el3 |= SCR_GCSEn_BIT; 391 } 392 393 /* 394 * CPTR_EL3 was initialized out of reset, copy that value to the 395 * context register. 396 */ 397 write_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3, read_cptr_el3()); 398 399 /* 400 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 401 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 402 * next mode is Hyp. 403 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 404 * same conditions as HVC instructions and when the processor supports 405 * ARMv8.6-FGT. 406 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 407 * CNTPOFF_EL2 register under the same conditions as HVC instructions 408 * and when the processor supports ECV. 409 */ 410 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 411 || ((GET_RW(ep->spsr) != MODE_RW_64) 412 && (GET_M32(ep->spsr) == MODE32_hyp))) { 413 scr_el3 |= SCR_HCE_BIT; 414 415 if (is_feat_fgt_supported()) { 416 scr_el3 |= SCR_FGTEN_BIT; 417 } 418 419 if (is_feat_ecv_supported()) { 420 scr_el3 |= SCR_ECVEN_BIT; 421 } 422 } 423 424 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 425 if (is_feat_twed_supported()) { 426 /* Set delay in SCR_EL3 */ 427 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 428 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK) 429 << SCR_TWEDEL_SHIFT); 430 431 /* Enable WFE delay */ 432 scr_el3 |= SCR_TWEDEn_BIT; 433 } 434 435 /* 436 * Populate EL3 state so that we've the right context 437 * before doing ERET 438 */ 439 state = get_el3state_ctx(ctx); 440 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 441 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 442 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 443 444 /* 445 * Store the X0-X7 value from the entrypoint into the context 446 * Use memcpy as we are in control of the layout of the structures 447 */ 448 gp_regs = get_gpregs_ctx(ctx); 449 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 450 } 451 452 /******************************************************************************* 453 * Context management library initialization routine. This library is used by 454 * runtime services to share pointers to 'cpu_context' structures for secure 455 * non-secure and realm states. Management of the structures and their associated 456 * memory is not done by the context management library e.g. the PSCI service 457 * manages the cpu context used for entry from and exit to the non-secure state. 458 * The Secure payload dispatcher service manages the context(s) corresponding to 459 * the secure state. It also uses this library to get access to the non-secure 460 * state cpu context pointers. 461 * Lastly, this library provides the API to make SP_EL3 point to the cpu context 462 * which will be used for programming an entry into a lower EL. The same context 463 * will be used to save state upon exception entry from that EL. 464 ******************************************************************************/ 465 void __init cm_init(void) 466 { 467 /* 468 * The context management library has only global data to initialize, but 469 * that will be done when the BSS is zeroed out. 470 */ 471 } 472 473 /******************************************************************************* 474 * This is the high-level function used to initialize the cpu_context 'ctx' for 475 * first use. It performs initializations that are common to all security states 476 * and initializations specific to the security state specified in 'ep' 477 ******************************************************************************/ 478 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 479 { 480 unsigned int security_state; 481 482 assert(ctx != NULL); 483 484 /* 485 * Perform initializations that are common 486 * to all security states 487 */ 488 setup_context_common(ctx, ep); 489 490 security_state = GET_SECURITY_STATE(ep->h.attr); 491 492 /* Perform security state specific initializations */ 493 switch (security_state) { 494 case SECURE: 495 setup_secure_context(ctx, ep); 496 break; 497 #if ENABLE_RME 498 case REALM: 499 setup_realm_context(ctx, ep); 500 break; 501 #endif 502 case NON_SECURE: 503 setup_ns_context(ctx, ep); 504 break; 505 default: 506 ERROR("Invalid security state\n"); 507 panic(); 508 break; 509 } 510 } 511 512 /******************************************************************************* 513 * Enable architecture extensions for EL3 execution. This function only updates 514 * registers in-place which are expected to either never change or be 515 * overwritten by el3_exit. 516 ******************************************************************************/ 517 #if IMAGE_BL31 518 void cm_manage_extensions_el3(void) 519 { 520 if (is_feat_spe_supported()) { 521 spe_init_el3(); 522 } 523 524 if (is_feat_amu_supported()) { 525 amu_init_el3(); 526 } 527 528 if (is_feat_sme_supported()) { 529 sme_init_el3(); 530 } 531 532 if (is_feat_mpam_supported()) { 533 mpam_init_el3(); 534 } 535 536 if (is_feat_trbe_supported()) { 537 trbe_init_el3(); 538 } 539 540 if (is_feat_brbe_supported()) { 541 brbe_init_el3(); 542 } 543 544 if (is_feat_trf_supported()) { 545 trf_init_el3(); 546 } 547 548 pmuv3_init_el3(); 549 } 550 #endif /* IMAGE_BL31 */ 551 552 /******************************************************************************* 553 * Enable architecture extensions on first entry to Non-secure world. 554 ******************************************************************************/ 555 static void manage_extensions_nonsecure(cpu_context_t *ctx) 556 { 557 #if IMAGE_BL31 558 if (is_feat_amu_supported()) { 559 amu_enable(ctx); 560 } 561 562 /* Enable SVE and FPU/SIMD */ 563 if (is_feat_sve_supported()) { 564 sve_enable(ctx); 565 } 566 567 if (is_feat_sme_supported()) { 568 sme_enable(ctx); 569 } 570 571 if (is_feat_sys_reg_trace_supported()) { 572 sys_reg_trace_enable(ctx); 573 } 574 575 pmuv3_enable(ctx); 576 #endif /* IMAGE_BL31 */ 577 } 578 579 /* TODO: move to lib/extensions/pauth when it has been ported to FEAT_STATE */ 580 static __unused void enable_pauth_el2(void) 581 { 582 u_register_t hcr_el2 = read_hcr_el2(); 583 /* 584 * For Armv8.3 pointer authentication feature, disable traps to EL2 when 585 * accessing key registers or using pointer authentication instructions 586 * from lower ELs. 587 */ 588 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 589 590 write_hcr_el2(hcr_el2); 591 } 592 593 /******************************************************************************* 594 * Enable architecture extensions in-place at EL2 on first entry to Non-secure 595 * world when EL2 is empty and unused. 596 ******************************************************************************/ 597 static void manage_extensions_nonsecure_el2_unused(void) 598 { 599 #if IMAGE_BL31 600 if (is_feat_spe_supported()) { 601 spe_init_el2_unused(); 602 } 603 604 if (is_feat_amu_supported()) { 605 amu_init_el2_unused(); 606 } 607 608 if (is_feat_mpam_supported()) { 609 mpam_init_el2_unused(); 610 } 611 612 if (is_feat_trbe_supported()) { 613 trbe_init_el2_unused(); 614 } 615 616 if (is_feat_sys_reg_trace_supported()) { 617 sys_reg_trace_init_el2_unused(); 618 } 619 620 if (is_feat_trf_supported()) { 621 trf_init_el2_unused(); 622 } 623 624 pmuv3_init_el2_unused(); 625 626 if (is_feat_sve_supported()) { 627 sve_init_el2_unused(); 628 } 629 630 if (is_feat_sme_supported()) { 631 sme_init_el2_unused(); 632 } 633 634 #if ENABLE_PAUTH 635 enable_pauth_el2(); 636 #endif /* ENABLE_PAUTH */ 637 #endif /* IMAGE_BL31 */ 638 } 639 640 /******************************************************************************* 641 * Enable architecture extensions on first entry to Secure world. 642 ******************************************************************************/ 643 static void manage_extensions_secure(cpu_context_t *ctx) 644 { 645 #if IMAGE_BL31 646 if (is_feat_sve_supported()) { 647 if (ENABLE_SVE_FOR_SWD) { 648 /* 649 * Enable SVE and FPU in secure context, secure manager must 650 * ensure that the SVE and FPU register contexts are properly 651 * managed. 652 */ 653 sve_enable(ctx); 654 } else { 655 /* 656 * Disable SVE and FPU in secure context so non-secure world 657 * can safely use them. 658 */ 659 sve_disable(ctx); 660 } 661 } 662 663 if (is_feat_sme_supported()) { 664 if (ENABLE_SME_FOR_SWD) { 665 /* 666 * Enable SME, SVE, FPU/SIMD in secure context, secure manager 667 * must ensure SME, SVE, and FPU/SIMD context properly managed. 668 */ 669 sme_init_el3(); 670 sme_enable(ctx); 671 } else { 672 /* 673 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 674 * world can safely use the associated registers. 675 */ 676 sme_disable(ctx); 677 } 678 } 679 680 /* NS can access this but Secure shouldn't */ 681 if (is_feat_sys_reg_trace_supported()) { 682 sys_reg_trace_disable(ctx); 683 } 684 #endif /* IMAGE_BL31 */ 685 } 686 687 /******************************************************************************* 688 * The following function initializes the cpu_context for a CPU specified by 689 * its `cpu_idx` for first use, and sets the initial entrypoint state as 690 * specified by the entry_point_info structure. 691 ******************************************************************************/ 692 void cm_init_context_by_index(unsigned int cpu_idx, 693 const entry_point_info_t *ep) 694 { 695 cpu_context_t *ctx; 696 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 697 cm_setup_context(ctx, ep); 698 } 699 700 /******************************************************************************* 701 * The following function initializes the cpu_context for the current CPU 702 * for first use, and sets the initial entrypoint state as specified by the 703 * entry_point_info structure. 704 ******************************************************************************/ 705 void cm_init_my_context(const entry_point_info_t *ep) 706 { 707 cpu_context_t *ctx; 708 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 709 cm_setup_context(ctx, ep); 710 } 711 712 /* EL2 present but unused, need to disable safely. SCTLR_EL2 can be ignored */ 713 static __unused void init_nonsecure_el2_unused(cpu_context_t *ctx) 714 { 715 u_register_t hcr_el2 = HCR_RESET_VAL; 716 u_register_t mdcr_el2; 717 u_register_t scr_el3; 718 719 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 720 721 /* Set EL2 register width: Set HCR_EL2.RW to match SCR_EL3.RW */ 722 if ((scr_el3 & SCR_RW_BIT) != 0U) { 723 hcr_el2 |= HCR_RW_BIT; 724 } 725 726 write_hcr_el2(hcr_el2); 727 728 /* 729 * Initialise CPTR_EL2 setting all fields rather than relying on the hw. 730 * All fields have architecturally UNKNOWN reset values. 731 */ 732 write_cptr_el2(CPTR_EL2_RESET_VAL); 733 734 /* 735 * Initialise CNTHCTL_EL2. All fields are architecturally UNKNOWN on 736 * reset and are set to zero except for field(s) listed below. 737 * 738 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to Hyp mode of 739 * Non-secure EL0 and EL1 accesses to the physical timer registers. 740 * 741 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to Hyp mode of 742 * Non-secure EL0 and EL1 accesses to the physical counter registers. 743 */ 744 write_cnthctl_el2(CNTHCTL_RESET_VAL | EL1PCEN_BIT | EL1PCTEN_BIT); 745 746 /* 747 * Initialise CNTVOFF_EL2 to zero as it resets to an architecturally 748 * UNKNOWN value. 749 */ 750 write_cntvoff_el2(0); 751 752 /* 753 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and MPIDR_EL1 754 * respectively. 755 */ 756 write_vpidr_el2(read_midr_el1()); 757 write_vmpidr_el2(read_mpidr_el1()); 758 759 /* 760 * Initialise VTTBR_EL2. All fields are architecturally UNKNOWN on reset. 761 * 762 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 2 address 763 * translation is disabled, cache maintenance operations depend on the 764 * VMID. 765 * 766 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address translation is 767 * disabled. 768 */ 769 write_vttbr_el2(VTTBR_RESET_VAL & 770 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) | 771 (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 772 773 /* 774 * Initialise MDCR_EL2, setting all fields rather than relying on hw. 775 * Some fields are architecturally UNKNOWN on reset. 776 * 777 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and EL1 System 778 * register accesses to the Debug ROM registers are not trapped to EL2. 779 * 780 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 System register 781 * accesses to the powerdown debug registers are not trapped to EL2. 782 * 783 * MDCR_EL2.TDA: Set to zero so that System register accesses to the 784 * debug registers do not trap to EL2. 785 * 786 * MDCR_EL2.TDE: Set to zero so that debug exceptions are not routed to 787 * EL2. 788 */ 789 mdcr_el2 = MDCR_EL2_RESET_VAL & 790 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | MDCR_EL2_TDA_BIT | 791 MDCR_EL2_TDE_BIT); 792 793 write_mdcr_el2(mdcr_el2); 794 795 /* 796 * Initialise HSTR_EL2. All fields are architecturally UNKNOWN on reset. 797 * 798 * HSTR_EL2.T<n>: Set all these fields to zero so that Non-secure EL0 or 799 * EL1 accesses to System registers do not trap to EL2. 800 */ 801 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 802 803 /* 804 * Initialise CNTHP_CTL_EL2. All fields are architecturally UNKNOWN on 805 * reset. 806 * 807 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 physical timer 808 * and prevent timer interrupts. 809 */ 810 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & ~(CNTHP_CTL_ENABLE_BIT)); 811 812 manage_extensions_nonsecure_el2_unused(); 813 } 814 815 /******************************************************************************* 816 * Prepare the CPU system registers for first entry into realm, secure, or 817 * normal world. 818 * 819 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 820 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 821 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 822 * For all entries, the EL1 registers are initialized from the cpu_context 823 ******************************************************************************/ 824 void cm_prepare_el3_exit(uint32_t security_state) 825 { 826 u_register_t sctlr_elx, scr_el3; 827 cpu_context_t *ctx = cm_get_context(security_state); 828 829 assert(ctx != NULL); 830 831 if (security_state == NON_SECURE) { 832 uint64_t el2_implemented = el_implemented(2); 833 834 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 835 CTX_SCR_EL3); 836 837 if (((scr_el3 & SCR_HCE_BIT) != 0U) 838 || (el2_implemented != EL_IMPL_NONE)) { 839 /* 840 * If context is not being used for EL2, initialize 841 * HCRX_EL2 with its init value here. 842 */ 843 if (is_feat_hcx_supported()) { 844 write_hcrx_el2(HCRX_EL2_INIT_VAL); 845 } 846 847 /* 848 * Initialize Fine-grained trap registers introduced 849 * by FEAT_FGT so all traps are initially disabled when 850 * switching to EL2 or a lower EL, preventing undesired 851 * behavior. 852 */ 853 if (is_feat_fgt_supported()) { 854 /* 855 * Initialize HFG*_EL2 registers with a default 856 * value so legacy systems unaware of FEAT_FGT 857 * do not get trapped due to their lack of 858 * initialization for this feature. 859 */ 860 write_hfgitr_el2(HFGITR_EL2_INIT_VAL); 861 write_hfgrtr_el2(HFGRTR_EL2_INIT_VAL); 862 write_hfgwtr_el2(HFGWTR_EL2_INIT_VAL); 863 } 864 } 865 866 867 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 868 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */ 869 sctlr_elx = read_ctx_reg(get_el1_sysregs_ctx(ctx), 870 CTX_SCTLR_EL1); 871 sctlr_elx &= SCTLR_EE_BIT; 872 sctlr_elx |= SCTLR_EL2_RES1; 873 #if ERRATA_A75_764081 874 /* 875 * If workaround of errata 764081 for Cortex-A75 is used 876 * then set SCTLR_EL2.IESB to enable Implicit Error 877 * Synchronization Barrier. 878 */ 879 sctlr_elx |= SCTLR_IESB_BIT; 880 #endif 881 write_sctlr_el2(sctlr_elx); 882 } else if (el2_implemented != EL_IMPL_NONE) { 883 init_nonsecure_el2_unused(ctx); 884 } 885 } 886 887 cm_el1_sysregs_context_restore(security_state); 888 cm_set_next_eret_context(security_state); 889 } 890 891 #if CTX_INCLUDE_EL2_REGS 892 893 static void el2_sysregs_context_save_fgt(el2_sysregs_t *ctx) 894 { 895 write_ctx_reg(ctx, CTX_HDFGRTR_EL2, read_hdfgrtr_el2()); 896 if (is_feat_amu_supported()) { 897 write_ctx_reg(ctx, CTX_HAFGRTR_EL2, read_hafgrtr_el2()); 898 } 899 write_ctx_reg(ctx, CTX_HDFGWTR_EL2, read_hdfgwtr_el2()); 900 write_ctx_reg(ctx, CTX_HFGITR_EL2, read_hfgitr_el2()); 901 write_ctx_reg(ctx, CTX_HFGRTR_EL2, read_hfgrtr_el2()); 902 write_ctx_reg(ctx, CTX_HFGWTR_EL2, read_hfgwtr_el2()); 903 } 904 905 static void el2_sysregs_context_restore_fgt(el2_sysregs_t *ctx) 906 { 907 write_hdfgrtr_el2(read_ctx_reg(ctx, CTX_HDFGRTR_EL2)); 908 if (is_feat_amu_supported()) { 909 write_hafgrtr_el2(read_ctx_reg(ctx, CTX_HAFGRTR_EL2)); 910 } 911 write_hdfgwtr_el2(read_ctx_reg(ctx, CTX_HDFGWTR_EL2)); 912 write_hfgitr_el2(read_ctx_reg(ctx, CTX_HFGITR_EL2)); 913 write_hfgrtr_el2(read_ctx_reg(ctx, CTX_HFGRTR_EL2)); 914 write_hfgwtr_el2(read_ctx_reg(ctx, CTX_HFGWTR_EL2)); 915 } 916 917 static void el2_sysregs_context_save_mpam(el2_sysregs_t *ctx) 918 { 919 u_register_t mpam_idr = read_mpamidr_el1(); 920 921 write_ctx_reg(ctx, CTX_MPAM2_EL2, read_mpam2_el2()); 922 923 /* 924 * The context registers that we intend to save would be part of the 925 * PE's system register frame only if MPAMIDR_EL1.HAS_HCR == 1. 926 */ 927 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 928 return; 929 } 930 931 /* 932 * MPAMHCR_EL2, MPAMVPMV_EL2 and MPAMVPM0_EL2 are always present if 933 * MPAMIDR_HAS_HCR_BIT == 1. 934 */ 935 write_ctx_reg(ctx, CTX_MPAMHCR_EL2, read_mpamhcr_el2()); 936 write_ctx_reg(ctx, CTX_MPAMVPM0_EL2, read_mpamvpm0_el2()); 937 write_ctx_reg(ctx, CTX_MPAMVPMV_EL2, read_mpamvpmv_el2()); 938 939 /* 940 * The number of MPAMVPM registers is implementation defined, their 941 * number is stored in the MPAMIDR_EL1 register. 942 */ 943 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 944 case 7: 945 write_ctx_reg(ctx, CTX_MPAMVPM7_EL2, read_mpamvpm7_el2()); 946 __fallthrough; 947 case 6: 948 write_ctx_reg(ctx, CTX_MPAMVPM6_EL2, read_mpamvpm6_el2()); 949 __fallthrough; 950 case 5: 951 write_ctx_reg(ctx, CTX_MPAMVPM5_EL2, read_mpamvpm5_el2()); 952 __fallthrough; 953 case 4: 954 write_ctx_reg(ctx, CTX_MPAMVPM4_EL2, read_mpamvpm4_el2()); 955 __fallthrough; 956 case 3: 957 write_ctx_reg(ctx, CTX_MPAMVPM3_EL2, read_mpamvpm3_el2()); 958 __fallthrough; 959 case 2: 960 write_ctx_reg(ctx, CTX_MPAMVPM2_EL2, read_mpamvpm2_el2()); 961 __fallthrough; 962 case 1: 963 write_ctx_reg(ctx, CTX_MPAMVPM1_EL2, read_mpamvpm1_el2()); 964 break; 965 } 966 } 967 968 static void el2_sysregs_context_restore_mpam(el2_sysregs_t *ctx) 969 { 970 u_register_t mpam_idr = read_mpamidr_el1(); 971 972 write_mpam2_el2(read_ctx_reg(ctx, CTX_MPAM2_EL2)); 973 974 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 975 return; 976 } 977 978 write_mpamhcr_el2(read_ctx_reg(ctx, CTX_MPAMHCR_EL2)); 979 write_mpamvpm0_el2(read_ctx_reg(ctx, CTX_MPAMVPM0_EL2)); 980 write_mpamvpmv_el2(read_ctx_reg(ctx, CTX_MPAMVPMV_EL2)); 981 982 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 983 case 7: 984 write_mpamvpm7_el2(read_ctx_reg(ctx, CTX_MPAMVPM7_EL2)); 985 __fallthrough; 986 case 6: 987 write_mpamvpm6_el2(read_ctx_reg(ctx, CTX_MPAMVPM6_EL2)); 988 __fallthrough; 989 case 5: 990 write_mpamvpm5_el2(read_ctx_reg(ctx, CTX_MPAMVPM5_EL2)); 991 __fallthrough; 992 case 4: 993 write_mpamvpm4_el2(read_ctx_reg(ctx, CTX_MPAMVPM4_EL2)); 994 __fallthrough; 995 case 3: 996 write_mpamvpm3_el2(read_ctx_reg(ctx, CTX_MPAMVPM3_EL2)); 997 __fallthrough; 998 case 2: 999 write_mpamvpm2_el2(read_ctx_reg(ctx, CTX_MPAMVPM2_EL2)); 1000 __fallthrough; 1001 case 1: 1002 write_mpamvpm1_el2(read_ctx_reg(ctx, CTX_MPAMVPM1_EL2)); 1003 break; 1004 } 1005 } 1006 1007 /* ----------------------------------------------------- 1008 * The following registers are not added: 1009 * AMEVCNTVOFF0<n>_EL2 1010 * AMEVCNTVOFF1<n>_EL2 1011 * ICH_AP0R<n>_EL2 1012 * ICH_AP1R<n>_EL2 1013 * ICH_LR<n>_EL2 1014 * ----------------------------------------------------- 1015 */ 1016 static void el2_sysregs_context_save_common(el2_sysregs_t *ctx) 1017 { 1018 write_ctx_reg(ctx, CTX_ACTLR_EL2, read_actlr_el2()); 1019 write_ctx_reg(ctx, CTX_AFSR0_EL2, read_afsr0_el2()); 1020 write_ctx_reg(ctx, CTX_AFSR1_EL2, read_afsr1_el2()); 1021 write_ctx_reg(ctx, CTX_AMAIR_EL2, read_amair_el2()); 1022 write_ctx_reg(ctx, CTX_CNTHCTL_EL2, read_cnthctl_el2()); 1023 write_ctx_reg(ctx, CTX_CNTVOFF_EL2, read_cntvoff_el2()); 1024 write_ctx_reg(ctx, CTX_CPTR_EL2, read_cptr_el2()); 1025 if (CTX_INCLUDE_AARCH32_REGS) { 1026 write_ctx_reg(ctx, CTX_DBGVCR32_EL2, read_dbgvcr32_el2()); 1027 } 1028 write_ctx_reg(ctx, CTX_ELR_EL2, read_elr_el2()); 1029 write_ctx_reg(ctx, CTX_ESR_EL2, read_esr_el2()); 1030 write_ctx_reg(ctx, CTX_FAR_EL2, read_far_el2()); 1031 write_ctx_reg(ctx, CTX_HACR_EL2, read_hacr_el2()); 1032 write_ctx_reg(ctx, CTX_HCR_EL2, read_hcr_el2()); 1033 write_ctx_reg(ctx, CTX_HPFAR_EL2, read_hpfar_el2()); 1034 write_ctx_reg(ctx, CTX_HSTR_EL2, read_hstr_el2()); 1035 write_ctx_reg(ctx, CTX_ICC_SRE_EL2, read_icc_sre_el2()); 1036 write_ctx_reg(ctx, CTX_ICH_HCR_EL2, read_ich_hcr_el2()); 1037 write_ctx_reg(ctx, CTX_ICH_VMCR_EL2, read_ich_vmcr_el2()); 1038 write_ctx_reg(ctx, CTX_MAIR_EL2, read_mair_el2()); 1039 write_ctx_reg(ctx, CTX_MDCR_EL2, read_mdcr_el2()); 1040 write_ctx_reg(ctx, CTX_SCTLR_EL2, read_sctlr_el2()); 1041 write_ctx_reg(ctx, CTX_SPSR_EL2, read_spsr_el2()); 1042 write_ctx_reg(ctx, CTX_SP_EL2, read_sp_el2()); 1043 write_ctx_reg(ctx, CTX_TCR_EL2, read_tcr_el2()); 1044 write_ctx_reg(ctx, CTX_TPIDR_EL2, read_tpidr_el2()); 1045 write_ctx_reg(ctx, CTX_TTBR0_EL2, read_ttbr0_el2()); 1046 write_ctx_reg(ctx, CTX_VBAR_EL2, read_vbar_el2()); 1047 write_ctx_reg(ctx, CTX_VMPIDR_EL2, read_vmpidr_el2()); 1048 write_ctx_reg(ctx, CTX_VPIDR_EL2, read_vpidr_el2()); 1049 write_ctx_reg(ctx, CTX_VTCR_EL2, read_vtcr_el2()); 1050 write_ctx_reg(ctx, CTX_VTTBR_EL2, read_vttbr_el2()); 1051 } 1052 1053 static void el2_sysregs_context_restore_common(el2_sysregs_t *ctx) 1054 { 1055 write_actlr_el2(read_ctx_reg(ctx, CTX_ACTLR_EL2)); 1056 write_afsr0_el2(read_ctx_reg(ctx, CTX_AFSR0_EL2)); 1057 write_afsr1_el2(read_ctx_reg(ctx, CTX_AFSR1_EL2)); 1058 write_amair_el2(read_ctx_reg(ctx, CTX_AMAIR_EL2)); 1059 write_cnthctl_el2(read_ctx_reg(ctx, CTX_CNTHCTL_EL2)); 1060 write_cntvoff_el2(read_ctx_reg(ctx, CTX_CNTVOFF_EL2)); 1061 write_cptr_el2(read_ctx_reg(ctx, CTX_CPTR_EL2)); 1062 if (CTX_INCLUDE_AARCH32_REGS) { 1063 write_dbgvcr32_el2(read_ctx_reg(ctx, CTX_DBGVCR32_EL2)); 1064 } 1065 write_elr_el2(read_ctx_reg(ctx, CTX_ELR_EL2)); 1066 write_esr_el2(read_ctx_reg(ctx, CTX_ESR_EL2)); 1067 write_far_el2(read_ctx_reg(ctx, CTX_FAR_EL2)); 1068 write_hacr_el2(read_ctx_reg(ctx, CTX_HACR_EL2)); 1069 write_hcr_el2(read_ctx_reg(ctx, CTX_HCR_EL2)); 1070 write_hpfar_el2(read_ctx_reg(ctx, CTX_HPFAR_EL2)); 1071 write_hstr_el2(read_ctx_reg(ctx, CTX_HSTR_EL2)); 1072 write_icc_sre_el2(read_ctx_reg(ctx, CTX_ICC_SRE_EL2)); 1073 write_ich_hcr_el2(read_ctx_reg(ctx, CTX_ICH_HCR_EL2)); 1074 write_ich_vmcr_el2(read_ctx_reg(ctx, CTX_ICH_VMCR_EL2)); 1075 write_mair_el2(read_ctx_reg(ctx, CTX_MAIR_EL2)); 1076 write_mdcr_el2(read_ctx_reg(ctx, CTX_MDCR_EL2)); 1077 write_sctlr_el2(read_ctx_reg(ctx, CTX_SCTLR_EL2)); 1078 write_spsr_el2(read_ctx_reg(ctx, CTX_SPSR_EL2)); 1079 write_sp_el2(read_ctx_reg(ctx, CTX_SP_EL2)); 1080 write_tcr_el2(read_ctx_reg(ctx, CTX_TCR_EL2)); 1081 write_tpidr_el2(read_ctx_reg(ctx, CTX_TPIDR_EL2)); 1082 write_ttbr0_el2(read_ctx_reg(ctx, CTX_TTBR0_EL2)); 1083 write_vbar_el2(read_ctx_reg(ctx, CTX_VBAR_EL2)); 1084 write_vmpidr_el2(read_ctx_reg(ctx, CTX_VMPIDR_EL2)); 1085 write_vpidr_el2(read_ctx_reg(ctx, CTX_VPIDR_EL2)); 1086 write_vtcr_el2(read_ctx_reg(ctx, CTX_VTCR_EL2)); 1087 write_vttbr_el2(read_ctx_reg(ctx, CTX_VTTBR_EL2)); 1088 } 1089 1090 /******************************************************************************* 1091 * Save EL2 sysreg context 1092 ******************************************************************************/ 1093 void cm_el2_sysregs_context_save(uint32_t security_state) 1094 { 1095 u_register_t scr_el3 = read_scr(); 1096 1097 /* 1098 * Always save the non-secure and realm EL2 context, only save the 1099 * S-EL2 context if S-EL2 is enabled. 1100 */ 1101 if ((security_state != SECURE) || 1102 ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) { 1103 cpu_context_t *ctx; 1104 el2_sysregs_t *el2_sysregs_ctx; 1105 1106 ctx = cm_get_context(security_state); 1107 assert(ctx != NULL); 1108 1109 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1110 1111 el2_sysregs_context_save_common(el2_sysregs_ctx); 1112 #if CTX_INCLUDE_MTE_REGS 1113 write_ctx_reg(el2_sysregs_ctx, CTX_TFSR_EL2, read_tfsr_el2()); 1114 #endif 1115 if (is_feat_mpam_supported()) { 1116 el2_sysregs_context_save_mpam(el2_sysregs_ctx); 1117 } 1118 1119 if (is_feat_fgt_supported()) { 1120 el2_sysregs_context_save_fgt(el2_sysregs_ctx); 1121 } 1122 1123 if (is_feat_ecv_v2_supported()) { 1124 write_ctx_reg(el2_sysregs_ctx, CTX_CNTPOFF_EL2, 1125 read_cntpoff_el2()); 1126 } 1127 1128 if (is_feat_vhe_supported()) { 1129 write_ctx_reg(el2_sysregs_ctx, CTX_CONTEXTIDR_EL2, 1130 read_contextidr_el2()); 1131 write_ctx_reg(el2_sysregs_ctx, CTX_TTBR1_EL2, 1132 read_ttbr1_el2()); 1133 } 1134 1135 if (is_feat_ras_supported()) { 1136 write_ctx_reg(el2_sysregs_ctx, CTX_VDISR_EL2, 1137 read_vdisr_el2()); 1138 write_ctx_reg(el2_sysregs_ctx, CTX_VSESR_EL2, 1139 read_vsesr_el2()); 1140 } 1141 1142 if (is_feat_nv2_supported()) { 1143 write_ctx_reg(el2_sysregs_ctx, CTX_VNCR_EL2, 1144 read_vncr_el2()); 1145 } 1146 1147 if (is_feat_trf_supported()) { 1148 write_ctx_reg(el2_sysregs_ctx, CTX_TRFCR_EL2, read_trfcr_el2()); 1149 } 1150 1151 if (is_feat_csv2_2_supported()) { 1152 write_ctx_reg(el2_sysregs_ctx, CTX_SCXTNUM_EL2, 1153 read_scxtnum_el2()); 1154 } 1155 1156 if (is_feat_hcx_supported()) { 1157 write_ctx_reg(el2_sysregs_ctx, CTX_HCRX_EL2, read_hcrx_el2()); 1158 } 1159 if (is_feat_tcr2_supported()) { 1160 write_ctx_reg(el2_sysregs_ctx, CTX_TCR2_EL2, read_tcr2_el2()); 1161 } 1162 if (is_feat_sxpie_supported()) { 1163 write_ctx_reg(el2_sysregs_ctx, CTX_PIRE0_EL2, read_pire0_el2()); 1164 write_ctx_reg(el2_sysregs_ctx, CTX_PIR_EL2, read_pir_el2()); 1165 } 1166 if (is_feat_s2pie_supported()) { 1167 write_ctx_reg(el2_sysregs_ctx, CTX_S2PIR_EL2, read_s2pir_el2()); 1168 } 1169 if (is_feat_sxpoe_supported()) { 1170 write_ctx_reg(el2_sysregs_ctx, CTX_POR_EL2, read_por_el2()); 1171 } 1172 if (is_feat_gcs_supported()) { 1173 write_ctx_reg(el2_sysregs_ctx, CTX_GCSPR_EL2, read_gcspr_el2()); 1174 write_ctx_reg(el2_sysregs_ctx, CTX_GCSCR_EL2, read_gcscr_el2()); 1175 } 1176 } 1177 } 1178 1179 /******************************************************************************* 1180 * Restore EL2 sysreg context 1181 ******************************************************************************/ 1182 void cm_el2_sysregs_context_restore(uint32_t security_state) 1183 { 1184 u_register_t scr_el3 = read_scr(); 1185 1186 /* 1187 * Always restore the non-secure and realm EL2 context, only restore the 1188 * S-EL2 context if S-EL2 is enabled. 1189 */ 1190 if ((security_state != SECURE) || 1191 ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) { 1192 cpu_context_t *ctx; 1193 el2_sysregs_t *el2_sysregs_ctx; 1194 1195 ctx = cm_get_context(security_state); 1196 assert(ctx != NULL); 1197 1198 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1199 1200 el2_sysregs_context_restore_common(el2_sysregs_ctx); 1201 #if CTX_INCLUDE_MTE_REGS 1202 write_tfsr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TFSR_EL2)); 1203 #endif 1204 if (is_feat_mpam_supported()) { 1205 el2_sysregs_context_restore_mpam(el2_sysregs_ctx); 1206 } 1207 1208 if (is_feat_fgt_supported()) { 1209 el2_sysregs_context_restore_fgt(el2_sysregs_ctx); 1210 } 1211 1212 if (is_feat_ecv_v2_supported()) { 1213 write_cntpoff_el2(read_ctx_reg(el2_sysregs_ctx, 1214 CTX_CNTPOFF_EL2)); 1215 } 1216 1217 if (is_feat_vhe_supported()) { 1218 write_contextidr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_CONTEXTIDR_EL2)); 1219 write_ttbr1_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TTBR1_EL2)); 1220 } 1221 1222 if (is_feat_ras_supported()) { 1223 write_vdisr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_VDISR_EL2)); 1224 write_vsesr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_VSESR_EL2)); 1225 } 1226 1227 if (is_feat_nv2_supported()) { 1228 write_vncr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_VNCR_EL2)); 1229 } 1230 if (is_feat_trf_supported()) { 1231 write_trfcr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TRFCR_EL2)); 1232 } 1233 1234 if (is_feat_csv2_2_supported()) { 1235 write_scxtnum_el2(read_ctx_reg(el2_sysregs_ctx, 1236 CTX_SCXTNUM_EL2)); 1237 } 1238 1239 if (is_feat_hcx_supported()) { 1240 write_hcrx_el2(read_ctx_reg(el2_sysregs_ctx, CTX_HCRX_EL2)); 1241 } 1242 if (is_feat_tcr2_supported()) { 1243 write_tcr2_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TCR2_EL2)); 1244 } 1245 if (is_feat_sxpie_supported()) { 1246 write_pire0_el2(read_ctx_reg(el2_sysregs_ctx, CTX_PIRE0_EL2)); 1247 write_pir_el2(read_ctx_reg(el2_sysregs_ctx, CTX_PIR_EL2)); 1248 } 1249 if (is_feat_s2pie_supported()) { 1250 write_s2pir_el2(read_ctx_reg(el2_sysregs_ctx, CTX_S2PIR_EL2)); 1251 } 1252 if (is_feat_sxpoe_supported()) { 1253 write_por_el2(read_ctx_reg(el2_sysregs_ctx, CTX_POR_EL2)); 1254 } 1255 if (is_feat_gcs_supported()) { 1256 write_gcscr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_GCSCR_EL2)); 1257 write_gcspr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_GCSPR_EL2)); 1258 } 1259 } 1260 } 1261 #endif /* CTX_INCLUDE_EL2_REGS */ 1262 1263 /******************************************************************************* 1264 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS 1265 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly 1266 * updating EL1 and EL2 registers. Otherwise, it calls the generic 1267 * cm_prepare_el3_exit function. 1268 ******************************************************************************/ 1269 void cm_prepare_el3_exit_ns(void) 1270 { 1271 #if CTX_INCLUDE_EL2_REGS 1272 #if ENABLE_ASSERTIONS 1273 cpu_context_t *ctx = cm_get_context(NON_SECURE); 1274 assert(ctx != NULL); 1275 1276 /* Assert that EL2 is used. */ 1277 u_register_t scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 1278 assert(((scr_el3 & SCR_HCE_BIT) != 0UL) && 1279 (el_implemented(2U) != EL_IMPL_NONE)); 1280 #endif /* ENABLE_ASSERTIONS */ 1281 1282 /* 1283 * Set the NS bit to be able to access the ICC_SRE_EL2 1284 * register when restoring context. 1285 */ 1286 write_scr_el3(read_scr_el3() | SCR_NS_BIT); 1287 1288 /* 1289 * Ensure the NS bit change is committed before the EL2/EL1 1290 * state restoration. 1291 */ 1292 isb(); 1293 1294 /* Restore EL2 and EL1 sysreg contexts */ 1295 cm_el2_sysregs_context_restore(NON_SECURE); 1296 cm_el1_sysregs_context_restore(NON_SECURE); 1297 cm_set_next_eret_context(NON_SECURE); 1298 #else 1299 cm_prepare_el3_exit(NON_SECURE); 1300 #endif /* CTX_INCLUDE_EL2_REGS */ 1301 } 1302 1303 /******************************************************************************* 1304 * The next four functions are used by runtime services to save and restore 1305 * EL1 context on the 'cpu_context' structure for the specified security 1306 * state. 1307 ******************************************************************************/ 1308 void cm_el1_sysregs_context_save(uint32_t security_state) 1309 { 1310 cpu_context_t *ctx; 1311 1312 ctx = cm_get_context(security_state); 1313 assert(ctx != NULL); 1314 1315 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 1316 1317 #if IMAGE_BL31 1318 if (security_state == SECURE) 1319 PUBLISH_EVENT(cm_exited_secure_world); 1320 else 1321 PUBLISH_EVENT(cm_exited_normal_world); 1322 #endif 1323 } 1324 1325 void cm_el1_sysregs_context_restore(uint32_t security_state) 1326 { 1327 cpu_context_t *ctx; 1328 1329 ctx = cm_get_context(security_state); 1330 assert(ctx != NULL); 1331 1332 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 1333 1334 #if IMAGE_BL31 1335 if (security_state == SECURE) 1336 PUBLISH_EVENT(cm_entering_secure_world); 1337 else 1338 PUBLISH_EVENT(cm_entering_normal_world); 1339 #endif 1340 } 1341 1342 /******************************************************************************* 1343 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 1344 * given security state with the given entrypoint 1345 ******************************************************************************/ 1346 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 1347 { 1348 cpu_context_t *ctx; 1349 el3_state_t *state; 1350 1351 ctx = cm_get_context(security_state); 1352 assert(ctx != NULL); 1353 1354 /* Populate EL3 state so that ERET jumps to the correct entry */ 1355 state = get_el3state_ctx(ctx); 1356 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1357 } 1358 1359 /******************************************************************************* 1360 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 1361 * pertaining to the given security state 1362 ******************************************************************************/ 1363 void cm_set_elr_spsr_el3(uint32_t security_state, 1364 uintptr_t entrypoint, uint32_t spsr) 1365 { 1366 cpu_context_t *ctx; 1367 el3_state_t *state; 1368 1369 ctx = cm_get_context(security_state); 1370 assert(ctx != NULL); 1371 1372 /* Populate EL3 state so that ERET jumps to the correct entry */ 1373 state = get_el3state_ctx(ctx); 1374 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1375 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 1376 } 1377 1378 /******************************************************************************* 1379 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 1380 * pertaining to the given security state using the value and bit position 1381 * specified in the parameters. It preserves all other bits. 1382 ******************************************************************************/ 1383 void cm_write_scr_el3_bit(uint32_t security_state, 1384 uint32_t bit_pos, 1385 uint32_t value) 1386 { 1387 cpu_context_t *ctx; 1388 el3_state_t *state; 1389 u_register_t scr_el3; 1390 1391 ctx = cm_get_context(security_state); 1392 assert(ctx != NULL); 1393 1394 /* Ensure that the bit position is a valid one */ 1395 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 1396 1397 /* Ensure that the 'value' is only a bit wide */ 1398 assert(value <= 1U); 1399 1400 /* 1401 * Get the SCR_EL3 value from the cpu context, clear the desired bit 1402 * and set it to its new value. 1403 */ 1404 state = get_el3state_ctx(ctx); 1405 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 1406 scr_el3 &= ~(1UL << bit_pos); 1407 scr_el3 |= (u_register_t)value << bit_pos; 1408 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 1409 } 1410 1411 /******************************************************************************* 1412 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 1413 * given security state. 1414 ******************************************************************************/ 1415 u_register_t cm_get_scr_el3(uint32_t security_state) 1416 { 1417 cpu_context_t *ctx; 1418 el3_state_t *state; 1419 1420 ctx = cm_get_context(security_state); 1421 assert(ctx != NULL); 1422 1423 /* Populate EL3 state so that ERET jumps to the correct entry */ 1424 state = get_el3state_ctx(ctx); 1425 return read_ctx_reg(state, CTX_SCR_EL3); 1426 } 1427 1428 /******************************************************************************* 1429 * This function is used to program the context that's used for exception 1430 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 1431 * the required security state 1432 ******************************************************************************/ 1433 void cm_set_next_eret_context(uint32_t security_state) 1434 { 1435 cpu_context_t *ctx; 1436 1437 ctx = cm_get_context(security_state); 1438 assert(ctx != NULL); 1439 1440 cm_set_next_context(ctx); 1441 } 1442