1 /* 2 * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <stdbool.h> 10 #include <string.h> 11 12 #include <platform_def.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <arch_features.h> 17 #include <bl31/interrupt_mgmt.h> 18 #include <common/bl_common.h> 19 #include <common/debug.h> 20 #include <context.h> 21 #include <drivers/arm/gicv3.h> 22 #include <lib/cpus/cpu_ops.h> 23 #include <lib/cpus/errata.h> 24 #include <lib/el3_runtime/context_mgmt.h> 25 #include <lib/el3_runtime/cpu_data.h> 26 #include <lib/el3_runtime/pubsub_events.h> 27 #include <lib/extensions/amu.h> 28 #include <lib/extensions/brbe.h> 29 #include <lib/extensions/debug_v8p9.h> 30 #include <lib/extensions/fgt2.h> 31 #include <lib/extensions/fpmr.h> 32 #include <lib/extensions/mpam.h> 33 #include <lib/extensions/pmuv3.h> 34 #include <lib/extensions/sme.h> 35 #include <lib/extensions/spe.h> 36 #include <lib/extensions/sve.h> 37 #include <lib/extensions/sysreg128.h> 38 #include <lib/extensions/sys_reg_trace.h> 39 #include <lib/extensions/tcr2.h> 40 #include <lib/extensions/trbe.h> 41 #include <lib/extensions/trf.h> 42 #include <lib/utils.h> 43 44 #if ENABLE_FEAT_TWED 45 /* Make sure delay value fits within the range(0-15) */ 46 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check); 47 #endif /* ENABLE_FEAT_TWED */ 48 49 per_world_context_t per_world_context[CPU_DATA_CONTEXT_NUM]; 50 static bool has_secure_perworld_init; 51 52 static void manage_extensions_nonsecure(cpu_context_t *ctx); 53 static void manage_extensions_secure(cpu_context_t *ctx); 54 static void manage_extensions_secure_per_world(void); 55 56 #if ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) 57 static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep) 58 { 59 u_register_t sctlr_elx, actlr_elx; 60 61 /* 62 * Initialise SCTLR_EL1 to the reset value corresponding to the target 63 * execution state setting all fields rather than relying on the hw. 64 * Some fields have architecturally UNKNOWN reset values and these are 65 * set to zero. 66 * 67 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 68 * 69 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 70 * required by PSCI specification) 71 */ 72 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 73 if (GET_RW(ep->spsr) == MODE_RW_64) { 74 sctlr_elx |= SCTLR_EL1_RES1; 75 } else { 76 /* 77 * If the target execution state is AArch32 then the following 78 * fields need to be set. 79 * 80 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 81 * instructions are not trapped to EL1. 82 * 83 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 84 * instructions are not trapped to EL1. 85 * 86 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 87 * CP15DMB, CP15DSB, and CP15ISB instructions. 88 */ 89 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 90 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 91 } 92 93 /* 94 * If workaround of errata 764081 for Cortex-A75 is used then set 95 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 96 */ 97 if (errata_a75_764081_applies()) { 98 sctlr_elx |= SCTLR_IESB_BIT; 99 } 100 101 /* Store the initialised SCTLR_EL1 value in the cpu_context */ 102 write_ctx_sctlr_el1_reg_errata(ctx, sctlr_elx); 103 104 /* 105 * Base the context ACTLR_EL1 on the current value, as it is 106 * implementation defined. The context restore process will write 107 * the value from the context to the actual register and can cause 108 * problems for processor cores that don't expect certain bits to 109 * be zero. 110 */ 111 actlr_elx = read_actlr_el1(); 112 write_el1_ctx_common(get_el1_sysregs_ctx(ctx), actlr_el1, actlr_elx); 113 } 114 #endif /* (IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS)) */ 115 116 /****************************************************************************** 117 * This function performs initializations that are specific to SECURE state 118 * and updates the cpu context specified by 'ctx'. 119 *****************************************************************************/ 120 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep) 121 { 122 u_register_t scr_el3; 123 el3_state_t *state; 124 125 state = get_el3state_ctx(ctx); 126 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 127 128 #if defined(IMAGE_BL31) && !defined(SPD_spmd) 129 /* 130 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 131 * indicated by the interrupt routing model for BL31. 132 */ 133 scr_el3 |= get_scr_el3_from_routing_model(SECURE); 134 #endif 135 136 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 137 if (is_feat_mte2_supported()) { 138 scr_el3 |= SCR_ATA_BIT; 139 } 140 141 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 142 143 /* 144 * Initialize EL1 context registers unless SPMC is running 145 * at S-EL2. 146 */ 147 #if (!SPMD_SPM_AT_SEL2) 148 setup_el1_context(ctx, ep); 149 #endif 150 151 manage_extensions_secure(ctx); 152 153 /** 154 * manage_extensions_secure_per_world api has to be executed once, 155 * as the registers getting initialised, maintain constant value across 156 * all the cpus for the secure world. 157 * Henceforth, this check ensures that the registers are initialised once 158 * and avoids re-initialization from multiple cores. 159 */ 160 if (!has_secure_perworld_init) { 161 manage_extensions_secure_per_world(); 162 } 163 } 164 165 #if ENABLE_RME 166 /****************************************************************************** 167 * This function performs initializations that are specific to REALM state 168 * and updates the cpu context specified by 'ctx'. 169 *****************************************************************************/ 170 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep) 171 { 172 u_register_t scr_el3; 173 el3_state_t *state; 174 175 state = get_el3state_ctx(ctx); 176 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 177 178 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT; 179 180 /* CSV2 version 2 and above */ 181 if (is_feat_csv2_2_supported()) { 182 /* Enable access to the SCXTNUM_ELx registers. */ 183 scr_el3 |= SCR_EnSCXT_BIT; 184 } 185 186 if (is_feat_sctlr2_supported()) { 187 /* Set the SCTLR2En bit in SCR_EL3 to enable access to 188 * SCTLR2_ELx registers. 189 */ 190 scr_el3 |= SCR_SCTLR2En_BIT; 191 } 192 193 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 194 195 if (is_feat_fgt2_supported()) { 196 fgt2_enable(ctx); 197 } 198 199 if (is_feat_debugv8p9_supported()) { 200 debugv8p9_extended_bp_wp_enable(ctx); 201 } 202 203 if (is_feat_brbe_supported()) { 204 brbe_enable(ctx); 205 } 206 207 } 208 #endif /* ENABLE_RME */ 209 210 /****************************************************************************** 211 * This function performs initializations that are specific to NON-SECURE state 212 * and updates the cpu context specified by 'ctx'. 213 *****************************************************************************/ 214 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep) 215 { 216 u_register_t scr_el3; 217 el3_state_t *state; 218 219 state = get_el3state_ctx(ctx); 220 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 221 222 /* SCR_NS: Set the NS bit */ 223 scr_el3 |= SCR_NS_BIT; 224 225 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 226 if (is_feat_mte2_supported()) { 227 scr_el3 |= SCR_ATA_BIT; 228 } 229 230 #if !CTX_INCLUDE_PAUTH_REGS 231 /* 232 * Pointer Authentication feature, if present, is always enabled by default 233 * for Non secure lower exception levels. We do not have an explicit 234 * flag to set it. 235 * CTX_INCLUDE_PAUTH_REGS flag, is explicitly used to enable for lower 236 * exception levels of secure and realm worlds. 237 * 238 * To prevent the leakage between the worlds during world switch, 239 * we enable it only for the non-secure world. 240 * 241 * If the Secure/realm world wants to use pointer authentication, 242 * CTX_INCLUDE_PAUTH_REGS must be explicitly set to 1, in which case 243 * it will be enabled globally for all the contexts. 244 * 245 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 246 * other than EL3 247 * 248 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 249 * than EL3 250 */ 251 if (is_armv8_3_pauth_present()) { 252 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 253 } 254 #endif /* CTX_INCLUDE_PAUTH_REGS */ 255 256 #if HANDLE_EA_EL3_FIRST_NS 257 /* SCR_EL3.EA: Route External Abort and SError Interrupt to EL3. */ 258 scr_el3 |= SCR_EA_BIT; 259 #endif 260 261 #if RAS_TRAP_NS_ERR_REC_ACCESS 262 /* 263 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 264 * and RAS ERX registers from EL1 and EL2(from any security state) 265 * are trapped to EL3. 266 * Set here to trap only for NS EL1/EL2 267 */ 268 scr_el3 |= SCR_TERR_BIT; 269 #endif 270 271 /* CSV2 version 2 and above */ 272 if (is_feat_csv2_2_supported()) { 273 /* Enable access to the SCXTNUM_ELx registers. */ 274 scr_el3 |= SCR_EnSCXT_BIT; 275 } 276 277 #ifdef IMAGE_BL31 278 /* 279 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 280 * indicated by the interrupt routing model for BL31. 281 */ 282 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE); 283 #endif 284 285 if (is_feat_the_supported()) { 286 /* Set the RCWMASKEn bit in SCR_EL3 to enable access to 287 * RCWMASK_EL1 and RCWSMASK_EL1 registers. 288 */ 289 scr_el3 |= SCR_RCWMASKEn_BIT; 290 } 291 292 if (is_feat_sctlr2_supported()) { 293 /* Set the SCTLR2En bit in SCR_EL3 to enable access to 294 * SCTLR2_ELx registers. 295 */ 296 scr_el3 |= SCR_SCTLR2En_BIT; 297 } 298 299 if (is_feat_d128_supported()) { 300 /* Set the D128En bit in SCR_EL3 to enable access to 128-bit 301 * versions of TTBR0_EL1, TTBR1_EL1, RCWMASK_EL1, RCWSMASK_EL1, 302 * PAR_EL1 and TTBR1_EL2, TTBR0_EL2 and VTTBR_EL2 registers. 303 */ 304 scr_el3 |= SCR_D128En_BIT; 305 } 306 307 if (is_feat_fpmr_supported()) { 308 /* Set the EnFPM bit in SCR_EL3 to enable access to FPMR 309 * register. 310 */ 311 scr_el3 |= SCR_EnFPM_BIT; 312 } 313 314 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 315 316 /* Initialize EL2 context registers */ 317 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 318 319 /* 320 * Initialize SCTLR_EL2 context register with reset value. 321 */ 322 write_el2_ctx_common(get_el2_sysregs_ctx(ctx), sctlr_el2, SCTLR_EL2_RES1); 323 324 if (is_feat_hcx_supported()) { 325 /* 326 * Initialize register HCRX_EL2 with its init value. 327 * As the value of HCRX_EL2 is UNKNOWN on reset, there is a 328 * chance that this can lead to unexpected behavior in lower 329 * ELs that have not been updated since the introduction of 330 * this feature if not properly initialized, especially when 331 * it comes to those bits that enable/disable traps. 332 */ 333 write_el2_ctx_hcx(get_el2_sysregs_ctx(ctx), hcrx_el2, 334 HCRX_EL2_INIT_VAL); 335 } 336 337 if (is_feat_fgt_supported()) { 338 /* 339 * Initialize HFG*_EL2 registers with a default value so legacy 340 * systems unaware of FEAT_FGT do not get trapped due to their lack 341 * of initialization for this feature. 342 */ 343 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgitr_el2, 344 HFGITR_EL2_INIT_VAL); 345 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgrtr_el2, 346 HFGRTR_EL2_INIT_VAL); 347 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgwtr_el2, 348 HFGWTR_EL2_INIT_VAL); 349 } 350 #else 351 /* Initialize EL1 context registers */ 352 setup_el1_context(ctx, ep); 353 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 354 355 manage_extensions_nonsecure(ctx); 356 } 357 358 /******************************************************************************* 359 * The following function performs initialization of the cpu_context 'ctx' 360 * for first use that is common to all security states, and sets the 361 * initial entrypoint state as specified by the entry_point_info structure. 362 * 363 * The EE and ST attributes are used to configure the endianness and secure 364 * timer availability for the new execution context. 365 ******************************************************************************/ 366 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 367 { 368 u_register_t scr_el3; 369 u_register_t mdcr_el3; 370 el3_state_t *state; 371 gp_regs_t *gp_regs; 372 373 state = get_el3state_ctx(ctx); 374 375 /* Clear any residual register values from the context */ 376 zeromem(ctx, sizeof(*ctx)); 377 378 /* 379 * The lower-EL context is zeroed so that no stale values leak to a world. 380 * It is assumed that an all-zero lower-EL context is good enough for it 381 * to boot correctly. However, there are very few registers where this 382 * is not true and some values need to be recreated. 383 */ 384 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 385 el2_sysregs_t *el2_ctx = get_el2_sysregs_ctx(ctx); 386 387 /* 388 * These bits are set in the gicv3 driver. Losing them (especially the 389 * SRE bit) is problematic for all worlds. Henceforth recreate them. 390 */ 391 u_register_t icc_sre_el2_val = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | 392 ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT; 393 write_el2_ctx_common(el2_ctx, icc_sre_el2, icc_sre_el2_val); 394 395 /* 396 * The actlr_el2 register can be initialized in platform's reset handler 397 * and it may contain access control bits (e.g. CLUSTERPMUEN bit). 398 */ 399 write_el2_ctx_common(el2_ctx, actlr_el2, read_actlr_el2()); 400 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 401 402 /* Start with a clean SCR_EL3 copy as all relevant values are set */ 403 scr_el3 = SCR_RESET_VAL; 404 405 /* 406 * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at 407 * EL2, EL1 and EL0 are not trapped to EL3. 408 * 409 * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at 410 * EL2, EL1 and EL0 are not trapped to EL3. 411 * 412 * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from 413 * both Security states and both Execution states. 414 * 415 * SCR_EL3.SIF: Set to one to disable secure instruction execution from 416 * Non-secure memory. 417 */ 418 scr_el3 &= ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT); 419 420 scr_el3 |= SCR_SIF_BIT; 421 422 /* 423 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 424 * Exception level as specified by SPSR. 425 */ 426 if (GET_RW(ep->spsr) == MODE_RW_64) { 427 scr_el3 |= SCR_RW_BIT; 428 } 429 430 /* 431 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 432 * Secure timer registers to EL3, from AArch64 state only, if specified 433 * by the entrypoint attributes. If SEL2 is present and enabled, the ST 434 * bit always behaves as 1 (i.e. secure physical timer register access 435 * is not trapped) 436 */ 437 if (EP_GET_ST(ep->h.attr) != 0U) { 438 scr_el3 |= SCR_ST_BIT; 439 } 440 441 /* 442 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting 443 * SCR_EL3.HXEn. 444 */ 445 if (is_feat_hcx_supported()) { 446 scr_el3 |= SCR_HXEn_BIT; 447 } 448 449 /* 450 * If FEAT_LS64_ACCDATA is enabled, enable access to ACCDATA_EL1 by 451 * setting SCR_EL3.ADEn and allow the ST64BV0 instruction by setting 452 * SCR_EL3.EnAS0. 453 */ 454 if (is_feat_ls64_accdata_supported()) { 455 scr_el3 |= SCR_ADEn_BIT | SCR_EnAS0_BIT; 456 } 457 458 /* 459 * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS 460 * registers are trapped to EL3. 461 */ 462 if (is_feat_rng_trap_supported()) { 463 scr_el3 |= SCR_TRNDR_BIT; 464 } 465 466 #if FAULT_INJECTION_SUPPORT 467 /* Enable fault injection from lower ELs */ 468 scr_el3 |= SCR_FIEN_BIT; 469 #endif 470 471 #if CTX_INCLUDE_PAUTH_REGS 472 /* 473 * Enable Pointer Authentication globally for all the worlds. 474 * 475 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 476 * other than EL3 477 * 478 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 479 * than EL3 480 */ 481 if (is_armv8_3_pauth_present()) { 482 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 483 } 484 #endif /* CTX_INCLUDE_PAUTH_REGS */ 485 486 /* 487 * SCR_EL3.TCR2EN: Enable access to TCR2_ELx for AArch64 if present. 488 */ 489 if (is_feat_tcr2_supported() && (GET_RW(ep->spsr) == MODE_RW_64)) { 490 scr_el3 |= SCR_TCR2EN_BIT; 491 } 492 493 /* 494 * SCR_EL3.PIEN: Enable permission indirection and overlay 495 * registers for AArch64 if present. 496 */ 497 if (is_feat_sxpie_supported() || is_feat_sxpoe_supported()) { 498 scr_el3 |= SCR_PIEN_BIT; 499 } 500 501 /* 502 * SCR_EL3.GCSEn: Enable GCS registers for AArch64 if present. 503 */ 504 if ((is_feat_gcs_supported()) && (GET_RW(ep->spsr) == MODE_RW_64)) { 505 scr_el3 |= SCR_GCSEn_BIT; 506 } 507 508 /* 509 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 510 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 511 * next mode is Hyp. 512 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 513 * same conditions as HVC instructions and when the processor supports 514 * ARMv8.6-FGT. 515 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 516 * CNTPOFF_EL2 register under the same conditions as HVC instructions 517 * and when the processor supports ECV. 518 */ 519 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 520 || ((GET_RW(ep->spsr) != MODE_RW_64) 521 && (GET_M32(ep->spsr) == MODE32_hyp))) { 522 scr_el3 |= SCR_HCE_BIT; 523 524 if (is_feat_fgt_supported()) { 525 scr_el3 |= SCR_FGTEN_BIT; 526 } 527 528 if (is_feat_ecv_supported()) { 529 scr_el3 |= SCR_ECVEN_BIT; 530 } 531 } 532 533 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 534 if (is_feat_twed_supported()) { 535 /* Set delay in SCR_EL3 */ 536 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 537 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK) 538 << SCR_TWEDEL_SHIFT); 539 540 /* Enable WFE delay */ 541 scr_el3 |= SCR_TWEDEn_BIT; 542 } 543 544 #if IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2 545 /* Enable S-EL2 if FEAT_SEL2 is implemented for all the contexts. */ 546 if (is_feat_sel2_supported()) { 547 scr_el3 |= SCR_EEL2_BIT; 548 } 549 #endif /* (IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2) */ 550 551 /* 552 * Populate EL3 state so that we've the right context 553 * before doing ERET 554 */ 555 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 556 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 557 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 558 559 /* Start with a clean MDCR_EL3 copy as all relevant values are set */ 560 mdcr_el3 = MDCR_EL3_RESET_VAL; 561 562 /* --------------------------------------------------------------------- 563 * Initialise MDCR_EL3, setting all fields rather than relying on hw. 564 * Some fields are architecturally UNKNOWN on reset. 565 * 566 * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug. 567 * Debug exceptions, other than Breakpoint Instruction exceptions, are 568 * disabled from all ELs in Secure state. 569 * 570 * MDCR_EL3.SPD32: Set to 0b10 to disable AArch32 Secure self-hosted 571 * privileged debug from S-EL1. 572 * 573 * MDCR_EL3.TDOSA: Set to zero so that EL2 and EL2 System register 574 * access to the powerdown debug registers do not trap to EL3. 575 * 576 * MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the 577 * debug registers, other than those registers that are controlled by 578 * MDCR_EL3.TDOSA. 579 */ 580 mdcr_el3 |= ((MDCR_SDD_BIT | MDCR_SPD32(MDCR_SPD32_DISABLE)) 581 & ~(MDCR_TDA_BIT | MDCR_TDOSA_BIT)) ; 582 write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3); 583 584 #if IMAGE_BL31 585 /* Enable FEAT_TRF for Non-Secure and prohibit for Secure state. */ 586 if (is_feat_trf_supported()) { 587 trf_enable(ctx); 588 } 589 590 pmuv3_enable(ctx); 591 #endif /* IMAGE_BL31 */ 592 593 /* 594 * Store the X0-X7 value from the entrypoint into the context 595 * Use memcpy as we are in control of the layout of the structures 596 */ 597 gp_regs = get_gpregs_ctx(ctx); 598 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 599 } 600 601 /******************************************************************************* 602 * Context management library initialization routine. This library is used by 603 * runtime services to share pointers to 'cpu_context' structures for secure 604 * non-secure and realm states. Management of the structures and their associated 605 * memory is not done by the context management library e.g. the PSCI service 606 * manages the cpu context used for entry from and exit to the non-secure state. 607 * The Secure payload dispatcher service manages the context(s) corresponding to 608 * the secure state. It also uses this library to get access to the non-secure 609 * state cpu context pointers. 610 * Lastly, this library provides the API to make SP_EL3 point to the cpu context 611 * which will be used for programming an entry into a lower EL. The same context 612 * will be used to save state upon exception entry from that EL. 613 ******************************************************************************/ 614 void __init cm_init(void) 615 { 616 /* 617 * The context management library has only global data to initialize, but 618 * that will be done when the BSS is zeroed out. 619 */ 620 } 621 622 /******************************************************************************* 623 * This is the high-level function used to initialize the cpu_context 'ctx' for 624 * first use. It performs initializations that are common to all security states 625 * and initializations specific to the security state specified in 'ep' 626 ******************************************************************************/ 627 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 628 { 629 unsigned int security_state; 630 631 assert(ctx != NULL); 632 633 /* 634 * Perform initializations that are common 635 * to all security states 636 */ 637 setup_context_common(ctx, ep); 638 639 security_state = GET_SECURITY_STATE(ep->h.attr); 640 641 /* Perform security state specific initializations */ 642 switch (security_state) { 643 case SECURE: 644 setup_secure_context(ctx, ep); 645 break; 646 #if ENABLE_RME 647 case REALM: 648 setup_realm_context(ctx, ep); 649 break; 650 #endif 651 case NON_SECURE: 652 setup_ns_context(ctx, ep); 653 break; 654 default: 655 ERROR("Invalid security state\n"); 656 panic(); 657 break; 658 } 659 } 660 661 /******************************************************************************* 662 * Enable architecture extensions for EL3 execution. This function only updates 663 * registers in-place which are expected to either never change or be 664 * overwritten by el3_exit. Expects the core_pos of the current core as argument. 665 ******************************************************************************/ 666 #if IMAGE_BL31 667 void cm_manage_extensions_el3(unsigned int my_idx) 668 { 669 if (is_feat_sve_supported()) { 670 sve_init_el3(); 671 } 672 673 if (is_feat_amu_supported()) { 674 amu_init_el3(my_idx); 675 } 676 677 if (is_feat_sme_supported()) { 678 sme_init_el3(); 679 } 680 681 pmuv3_init_el3(); 682 } 683 #endif /* IMAGE_BL31 */ 684 685 /****************************************************************************** 686 * Function to initialise the registers with the RESET values in the context 687 * memory, which are maintained per world. 688 ******************************************************************************/ 689 #if IMAGE_BL31 690 void cm_el3_arch_init_per_world(per_world_context_t *per_world_ctx) 691 { 692 /* 693 * Initialise CPTR_EL3, setting all fields rather than relying on hw. 694 * 695 * CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers 696 * by Advanced SIMD, floating-point or SVE instructions (if 697 * implemented) do not trap to EL3. 698 * 699 * CPTR_EL3.TCPAC: Set to zero so that accesses to CPACR_EL1, 700 * CPTR_EL2,CPACR, or HCPTR do not trap to EL3. 701 */ 702 uint64_t cptr_el3 = CPTR_EL3_RESET_VAL & ~(TCPAC_BIT | TFP_BIT); 703 704 per_world_ctx->ctx_cptr_el3 = cptr_el3; 705 706 /* 707 * Initialize MPAM3_EL3 to its default reset value 708 * 709 * MPAM3_EL3_RESET_VAL sets the MPAM3_EL3.TRAPLOWER bit that forces 710 * all lower ELn MPAM3_EL3 register access to, trap to EL3 711 */ 712 713 per_world_ctx->ctx_mpam3_el3 = MPAM3_EL3_RESET_VAL; 714 } 715 #endif /* IMAGE_BL31 */ 716 717 /******************************************************************************* 718 * Initialise per_world_context for Non-Secure world. 719 * This function enables the architecture extensions, which have same value 720 * across the cores for the non-secure world. 721 ******************************************************************************/ 722 #if IMAGE_BL31 723 void manage_extensions_nonsecure_per_world(void) 724 { 725 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_NS]); 726 727 if (is_feat_sme_supported()) { 728 sme_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 729 } 730 731 if (is_feat_sve_supported()) { 732 sve_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 733 } 734 735 if (is_feat_amu_supported()) { 736 amu_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 737 } 738 739 if (is_feat_sys_reg_trace_supported()) { 740 sys_reg_trace_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 741 } 742 743 if (is_feat_mpam_supported()) { 744 mpam_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 745 } 746 747 if (is_feat_fpmr_supported()) { 748 fpmr_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 749 } 750 } 751 #endif /* IMAGE_BL31 */ 752 753 /******************************************************************************* 754 * Initialise per_world_context for Secure world. 755 * This function enables the architecture extensions, which have same value 756 * across the cores for the secure world. 757 ******************************************************************************/ 758 static void manage_extensions_secure_per_world(void) 759 { 760 #if IMAGE_BL31 761 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 762 763 if (is_feat_sme_supported()) { 764 765 if (ENABLE_SME_FOR_SWD) { 766 /* 767 * Enable SME, SVE, FPU/SIMD in secure context, SPM must ensure 768 * SME, SVE, and FPU/SIMD context properly managed. 769 */ 770 sme_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 771 } else { 772 /* 773 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 774 * world can safely use the associated registers. 775 */ 776 sme_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 777 } 778 } 779 if (is_feat_sve_supported()) { 780 if (ENABLE_SVE_FOR_SWD) { 781 /* 782 * Enable SVE and FPU in secure context, SPM must ensure 783 * that the SVE and FPU register contexts are properly managed. 784 */ 785 sve_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 786 } else { 787 /* 788 * Disable SVE and FPU in secure context so non-secure world 789 * can safely use them. 790 */ 791 sve_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 792 } 793 } 794 795 /* NS can access this but Secure shouldn't */ 796 if (is_feat_sys_reg_trace_supported()) { 797 sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 798 } 799 800 has_secure_perworld_init = true; 801 #endif /* IMAGE_BL31 */ 802 } 803 804 /******************************************************************************* 805 * Enable architecture extensions on first entry to Non-secure world. 806 ******************************************************************************/ 807 static void manage_extensions_nonsecure(cpu_context_t *ctx) 808 { 809 #if IMAGE_BL31 810 /* NOTE: registers are not context switched */ 811 if (is_feat_amu_supported()) { 812 amu_enable(ctx); 813 } 814 815 if (is_feat_sme_supported()) { 816 sme_enable(ctx); 817 } 818 819 if (is_feat_fgt2_supported()) { 820 fgt2_enable(ctx); 821 } 822 823 if (is_feat_debugv8p9_supported()) { 824 debugv8p9_extended_bp_wp_enable(ctx); 825 } 826 827 /* 828 * SPE, TRBE, and BRBE have multi-field enables that affect which world 829 * they apply to. Despite this, it is useful to ignore these for 830 * simplicity in determining the feature's per world enablement status. 831 * This is only possible when context is written per-world. Relied on 832 * by SMCCC_ARCH_FEATURE_AVAILABILITY 833 */ 834 if (is_feat_spe_supported()) { 835 spe_enable(ctx); 836 } 837 838 if (is_feat_trbe_supported()) { 839 trbe_enable(ctx); 840 } 841 842 if (is_feat_brbe_supported()) { 843 brbe_enable(ctx); 844 } 845 #endif /* IMAGE_BL31 */ 846 } 847 848 /* TODO: move to lib/extensions/pauth when it has been ported to FEAT_STATE */ 849 static __unused void enable_pauth_el2(void) 850 { 851 u_register_t hcr_el2 = read_hcr_el2(); 852 /* 853 * For Armv8.3 pointer authentication feature, disable traps to EL2 when 854 * accessing key registers or using pointer authentication instructions 855 * from lower ELs. 856 */ 857 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 858 859 write_hcr_el2(hcr_el2); 860 } 861 862 #if INIT_UNUSED_NS_EL2 863 /******************************************************************************* 864 * Enable architecture extensions in-place at EL2 on first entry to Non-secure 865 * world when EL2 is empty and unused. 866 ******************************************************************************/ 867 static void manage_extensions_nonsecure_el2_unused(void) 868 { 869 #if IMAGE_BL31 870 if (is_feat_spe_supported()) { 871 spe_init_el2_unused(); 872 } 873 874 if (is_feat_amu_supported()) { 875 amu_init_el2_unused(); 876 } 877 878 if (is_feat_mpam_supported()) { 879 mpam_init_el2_unused(); 880 } 881 882 if (is_feat_trbe_supported()) { 883 trbe_init_el2_unused(); 884 } 885 886 if (is_feat_sys_reg_trace_supported()) { 887 sys_reg_trace_init_el2_unused(); 888 } 889 890 if (is_feat_trf_supported()) { 891 trf_init_el2_unused(); 892 } 893 894 pmuv3_init_el2_unused(); 895 896 if (is_feat_sve_supported()) { 897 sve_init_el2_unused(); 898 } 899 900 if (is_feat_sme_supported()) { 901 sme_init_el2_unused(); 902 } 903 904 if (is_feat_mops_supported()) { 905 write_hcrx_el2(read_hcrx_el2() | HCRX_EL2_MSCEn_BIT); 906 } 907 908 #if ENABLE_PAUTH 909 enable_pauth_el2(); 910 #endif /* ENABLE_PAUTH */ 911 #endif /* IMAGE_BL31 */ 912 } 913 #endif /* INIT_UNUSED_NS_EL2 */ 914 915 /******************************************************************************* 916 * Enable architecture extensions on first entry to Secure world. 917 ******************************************************************************/ 918 static void manage_extensions_secure(cpu_context_t *ctx) 919 { 920 #if IMAGE_BL31 921 if (is_feat_sme_supported()) { 922 if (ENABLE_SME_FOR_SWD) { 923 /* 924 * Enable SME, SVE, FPU/SIMD in secure context, secure manager 925 * must ensure SME, SVE, and FPU/SIMD context properly managed. 926 */ 927 sme_init_el3(); 928 sme_enable(ctx); 929 } else { 930 /* 931 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 932 * world can safely use the associated registers. 933 */ 934 sme_disable(ctx); 935 } 936 } 937 938 /* 939 * SPE and TRBE cannot be fully disabled from EL3 registers alone, only 940 * sysreg access can. In case the EL1 controls leave them active on 941 * context switch, we want the owning security state to be NS so Secure 942 * can't be DOSed. 943 */ 944 if (is_feat_spe_supported()) { 945 spe_disable(ctx); 946 } 947 948 if (is_feat_trbe_supported()) { 949 trbe_disable(ctx); 950 } 951 #endif /* IMAGE_BL31 */ 952 } 953 954 #if !IMAGE_BL1 955 /******************************************************************************* 956 * The following function initializes the cpu_context for a CPU specified by 957 * its `cpu_idx` for first use, and sets the initial entrypoint state as 958 * specified by the entry_point_info structure. 959 ******************************************************************************/ 960 void cm_init_context_by_index(unsigned int cpu_idx, 961 const entry_point_info_t *ep) 962 { 963 cpu_context_t *ctx; 964 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 965 cm_setup_context(ctx, ep); 966 } 967 #endif /* !IMAGE_BL1 */ 968 969 /******************************************************************************* 970 * The following function initializes the cpu_context for the current CPU 971 * for first use, and sets the initial entrypoint state as specified by the 972 * entry_point_info structure. 973 ******************************************************************************/ 974 void cm_init_my_context(const entry_point_info_t *ep) 975 { 976 cpu_context_t *ctx; 977 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 978 cm_setup_context(ctx, ep); 979 } 980 981 /* EL2 present but unused, need to disable safely. SCTLR_EL2 can be ignored */ 982 static void init_nonsecure_el2_unused(cpu_context_t *ctx) 983 { 984 #if INIT_UNUSED_NS_EL2 985 u_register_t hcr_el2 = HCR_RESET_VAL; 986 u_register_t mdcr_el2; 987 u_register_t scr_el3; 988 989 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 990 991 /* Set EL2 register width: Set HCR_EL2.RW to match SCR_EL3.RW */ 992 if ((scr_el3 & SCR_RW_BIT) != 0U) { 993 hcr_el2 |= HCR_RW_BIT; 994 } 995 996 write_hcr_el2(hcr_el2); 997 998 /* 999 * Initialise CPTR_EL2 setting all fields rather than relying on the hw. 1000 * All fields have architecturally UNKNOWN reset values. 1001 */ 1002 write_cptr_el2(CPTR_EL2_RESET_VAL); 1003 1004 /* 1005 * Initialise CNTHCTL_EL2. All fields are architecturally UNKNOWN on 1006 * reset and are set to zero except for field(s) listed below. 1007 * 1008 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to Hyp mode of 1009 * Non-secure EL0 and EL1 accesses to the physical timer registers. 1010 * 1011 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to Hyp mode of 1012 * Non-secure EL0 and EL1 accesses to the physical counter registers. 1013 */ 1014 write_cnthctl_el2(CNTHCTL_RESET_VAL | EL1PCEN_BIT | EL1PCTEN_BIT); 1015 1016 /* 1017 * Initialise CNTVOFF_EL2 to zero as it resets to an architecturally 1018 * UNKNOWN value. 1019 */ 1020 write_cntvoff_el2(0); 1021 1022 /* 1023 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and MPIDR_EL1 1024 * respectively. 1025 */ 1026 write_vpidr_el2(read_midr_el1()); 1027 write_vmpidr_el2(read_mpidr_el1()); 1028 1029 /* 1030 * Initialise VTTBR_EL2. All fields are architecturally UNKNOWN on reset. 1031 * 1032 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 2 address 1033 * translation is disabled, cache maintenance operations depend on the 1034 * VMID. 1035 * 1036 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address translation is 1037 * disabled. 1038 */ 1039 write_vttbr_el2(VTTBR_RESET_VAL & 1040 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) | 1041 (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 1042 1043 /* 1044 * Initialise MDCR_EL2, setting all fields rather than relying on hw. 1045 * Some fields are architecturally UNKNOWN on reset. 1046 * 1047 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and EL1 System 1048 * register accesses to the Debug ROM registers are not trapped to EL2. 1049 * 1050 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 System register 1051 * accesses to the powerdown debug registers are not trapped to EL2. 1052 * 1053 * MDCR_EL2.TDA: Set to zero so that System register accesses to the 1054 * debug registers do not trap to EL2. 1055 * 1056 * MDCR_EL2.TDE: Set to zero so that debug exceptions are not routed to 1057 * EL2. 1058 */ 1059 mdcr_el2 = MDCR_EL2_RESET_VAL & 1060 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | MDCR_EL2_TDA_BIT | 1061 MDCR_EL2_TDE_BIT); 1062 1063 write_mdcr_el2(mdcr_el2); 1064 1065 /* 1066 * Initialise HSTR_EL2. All fields are architecturally UNKNOWN on reset. 1067 * 1068 * HSTR_EL2.T<n>: Set all these fields to zero so that Non-secure EL0 or 1069 * EL1 accesses to System registers do not trap to EL2. 1070 */ 1071 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 1072 1073 /* 1074 * Initialise CNTHP_CTL_EL2. All fields are architecturally UNKNOWN on 1075 * reset. 1076 * 1077 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 physical timer 1078 * and prevent timer interrupts. 1079 */ 1080 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & ~(CNTHP_CTL_ENABLE_BIT)); 1081 1082 manage_extensions_nonsecure_el2_unused(); 1083 #endif /* INIT_UNUSED_NS_EL2 */ 1084 } 1085 1086 /******************************************************************************* 1087 * Prepare the CPU system registers for first entry into realm, secure, or 1088 * normal world. 1089 * 1090 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 1091 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 1092 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 1093 * For all entries, the EL1 registers are initialized from the cpu_context 1094 ******************************************************************************/ 1095 void cm_prepare_el3_exit(uint32_t security_state) 1096 { 1097 u_register_t sctlr_el2, scr_el3; 1098 cpu_context_t *ctx = cm_get_context(security_state); 1099 1100 assert(ctx != NULL); 1101 1102 if (security_state == NON_SECURE) { 1103 uint64_t el2_implemented = el_implemented(2); 1104 1105 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 1106 CTX_SCR_EL3); 1107 1108 if (el2_implemented != EL_IMPL_NONE) { 1109 1110 /* 1111 * If context is not being used for EL2, initialize 1112 * HCRX_EL2 with its init value here. 1113 */ 1114 if (is_feat_hcx_supported()) { 1115 write_hcrx_el2(HCRX_EL2_INIT_VAL); 1116 } 1117 1118 /* 1119 * Initialize Fine-grained trap registers introduced 1120 * by FEAT_FGT so all traps are initially disabled when 1121 * switching to EL2 or a lower EL, preventing undesired 1122 * behavior. 1123 */ 1124 if (is_feat_fgt_supported()) { 1125 /* 1126 * Initialize HFG*_EL2 registers with a default 1127 * value so legacy systems unaware of FEAT_FGT 1128 * do not get trapped due to their lack of 1129 * initialization for this feature. 1130 */ 1131 write_hfgitr_el2(HFGITR_EL2_INIT_VAL); 1132 write_hfgrtr_el2(HFGRTR_EL2_INIT_VAL); 1133 write_hfgwtr_el2(HFGWTR_EL2_INIT_VAL); 1134 } 1135 1136 /* Condition to ensure EL2 is being used. */ 1137 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 1138 /* Initialize SCTLR_EL2 register with reset value. */ 1139 sctlr_el2 = SCTLR_EL2_RES1; 1140 1141 /* 1142 * If workaround of errata 764081 for Cortex-A75 1143 * is used then set SCTLR_EL2.IESB to enable 1144 * Implicit Error Synchronization Barrier. 1145 */ 1146 if (errata_a75_764081_applies()) { 1147 sctlr_el2 |= SCTLR_IESB_BIT; 1148 } 1149 1150 write_sctlr_el2(sctlr_el2); 1151 } else { 1152 /* 1153 * (scr_el3 & SCR_HCE_BIT==0) 1154 * EL2 implemented but unused. 1155 */ 1156 init_nonsecure_el2_unused(ctx); 1157 } 1158 } 1159 } 1160 #if (!CTX_INCLUDE_EL2_REGS) 1161 /* Restore EL1 system registers, only when CTX_INCLUDE_EL2_REGS=0 */ 1162 cm_el1_sysregs_context_restore(security_state); 1163 #endif 1164 cm_set_next_eret_context(security_state); 1165 } 1166 1167 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 1168 1169 static void el2_sysregs_context_save_fgt(el2_sysregs_t *ctx) 1170 { 1171 write_el2_ctx_fgt(ctx, hdfgrtr_el2, read_hdfgrtr_el2()); 1172 if (is_feat_amu_supported()) { 1173 write_el2_ctx_fgt(ctx, hafgrtr_el2, read_hafgrtr_el2()); 1174 } 1175 write_el2_ctx_fgt(ctx, hdfgwtr_el2, read_hdfgwtr_el2()); 1176 write_el2_ctx_fgt(ctx, hfgitr_el2, read_hfgitr_el2()); 1177 write_el2_ctx_fgt(ctx, hfgrtr_el2, read_hfgrtr_el2()); 1178 write_el2_ctx_fgt(ctx, hfgwtr_el2, read_hfgwtr_el2()); 1179 } 1180 1181 static void el2_sysregs_context_restore_fgt(el2_sysregs_t *ctx) 1182 { 1183 write_hdfgrtr_el2(read_el2_ctx_fgt(ctx, hdfgrtr_el2)); 1184 if (is_feat_amu_supported()) { 1185 write_hafgrtr_el2(read_el2_ctx_fgt(ctx, hafgrtr_el2)); 1186 } 1187 write_hdfgwtr_el2(read_el2_ctx_fgt(ctx, hdfgwtr_el2)); 1188 write_hfgitr_el2(read_el2_ctx_fgt(ctx, hfgitr_el2)); 1189 write_hfgrtr_el2(read_el2_ctx_fgt(ctx, hfgrtr_el2)); 1190 write_hfgwtr_el2(read_el2_ctx_fgt(ctx, hfgwtr_el2)); 1191 } 1192 1193 static void el2_sysregs_context_save_fgt2(el2_sysregs_t *ctx) 1194 { 1195 write_el2_ctx_fgt2(ctx, hdfgrtr2_el2, read_hdfgrtr2_el2()); 1196 write_el2_ctx_fgt2(ctx, hdfgwtr2_el2, read_hdfgwtr2_el2()); 1197 write_el2_ctx_fgt2(ctx, hfgitr2_el2, read_hfgitr2_el2()); 1198 write_el2_ctx_fgt2(ctx, hfgrtr2_el2, read_hfgrtr2_el2()); 1199 write_el2_ctx_fgt2(ctx, hfgwtr2_el2, read_hfgwtr2_el2()); 1200 } 1201 1202 static void el2_sysregs_context_restore_fgt2(el2_sysregs_t *ctx) 1203 { 1204 write_hdfgrtr2_el2(read_el2_ctx_fgt2(ctx, hdfgrtr2_el2)); 1205 write_hdfgwtr2_el2(read_el2_ctx_fgt2(ctx, hdfgwtr2_el2)); 1206 write_hfgitr2_el2(read_el2_ctx_fgt2(ctx, hfgitr2_el2)); 1207 write_hfgrtr2_el2(read_el2_ctx_fgt2(ctx, hfgrtr2_el2)); 1208 write_hfgwtr2_el2(read_el2_ctx_fgt2(ctx, hfgwtr2_el2)); 1209 } 1210 1211 static void el2_sysregs_context_save_mpam(el2_sysregs_t *ctx) 1212 { 1213 u_register_t mpam_idr = read_mpamidr_el1(); 1214 1215 write_el2_ctx_mpam(ctx, mpam2_el2, read_mpam2_el2()); 1216 1217 /* 1218 * The context registers that we intend to save would be part of the 1219 * PE's system register frame only if MPAMIDR_EL1.HAS_HCR == 1. 1220 */ 1221 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1222 return; 1223 } 1224 1225 /* 1226 * MPAMHCR_EL2, MPAMVPMV_EL2 and MPAMVPM0_EL2 are always present if 1227 * MPAMIDR_HAS_HCR_BIT == 1. 1228 */ 1229 write_el2_ctx_mpam(ctx, mpamhcr_el2, read_mpamhcr_el2()); 1230 write_el2_ctx_mpam(ctx, mpamvpm0_el2, read_mpamvpm0_el2()); 1231 write_el2_ctx_mpam(ctx, mpamvpmv_el2, read_mpamvpmv_el2()); 1232 1233 /* 1234 * The number of MPAMVPM registers is implementation defined, their 1235 * number is stored in the MPAMIDR_EL1 register. 1236 */ 1237 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1238 case 7: 1239 write_el2_ctx_mpam(ctx, mpamvpm7_el2, read_mpamvpm7_el2()); 1240 __fallthrough; 1241 case 6: 1242 write_el2_ctx_mpam(ctx, mpamvpm6_el2, read_mpamvpm6_el2()); 1243 __fallthrough; 1244 case 5: 1245 write_el2_ctx_mpam(ctx, mpamvpm5_el2, read_mpamvpm5_el2()); 1246 __fallthrough; 1247 case 4: 1248 write_el2_ctx_mpam(ctx, mpamvpm4_el2, read_mpamvpm4_el2()); 1249 __fallthrough; 1250 case 3: 1251 write_el2_ctx_mpam(ctx, mpamvpm3_el2, read_mpamvpm3_el2()); 1252 __fallthrough; 1253 case 2: 1254 write_el2_ctx_mpam(ctx, mpamvpm2_el2, read_mpamvpm2_el2()); 1255 __fallthrough; 1256 case 1: 1257 write_el2_ctx_mpam(ctx, mpamvpm1_el2, read_mpamvpm1_el2()); 1258 break; 1259 } 1260 } 1261 1262 static void el2_sysregs_context_restore_mpam(el2_sysregs_t *ctx) 1263 { 1264 u_register_t mpam_idr = read_mpamidr_el1(); 1265 1266 write_mpam2_el2(read_el2_ctx_mpam(ctx, mpam2_el2)); 1267 1268 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1269 return; 1270 } 1271 1272 write_mpamhcr_el2(read_el2_ctx_mpam(ctx, mpamhcr_el2)); 1273 write_mpamvpm0_el2(read_el2_ctx_mpam(ctx, mpamvpm0_el2)); 1274 write_mpamvpmv_el2(read_el2_ctx_mpam(ctx, mpamvpmv_el2)); 1275 1276 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1277 case 7: 1278 write_mpamvpm7_el2(read_el2_ctx_mpam(ctx, mpamvpm7_el2)); 1279 __fallthrough; 1280 case 6: 1281 write_mpamvpm6_el2(read_el2_ctx_mpam(ctx, mpamvpm6_el2)); 1282 __fallthrough; 1283 case 5: 1284 write_mpamvpm5_el2(read_el2_ctx_mpam(ctx, mpamvpm5_el2)); 1285 __fallthrough; 1286 case 4: 1287 write_mpamvpm4_el2(read_el2_ctx_mpam(ctx, mpamvpm4_el2)); 1288 __fallthrough; 1289 case 3: 1290 write_mpamvpm3_el2(read_el2_ctx_mpam(ctx, mpamvpm3_el2)); 1291 __fallthrough; 1292 case 2: 1293 write_mpamvpm2_el2(read_el2_ctx_mpam(ctx, mpamvpm2_el2)); 1294 __fallthrough; 1295 case 1: 1296 write_mpamvpm1_el2(read_el2_ctx_mpam(ctx, mpamvpm1_el2)); 1297 break; 1298 } 1299 } 1300 1301 /* --------------------------------------------------------------------------- 1302 * The following registers are not added: 1303 * ICH_AP0R<n>_EL2 1304 * ICH_AP1R<n>_EL2 1305 * ICH_LR<n>_EL2 1306 * 1307 * NOTE: For a system with S-EL2 present but not enabled, accessing 1308 * ICC_SRE_EL2 is undefined from EL3. To workaround this change the 1309 * SCR_EL3.NS = 1 before accessing this register. 1310 * --------------------------------------------------------------------------- 1311 */ 1312 static void el2_sysregs_context_save_gic(el2_sysregs_t *ctx, uint32_t security_state) 1313 { 1314 u_register_t scr_el3 = read_scr_el3(); 1315 1316 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1317 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1318 #else 1319 write_scr_el3(scr_el3 | SCR_NS_BIT); 1320 isb(); 1321 1322 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1323 1324 write_scr_el3(scr_el3); 1325 isb(); 1326 #endif 1327 write_el2_ctx_common(ctx, ich_hcr_el2, read_ich_hcr_el2()); 1328 1329 if (errata_ich_vmcr_el2_applies()) { 1330 if (security_state == SECURE) { 1331 write_scr_el3(scr_el3 & ~SCR_NS_BIT); 1332 } else { 1333 write_scr_el3(scr_el3 | SCR_NS_BIT); 1334 } 1335 isb(); 1336 } 1337 1338 write_el2_ctx_common(ctx, ich_vmcr_el2, read_ich_vmcr_el2()); 1339 1340 if (errata_ich_vmcr_el2_applies()) { 1341 write_scr_el3(scr_el3); 1342 isb(); 1343 } 1344 } 1345 1346 static void el2_sysregs_context_restore_gic(el2_sysregs_t *ctx, uint32_t security_state) 1347 { 1348 u_register_t scr_el3 = read_scr_el3(); 1349 1350 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1351 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1352 #else 1353 write_scr_el3(scr_el3 | SCR_NS_BIT); 1354 isb(); 1355 1356 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1357 1358 write_scr_el3(scr_el3); 1359 isb(); 1360 #endif 1361 write_ich_hcr_el2(read_el2_ctx_common(ctx, ich_hcr_el2)); 1362 1363 if (errata_ich_vmcr_el2_applies()) { 1364 if (security_state == SECURE) { 1365 write_scr_el3(scr_el3 & ~SCR_NS_BIT); 1366 } else { 1367 write_scr_el3(scr_el3 | SCR_NS_BIT); 1368 } 1369 isb(); 1370 } 1371 1372 write_ich_vmcr_el2(read_el2_ctx_common(ctx, ich_vmcr_el2)); 1373 1374 if (errata_ich_vmcr_el2_applies()) { 1375 write_scr_el3(scr_el3); 1376 isb(); 1377 } 1378 } 1379 1380 /* ----------------------------------------------------- 1381 * The following registers are not added: 1382 * AMEVCNTVOFF0<n>_EL2 1383 * AMEVCNTVOFF1<n>_EL2 1384 * ----------------------------------------------------- 1385 */ 1386 static void el2_sysregs_context_save_common(el2_sysregs_t *ctx) 1387 { 1388 write_el2_ctx_common(ctx, actlr_el2, read_actlr_el2()); 1389 write_el2_ctx_common(ctx, afsr0_el2, read_afsr0_el2()); 1390 write_el2_ctx_common(ctx, afsr1_el2, read_afsr1_el2()); 1391 write_el2_ctx_common(ctx, amair_el2, read_amair_el2()); 1392 write_el2_ctx_common(ctx, cnthctl_el2, read_cnthctl_el2()); 1393 write_el2_ctx_common(ctx, cntvoff_el2, read_cntvoff_el2()); 1394 write_el2_ctx_common(ctx, cptr_el2, read_cptr_el2()); 1395 if (CTX_INCLUDE_AARCH32_REGS) { 1396 write_el2_ctx_common(ctx, dbgvcr32_el2, read_dbgvcr32_el2()); 1397 } 1398 write_el2_ctx_common(ctx, elr_el2, read_elr_el2()); 1399 write_el2_ctx_common(ctx, esr_el2, read_esr_el2()); 1400 write_el2_ctx_common(ctx, far_el2, read_far_el2()); 1401 write_el2_ctx_common(ctx, hacr_el2, read_hacr_el2()); 1402 write_el2_ctx_common(ctx, hcr_el2, read_hcr_el2()); 1403 write_el2_ctx_common(ctx, hpfar_el2, read_hpfar_el2()); 1404 write_el2_ctx_common(ctx, hstr_el2, read_hstr_el2()); 1405 write_el2_ctx_common(ctx, mair_el2, read_mair_el2()); 1406 write_el2_ctx_common(ctx, mdcr_el2, read_mdcr_el2()); 1407 write_el2_ctx_common(ctx, sctlr_el2, read_sctlr_el2()); 1408 write_el2_ctx_common(ctx, spsr_el2, read_spsr_el2()); 1409 write_el2_ctx_common(ctx, sp_el2, read_sp_el2()); 1410 write_el2_ctx_common(ctx, tcr_el2, read_tcr_el2()); 1411 write_el2_ctx_common(ctx, tpidr_el2, read_tpidr_el2()); 1412 write_el2_ctx_common(ctx, vbar_el2, read_vbar_el2()); 1413 write_el2_ctx_common(ctx, vmpidr_el2, read_vmpidr_el2()); 1414 write_el2_ctx_common(ctx, vpidr_el2, read_vpidr_el2()); 1415 write_el2_ctx_common(ctx, vtcr_el2, read_vtcr_el2()); 1416 1417 write_el2_ctx_common_sysreg128(ctx, ttbr0_el2, read_ttbr0_el2()); 1418 write_el2_ctx_common_sysreg128(ctx, vttbr_el2, read_vttbr_el2()); 1419 } 1420 1421 static void el2_sysregs_context_restore_common(el2_sysregs_t *ctx) 1422 { 1423 write_actlr_el2(read_el2_ctx_common(ctx, actlr_el2)); 1424 write_afsr0_el2(read_el2_ctx_common(ctx, afsr0_el2)); 1425 write_afsr1_el2(read_el2_ctx_common(ctx, afsr1_el2)); 1426 write_amair_el2(read_el2_ctx_common(ctx, amair_el2)); 1427 write_cnthctl_el2(read_el2_ctx_common(ctx, cnthctl_el2)); 1428 write_cntvoff_el2(read_el2_ctx_common(ctx, cntvoff_el2)); 1429 write_cptr_el2(read_el2_ctx_common(ctx, cptr_el2)); 1430 if (CTX_INCLUDE_AARCH32_REGS) { 1431 write_dbgvcr32_el2(read_el2_ctx_common(ctx, dbgvcr32_el2)); 1432 } 1433 write_elr_el2(read_el2_ctx_common(ctx, elr_el2)); 1434 write_esr_el2(read_el2_ctx_common(ctx, esr_el2)); 1435 write_far_el2(read_el2_ctx_common(ctx, far_el2)); 1436 write_hacr_el2(read_el2_ctx_common(ctx, hacr_el2)); 1437 write_hcr_el2(read_el2_ctx_common(ctx, hcr_el2)); 1438 write_hpfar_el2(read_el2_ctx_common(ctx, hpfar_el2)); 1439 write_hstr_el2(read_el2_ctx_common(ctx, hstr_el2)); 1440 write_mair_el2(read_el2_ctx_common(ctx, mair_el2)); 1441 write_mdcr_el2(read_el2_ctx_common(ctx, mdcr_el2)); 1442 write_sctlr_el2(read_el2_ctx_common(ctx, sctlr_el2)); 1443 write_spsr_el2(read_el2_ctx_common(ctx, spsr_el2)); 1444 write_sp_el2(read_el2_ctx_common(ctx, sp_el2)); 1445 write_tcr_el2(read_el2_ctx_common(ctx, tcr_el2)); 1446 write_tpidr_el2(read_el2_ctx_common(ctx, tpidr_el2)); 1447 write_ttbr0_el2(read_el2_ctx_common(ctx, ttbr0_el2)); 1448 write_vbar_el2(read_el2_ctx_common(ctx, vbar_el2)); 1449 write_vmpidr_el2(read_el2_ctx_common(ctx, vmpidr_el2)); 1450 write_vpidr_el2(read_el2_ctx_common(ctx, vpidr_el2)); 1451 write_vtcr_el2(read_el2_ctx_common(ctx, vtcr_el2)); 1452 write_vttbr_el2(read_el2_ctx_common(ctx, vttbr_el2)); 1453 } 1454 1455 /******************************************************************************* 1456 * Save EL2 sysreg context 1457 ******************************************************************************/ 1458 void cm_el2_sysregs_context_save(uint32_t security_state) 1459 { 1460 cpu_context_t *ctx; 1461 el2_sysregs_t *el2_sysregs_ctx; 1462 1463 ctx = cm_get_context(security_state); 1464 assert(ctx != NULL); 1465 1466 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1467 1468 el2_sysregs_context_save_common(el2_sysregs_ctx); 1469 el2_sysregs_context_save_gic(el2_sysregs_ctx, security_state); 1470 1471 if (is_feat_mte2_supported()) { 1472 write_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2, read_tfsr_el2()); 1473 } 1474 1475 if (is_feat_mpam_supported()) { 1476 el2_sysregs_context_save_mpam(el2_sysregs_ctx); 1477 } 1478 1479 if (is_feat_fgt_supported()) { 1480 el2_sysregs_context_save_fgt(el2_sysregs_ctx); 1481 } 1482 1483 if (is_feat_fgt2_supported()) { 1484 el2_sysregs_context_save_fgt2(el2_sysregs_ctx); 1485 } 1486 1487 if (is_feat_ecv_v2_supported()) { 1488 write_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2, read_cntpoff_el2()); 1489 } 1490 1491 if (is_feat_vhe_supported()) { 1492 write_el2_ctx_vhe(el2_sysregs_ctx, contextidr_el2, 1493 read_contextidr_el2()); 1494 write_el2_ctx_vhe_sysreg128(el2_sysregs_ctx, ttbr1_el2, read_ttbr1_el2()); 1495 } 1496 1497 if (is_feat_ras_supported()) { 1498 write_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2, read_vdisr_el2()); 1499 write_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2, read_vsesr_el2()); 1500 } 1501 1502 if (is_feat_nv2_supported()) { 1503 write_el2_ctx_neve(el2_sysregs_ctx, vncr_el2, read_vncr_el2()); 1504 } 1505 1506 if (is_feat_trf_supported()) { 1507 write_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2, read_trfcr_el2()); 1508 } 1509 1510 if (is_feat_csv2_2_supported()) { 1511 write_el2_ctx_csv2_2(el2_sysregs_ctx, scxtnum_el2, 1512 read_scxtnum_el2()); 1513 } 1514 1515 if (is_feat_hcx_supported()) { 1516 write_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2, read_hcrx_el2()); 1517 } 1518 1519 if (is_feat_tcr2_supported()) { 1520 write_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2, read_tcr2_el2()); 1521 } 1522 1523 if (is_feat_sxpie_supported()) { 1524 write_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2, read_pire0_el2()); 1525 write_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2, read_pir_el2()); 1526 } 1527 1528 if (is_feat_sxpoe_supported()) { 1529 write_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2, read_por_el2()); 1530 } 1531 1532 if (is_feat_brbe_supported()) { 1533 write_el2_ctx_brbe(el2_sysregs_ctx, brbcr_el2, read_brbcr_el2()); 1534 } 1535 1536 if (is_feat_s2pie_supported()) { 1537 write_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2, read_s2pir_el2()); 1538 } 1539 1540 if (is_feat_gcs_supported()) { 1541 write_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2, read_gcscr_el2()); 1542 write_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2, read_gcspr_el2()); 1543 } 1544 1545 if (is_feat_sctlr2_supported()) { 1546 write_el2_ctx_sctlr2(el2_sysregs_ctx, sctlr2_el2, read_sctlr2_el2()); 1547 } 1548 } 1549 1550 /******************************************************************************* 1551 * Restore EL2 sysreg context 1552 ******************************************************************************/ 1553 void cm_el2_sysregs_context_restore(uint32_t security_state) 1554 { 1555 cpu_context_t *ctx; 1556 el2_sysregs_t *el2_sysregs_ctx; 1557 1558 ctx = cm_get_context(security_state); 1559 assert(ctx != NULL); 1560 1561 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1562 1563 el2_sysregs_context_restore_common(el2_sysregs_ctx); 1564 el2_sysregs_context_restore_gic(el2_sysregs_ctx, security_state); 1565 1566 if (is_feat_mte2_supported()) { 1567 write_tfsr_el2(read_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2)); 1568 } 1569 1570 if (is_feat_mpam_supported()) { 1571 el2_sysregs_context_restore_mpam(el2_sysregs_ctx); 1572 } 1573 1574 if (is_feat_fgt_supported()) { 1575 el2_sysregs_context_restore_fgt(el2_sysregs_ctx); 1576 } 1577 1578 if (is_feat_fgt2_supported()) { 1579 el2_sysregs_context_restore_fgt2(el2_sysregs_ctx); 1580 } 1581 1582 if (is_feat_ecv_v2_supported()) { 1583 write_cntpoff_el2(read_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2)); 1584 } 1585 1586 if (is_feat_vhe_supported()) { 1587 write_contextidr_el2(read_el2_ctx_vhe(el2_sysregs_ctx, 1588 contextidr_el2)); 1589 write_ttbr1_el2(read_el2_ctx_vhe(el2_sysregs_ctx, ttbr1_el2)); 1590 } 1591 1592 if (is_feat_ras_supported()) { 1593 write_vdisr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2)); 1594 write_vsesr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2)); 1595 } 1596 1597 if (is_feat_nv2_supported()) { 1598 write_vncr_el2(read_el2_ctx_neve(el2_sysregs_ctx, vncr_el2)); 1599 } 1600 1601 if (is_feat_trf_supported()) { 1602 write_trfcr_el2(read_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2)); 1603 } 1604 1605 if (is_feat_csv2_2_supported()) { 1606 write_scxtnum_el2(read_el2_ctx_csv2_2(el2_sysregs_ctx, 1607 scxtnum_el2)); 1608 } 1609 1610 if (is_feat_hcx_supported()) { 1611 write_hcrx_el2(read_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2)); 1612 } 1613 1614 if (is_feat_tcr2_supported()) { 1615 write_tcr2_el2(read_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2)); 1616 } 1617 1618 if (is_feat_sxpie_supported()) { 1619 write_pire0_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2)); 1620 write_pir_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2)); 1621 } 1622 1623 if (is_feat_sxpoe_supported()) { 1624 write_por_el2(read_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2)); 1625 } 1626 1627 if (is_feat_s2pie_supported()) { 1628 write_s2pir_el2(read_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2)); 1629 } 1630 1631 if (is_feat_gcs_supported()) { 1632 write_gcscr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2)); 1633 write_gcspr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2)); 1634 } 1635 1636 if (is_feat_sctlr2_supported()) { 1637 write_sctlr2_el2(read_el2_ctx_sctlr2(el2_sysregs_ctx, sctlr2_el2)); 1638 } 1639 1640 if (is_feat_brbe_supported()) { 1641 write_brbcr_el2(read_el2_ctx_brbe(el2_sysregs_ctx, brbcr_el2)); 1642 } 1643 } 1644 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 1645 1646 #if IMAGE_BL31 1647 /********************************************************************************* 1648 * This function allows Architecture features asymmetry among cores. 1649 * TF-A assumes that all the cores in the platform has architecture feature parity 1650 * and hence the context is setup on different core (e.g. primary sets up the 1651 * context for secondary cores).This assumption may not be true for systems where 1652 * cores are not conforming to same Arch version or there is CPU Erratum which 1653 * requires certain feature to be be disabled only on a given core. 1654 * 1655 * This function is called on secondary cores to override any disparity in context 1656 * setup by primary, this would be called during warmboot path. 1657 *********************************************************************************/ 1658 void cm_handle_asymmetric_features(void) 1659 { 1660 cpu_context_t *ctx __maybe_unused = cm_get_context(NON_SECURE); 1661 1662 assert(ctx != NULL); 1663 1664 #if ENABLE_SPE_FOR_NS == FEAT_STATE_CHECK_ASYMMETRIC 1665 if (is_feat_spe_supported()) { 1666 spe_enable(ctx); 1667 } else { 1668 spe_disable(ctx); 1669 } 1670 #endif 1671 1672 #if ERRATA_A520_2938996 || ERRATA_X4_2726228 1673 if (check_if_affected_core() == ERRATA_APPLIES) { 1674 if (is_feat_trbe_supported()) { 1675 trbe_disable(ctx); 1676 } 1677 } 1678 #endif 1679 1680 #if ENABLE_FEAT_TCR2 == FEAT_STATE_CHECK_ASYMMETRIC 1681 el3_state_t *el3_state = get_el3state_ctx(ctx); 1682 u_register_t spsr = read_ctx_reg(el3_state, CTX_SPSR_EL3); 1683 1684 if (is_feat_tcr2_supported() && (GET_RW(spsr) == MODE_RW_64)) { 1685 tcr2_enable(ctx); 1686 } else { 1687 tcr2_disable(ctx); 1688 } 1689 #endif 1690 1691 } 1692 #endif 1693 1694 /******************************************************************************* 1695 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS 1696 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly 1697 * updating EL1 and EL2 registers. Otherwise, it calls the generic 1698 * cm_prepare_el3_exit function. 1699 ******************************************************************************/ 1700 void cm_prepare_el3_exit_ns(void) 1701 { 1702 #if IMAGE_BL31 1703 /* 1704 * Check and handle Architecture feature asymmetry among cores. 1705 * 1706 * In warmboot path secondary cores context is initialized on core which 1707 * did CPU_ON SMC call, if there is feature asymmetry in these cores handle 1708 * it in this function call. 1709 * For Symmetric cores this is an empty function. 1710 */ 1711 cm_handle_asymmetric_features(); 1712 #endif 1713 1714 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 1715 #if ENABLE_ASSERTIONS 1716 cpu_context_t *ctx = cm_get_context(NON_SECURE); 1717 assert(ctx != NULL); 1718 1719 /* Assert that EL2 is used. */ 1720 u_register_t scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 1721 assert(((scr_el3 & SCR_HCE_BIT) != 0UL) && 1722 (el_implemented(2U) != EL_IMPL_NONE)); 1723 #endif /* ENABLE_ASSERTIONS */ 1724 1725 /* Restore EL2 sysreg contexts */ 1726 cm_el2_sysregs_context_restore(NON_SECURE); 1727 cm_set_next_eret_context(NON_SECURE); 1728 #else 1729 cm_prepare_el3_exit(NON_SECURE); 1730 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 1731 } 1732 1733 #if ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) 1734 /******************************************************************************* 1735 * The next set of six functions are used by runtime services to save and restore 1736 * EL1 context on the 'cpu_context' structure for the specified security state. 1737 ******************************************************************************/ 1738 static void el1_sysregs_context_save(el1_sysregs_t *ctx) 1739 { 1740 write_el1_ctx_common(ctx, spsr_el1, read_spsr_el1()); 1741 write_el1_ctx_common(ctx, elr_el1, read_elr_el1()); 1742 1743 #if (!ERRATA_SPECULATIVE_AT) 1744 write_el1_ctx_common(ctx, sctlr_el1, read_sctlr_el1()); 1745 write_el1_ctx_common(ctx, tcr_el1, read_tcr_el1()); 1746 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1747 1748 write_el1_ctx_common(ctx, cpacr_el1, read_cpacr_el1()); 1749 write_el1_ctx_common(ctx, csselr_el1, read_csselr_el1()); 1750 write_el1_ctx_common(ctx, sp_el1, read_sp_el1()); 1751 write_el1_ctx_common(ctx, esr_el1, read_esr_el1()); 1752 write_el1_ctx_common(ctx, mair_el1, read_mair_el1()); 1753 write_el1_ctx_common(ctx, amair_el1, read_amair_el1()); 1754 write_el1_ctx_common(ctx, actlr_el1, read_actlr_el1()); 1755 write_el1_ctx_common(ctx, tpidr_el1, read_tpidr_el1()); 1756 write_el1_ctx_common(ctx, tpidr_el0, read_tpidr_el0()); 1757 write_el1_ctx_common(ctx, tpidrro_el0, read_tpidrro_el0()); 1758 write_el1_ctx_common(ctx, far_el1, read_far_el1()); 1759 write_el1_ctx_common(ctx, afsr0_el1, read_afsr0_el1()); 1760 write_el1_ctx_common(ctx, afsr1_el1, read_afsr1_el1()); 1761 write_el1_ctx_common(ctx, contextidr_el1, read_contextidr_el1()); 1762 write_el1_ctx_common(ctx, vbar_el1, read_vbar_el1()); 1763 write_el1_ctx_common(ctx, mdccint_el1, read_mdccint_el1()); 1764 write_el1_ctx_common(ctx, mdscr_el1, read_mdscr_el1()); 1765 1766 write_el1_ctx_common_sysreg128(ctx, par_el1, read_par_el1()); 1767 write_el1_ctx_common_sysreg128(ctx, ttbr0_el1, read_ttbr0_el1()); 1768 write_el1_ctx_common_sysreg128(ctx, ttbr1_el1, read_ttbr1_el1()); 1769 1770 if (CTX_INCLUDE_AARCH32_REGS) { 1771 /* Save Aarch32 registers */ 1772 write_el1_ctx_aarch32(ctx, spsr_abt, read_spsr_abt()); 1773 write_el1_ctx_aarch32(ctx, spsr_und, read_spsr_und()); 1774 write_el1_ctx_aarch32(ctx, spsr_irq, read_spsr_irq()); 1775 write_el1_ctx_aarch32(ctx, spsr_fiq, read_spsr_fiq()); 1776 write_el1_ctx_aarch32(ctx, dacr32_el2, read_dacr32_el2()); 1777 write_el1_ctx_aarch32(ctx, ifsr32_el2, read_ifsr32_el2()); 1778 } 1779 1780 if (NS_TIMER_SWITCH) { 1781 /* Save NS Timer registers */ 1782 write_el1_ctx_arch_timer(ctx, cntp_ctl_el0, read_cntp_ctl_el0()); 1783 write_el1_ctx_arch_timer(ctx, cntp_cval_el0, read_cntp_cval_el0()); 1784 write_el1_ctx_arch_timer(ctx, cntv_ctl_el0, read_cntv_ctl_el0()); 1785 write_el1_ctx_arch_timer(ctx, cntv_cval_el0, read_cntv_cval_el0()); 1786 write_el1_ctx_arch_timer(ctx, cntkctl_el1, read_cntkctl_el1()); 1787 } 1788 1789 if (is_feat_mte2_supported()) { 1790 write_el1_ctx_mte2(ctx, tfsre0_el1, read_tfsre0_el1()); 1791 write_el1_ctx_mte2(ctx, tfsr_el1, read_tfsr_el1()); 1792 write_el1_ctx_mte2(ctx, rgsr_el1, read_rgsr_el1()); 1793 write_el1_ctx_mte2(ctx, gcr_el1, read_gcr_el1()); 1794 } 1795 1796 if (is_feat_ras_supported()) { 1797 write_el1_ctx_ras(ctx, disr_el1, read_disr_el1()); 1798 } 1799 1800 if (is_feat_s1pie_supported()) { 1801 write_el1_ctx_s1pie(ctx, pire0_el1, read_pire0_el1()); 1802 write_el1_ctx_s1pie(ctx, pir_el1, read_pir_el1()); 1803 } 1804 1805 if (is_feat_s1poe_supported()) { 1806 write_el1_ctx_s1poe(ctx, por_el1, read_por_el1()); 1807 } 1808 1809 if (is_feat_s2poe_supported()) { 1810 write_el1_ctx_s2poe(ctx, s2por_el1, read_s2por_el1()); 1811 } 1812 1813 if (is_feat_tcr2_supported()) { 1814 write_el1_ctx_tcr2(ctx, tcr2_el1, read_tcr2_el1()); 1815 } 1816 1817 if (is_feat_trf_supported()) { 1818 write_el1_ctx_trf(ctx, trfcr_el1, read_trfcr_el1()); 1819 } 1820 1821 if (is_feat_csv2_2_supported()) { 1822 write_el1_ctx_csv2_2(ctx, scxtnum_el0, read_scxtnum_el0()); 1823 write_el1_ctx_csv2_2(ctx, scxtnum_el1, read_scxtnum_el1()); 1824 } 1825 1826 if (is_feat_gcs_supported()) { 1827 write_el1_ctx_gcs(ctx, gcscr_el1, read_gcscr_el1()); 1828 write_el1_ctx_gcs(ctx, gcscre0_el1, read_gcscre0_el1()); 1829 write_el1_ctx_gcs(ctx, gcspr_el1, read_gcspr_el1()); 1830 write_el1_ctx_gcs(ctx, gcspr_el0, read_gcspr_el0()); 1831 } 1832 1833 if (is_feat_the_supported()) { 1834 write_el1_ctx_the_sysreg128(ctx, rcwmask_el1, read_rcwmask_el1()); 1835 write_el1_ctx_the_sysreg128(ctx, rcwsmask_el1, read_rcwsmask_el1()); 1836 } 1837 1838 if (is_feat_sctlr2_supported()) { 1839 write_el1_ctx_sctlr2(ctx, sctlr2_el1, read_sctlr2_el1()); 1840 } 1841 1842 if (is_feat_ls64_accdata_supported()) { 1843 write_el1_ctx_ls64(ctx, accdata_el1, read_accdata_el1()); 1844 } 1845 } 1846 1847 static void el1_sysregs_context_restore(el1_sysregs_t *ctx) 1848 { 1849 write_spsr_el1(read_el1_ctx_common(ctx, spsr_el1)); 1850 write_elr_el1(read_el1_ctx_common(ctx, elr_el1)); 1851 1852 #if (!ERRATA_SPECULATIVE_AT) 1853 write_sctlr_el1(read_el1_ctx_common(ctx, sctlr_el1)); 1854 write_tcr_el1(read_el1_ctx_common(ctx, tcr_el1)); 1855 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1856 1857 write_cpacr_el1(read_el1_ctx_common(ctx, cpacr_el1)); 1858 write_csselr_el1(read_el1_ctx_common(ctx, csselr_el1)); 1859 write_sp_el1(read_el1_ctx_common(ctx, sp_el1)); 1860 write_esr_el1(read_el1_ctx_common(ctx, esr_el1)); 1861 write_ttbr0_el1(read_el1_ctx_common(ctx, ttbr0_el1)); 1862 write_ttbr1_el1(read_el1_ctx_common(ctx, ttbr1_el1)); 1863 write_mair_el1(read_el1_ctx_common(ctx, mair_el1)); 1864 write_amair_el1(read_el1_ctx_common(ctx, amair_el1)); 1865 write_actlr_el1(read_el1_ctx_common(ctx, actlr_el1)); 1866 write_tpidr_el1(read_el1_ctx_common(ctx, tpidr_el1)); 1867 write_tpidr_el0(read_el1_ctx_common(ctx, tpidr_el0)); 1868 write_tpidrro_el0(read_el1_ctx_common(ctx, tpidrro_el0)); 1869 write_par_el1(read_el1_ctx_common(ctx, par_el1)); 1870 write_far_el1(read_el1_ctx_common(ctx, far_el1)); 1871 write_afsr0_el1(read_el1_ctx_common(ctx, afsr0_el1)); 1872 write_afsr1_el1(read_el1_ctx_common(ctx, afsr1_el1)); 1873 write_contextidr_el1(read_el1_ctx_common(ctx, contextidr_el1)); 1874 write_vbar_el1(read_el1_ctx_common(ctx, vbar_el1)); 1875 write_mdccint_el1(read_el1_ctx_common(ctx, mdccint_el1)); 1876 write_mdscr_el1(read_el1_ctx_common(ctx, mdscr_el1)); 1877 1878 if (CTX_INCLUDE_AARCH32_REGS) { 1879 /* Restore Aarch32 registers */ 1880 write_spsr_abt(read_el1_ctx_aarch32(ctx, spsr_abt)); 1881 write_spsr_und(read_el1_ctx_aarch32(ctx, spsr_und)); 1882 write_spsr_irq(read_el1_ctx_aarch32(ctx, spsr_irq)); 1883 write_spsr_fiq(read_el1_ctx_aarch32(ctx, spsr_fiq)); 1884 write_dacr32_el2(read_el1_ctx_aarch32(ctx, dacr32_el2)); 1885 write_ifsr32_el2(read_el1_ctx_aarch32(ctx, ifsr32_el2)); 1886 } 1887 1888 if (NS_TIMER_SWITCH) { 1889 /* Restore NS Timer registers */ 1890 write_cntp_ctl_el0(read_el1_ctx_arch_timer(ctx, cntp_ctl_el0)); 1891 write_cntp_cval_el0(read_el1_ctx_arch_timer(ctx, cntp_cval_el0)); 1892 write_cntv_ctl_el0(read_el1_ctx_arch_timer(ctx, cntv_ctl_el0)); 1893 write_cntv_cval_el0(read_el1_ctx_arch_timer(ctx, cntv_cval_el0)); 1894 write_cntkctl_el1(read_el1_ctx_arch_timer(ctx, cntkctl_el1)); 1895 } 1896 1897 if (is_feat_mte2_supported()) { 1898 write_tfsre0_el1(read_el1_ctx_mte2(ctx, tfsre0_el1)); 1899 write_tfsr_el1(read_el1_ctx_mte2(ctx, tfsr_el1)); 1900 write_rgsr_el1(read_el1_ctx_mte2(ctx, rgsr_el1)); 1901 write_gcr_el1(read_el1_ctx_mte2(ctx, gcr_el1)); 1902 } 1903 1904 if (is_feat_ras_supported()) { 1905 write_disr_el1(read_el1_ctx_ras(ctx, disr_el1)); 1906 } 1907 1908 if (is_feat_s1pie_supported()) { 1909 write_pire0_el1(read_el1_ctx_s1pie(ctx, pire0_el1)); 1910 write_pir_el1(read_el1_ctx_s1pie(ctx, pir_el1)); 1911 } 1912 1913 if (is_feat_s1poe_supported()) { 1914 write_por_el1(read_el1_ctx_s1poe(ctx, por_el1)); 1915 } 1916 1917 if (is_feat_s2poe_supported()) { 1918 write_s2por_el1(read_el1_ctx_s2poe(ctx, s2por_el1)); 1919 } 1920 1921 if (is_feat_tcr2_supported()) { 1922 write_tcr2_el1(read_el1_ctx_tcr2(ctx, tcr2_el1)); 1923 } 1924 1925 if (is_feat_trf_supported()) { 1926 write_trfcr_el1(read_el1_ctx_trf(ctx, trfcr_el1)); 1927 } 1928 1929 if (is_feat_csv2_2_supported()) { 1930 write_scxtnum_el0(read_el1_ctx_csv2_2(ctx, scxtnum_el0)); 1931 write_scxtnum_el1(read_el1_ctx_csv2_2(ctx, scxtnum_el1)); 1932 } 1933 1934 if (is_feat_gcs_supported()) { 1935 write_gcscr_el1(read_el1_ctx_gcs(ctx, gcscr_el1)); 1936 write_gcscre0_el1(read_el1_ctx_gcs(ctx, gcscre0_el1)); 1937 write_gcspr_el1(read_el1_ctx_gcs(ctx, gcspr_el1)); 1938 write_gcspr_el0(read_el1_ctx_gcs(ctx, gcspr_el0)); 1939 } 1940 1941 if (is_feat_the_supported()) { 1942 write_rcwmask_el1(read_el1_ctx_the(ctx, rcwmask_el1)); 1943 write_rcwsmask_el1(read_el1_ctx_the(ctx, rcwsmask_el1)); 1944 } 1945 1946 if (is_feat_sctlr2_supported()) { 1947 write_sctlr2_el1(read_el1_ctx_sctlr2(ctx, sctlr2_el1)); 1948 } 1949 1950 if (is_feat_ls64_accdata_supported()) { 1951 write_accdata_el1(read_el1_ctx_ls64(ctx, accdata_el1)); 1952 } 1953 } 1954 1955 /******************************************************************************* 1956 * The next couple of functions are used by runtime services to save and restore 1957 * EL1 context on the 'cpu_context' structure for the specified security state. 1958 ******************************************************************************/ 1959 void cm_el1_sysregs_context_save(uint32_t security_state) 1960 { 1961 cpu_context_t *ctx; 1962 1963 ctx = cm_get_context(security_state); 1964 assert(ctx != NULL); 1965 1966 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 1967 1968 #if IMAGE_BL31 1969 if (security_state == SECURE) 1970 PUBLISH_EVENT(cm_exited_secure_world); 1971 else 1972 PUBLISH_EVENT(cm_exited_normal_world); 1973 #endif 1974 } 1975 1976 void cm_el1_sysregs_context_restore(uint32_t security_state) 1977 { 1978 cpu_context_t *ctx; 1979 1980 ctx = cm_get_context(security_state); 1981 assert(ctx != NULL); 1982 1983 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 1984 1985 #if IMAGE_BL31 1986 if (security_state == SECURE) 1987 PUBLISH_EVENT(cm_entering_secure_world); 1988 else 1989 PUBLISH_EVENT(cm_entering_normal_world); 1990 #endif 1991 } 1992 1993 #endif /* ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) */ 1994 1995 /******************************************************************************* 1996 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 1997 * given security state with the given entrypoint 1998 ******************************************************************************/ 1999 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 2000 { 2001 cpu_context_t *ctx; 2002 el3_state_t *state; 2003 2004 ctx = cm_get_context(security_state); 2005 assert(ctx != NULL); 2006 2007 /* Populate EL3 state so that ERET jumps to the correct entry */ 2008 state = get_el3state_ctx(ctx); 2009 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 2010 } 2011 2012 /******************************************************************************* 2013 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 2014 * pertaining to the given security state 2015 ******************************************************************************/ 2016 void cm_set_elr_spsr_el3(uint32_t security_state, 2017 uintptr_t entrypoint, uint32_t spsr) 2018 { 2019 cpu_context_t *ctx; 2020 el3_state_t *state; 2021 2022 ctx = cm_get_context(security_state); 2023 assert(ctx != NULL); 2024 2025 /* Populate EL3 state so that ERET jumps to the correct entry */ 2026 state = get_el3state_ctx(ctx); 2027 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 2028 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 2029 } 2030 2031 /******************************************************************************* 2032 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 2033 * pertaining to the given security state using the value and bit position 2034 * specified in the parameters. It preserves all other bits. 2035 ******************************************************************************/ 2036 void cm_write_scr_el3_bit(uint32_t security_state, 2037 uint32_t bit_pos, 2038 uint32_t value) 2039 { 2040 cpu_context_t *ctx; 2041 el3_state_t *state; 2042 u_register_t scr_el3; 2043 2044 ctx = cm_get_context(security_state); 2045 assert(ctx != NULL); 2046 2047 /* Ensure that the bit position is a valid one */ 2048 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 2049 2050 /* Ensure that the 'value' is only a bit wide */ 2051 assert(value <= 1U); 2052 2053 /* 2054 * Get the SCR_EL3 value from the cpu context, clear the desired bit 2055 * and set it to its new value. 2056 */ 2057 state = get_el3state_ctx(ctx); 2058 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 2059 scr_el3 &= ~(1UL << bit_pos); 2060 scr_el3 |= (u_register_t)value << bit_pos; 2061 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 2062 } 2063 2064 /******************************************************************************* 2065 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 2066 * given security state. 2067 ******************************************************************************/ 2068 u_register_t cm_get_scr_el3(uint32_t security_state) 2069 { 2070 cpu_context_t *ctx; 2071 el3_state_t *state; 2072 2073 ctx = cm_get_context(security_state); 2074 assert(ctx != NULL); 2075 2076 /* Populate EL3 state so that ERET jumps to the correct entry */ 2077 state = get_el3state_ctx(ctx); 2078 return read_ctx_reg(state, CTX_SCR_EL3); 2079 } 2080 2081 /******************************************************************************* 2082 * This function is used to program the context that's used for exception 2083 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 2084 * the required security state 2085 ******************************************************************************/ 2086 void cm_set_next_eret_context(uint32_t security_state) 2087 { 2088 cpu_context_t *ctx; 2089 2090 ctx = cm_get_context(security_state); 2091 assert(ctx != NULL); 2092 2093 cm_set_next_context(ctx); 2094 } 2095