1 /* 2 * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 #include <string.h> 10 11 #include <platform_def.h> 12 13 #include <arch.h> 14 #include <arch_helpers.h> 15 #include <arch_features.h> 16 #include <bl31/interrupt_mgmt.h> 17 #include <common/bl_common.h> 18 #include <context.h> 19 #include <lib/el3_runtime/context_mgmt.h> 20 #include <lib/el3_runtime/pubsub_events.h> 21 #include <lib/extensions/amu.h> 22 #include <lib/extensions/mpam.h> 23 #include <lib/extensions/spe.h> 24 #include <lib/extensions/sve.h> 25 #include <lib/extensions/twed.h> 26 #include <lib/utils.h> 27 28 29 /******************************************************************************* 30 * Context management library initialisation routine. This library is used by 31 * runtime services to share pointers to 'cpu_context' structures for the secure 32 * and non-secure states. Management of the structures and their associated 33 * memory is not done by the context management library e.g. the PSCI service 34 * manages the cpu context used for entry from and exit to the non-secure state. 35 * The Secure payload dispatcher service manages the context(s) corresponding to 36 * the secure state. It also uses this library to get access to the non-secure 37 * state cpu context pointers. 38 * Lastly, this library provides the api to make SP_EL3 point to the cpu context 39 * which will used for programming an entry into a lower EL. The same context 40 * will used to save state upon exception entry from that EL. 41 ******************************************************************************/ 42 void __init cm_init(void) 43 { 44 /* 45 * The context management library has only global data to intialize, but 46 * that will be done when the BSS is zeroed out 47 */ 48 } 49 50 /******************************************************************************* 51 * The following function initializes the cpu_context 'ctx' for 52 * first use, and sets the initial entrypoint state as specified by the 53 * entry_point_info structure. 54 * 55 * The security state to initialize is determined by the SECURE attribute 56 * of the entry_point_info. 57 * 58 * The EE and ST attributes are used to configure the endianness and secure 59 * timer availability for the new execution context. 60 * 61 * To prepare the register state for entry call cm_prepare_el3_exit() and 62 * el3_exit(). For Secure-EL1 cm_prepare_el3_exit() is equivalent to 63 * cm_el1_sysregs_context_restore(). 64 ******************************************************************************/ 65 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 66 { 67 unsigned int security_state; 68 u_register_t scr_el3; 69 el3_state_t *state; 70 gp_regs_t *gp_regs; 71 u_register_t sctlr_elx, actlr_elx; 72 73 assert(ctx != NULL); 74 75 security_state = GET_SECURITY_STATE(ep->h.attr); 76 77 /* Clear any residual register values from the context */ 78 zeromem(ctx, sizeof(*ctx)); 79 80 /* 81 * SCR_EL3 was initialised during reset sequence in macro 82 * el3_arch_init_common. This code modifies the SCR_EL3 fields that 83 * affect the next EL. 84 * 85 * The following fields are initially set to zero and then updated to 86 * the required value depending on the state of the SPSR_EL3 and the 87 * Security state and entrypoint attributes of the next EL. 88 */ 89 scr_el3 = read_scr(); 90 scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT | 91 SCR_ST_BIT | SCR_HCE_BIT); 92 /* 93 * SCR_NS: Set the security state of the next EL. 94 */ 95 if (security_state != SECURE) 96 scr_el3 |= SCR_NS_BIT; 97 /* 98 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 99 * Exception level as specified by SPSR. 100 */ 101 if (GET_RW(ep->spsr) == MODE_RW_64) 102 scr_el3 |= SCR_RW_BIT; 103 /* 104 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 105 * Secure timer registers to EL3, from AArch64 state only, if specified 106 * by the entrypoint attributes. 107 */ 108 if (EP_GET_ST(ep->h.attr) != 0U) 109 scr_el3 |= SCR_ST_BIT; 110 111 #if RAS_TRAP_LOWER_EL_ERR_ACCESS 112 /* 113 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 114 * and RAS ERX registers from EL1 and EL2 are trapped to EL3. 115 */ 116 scr_el3 |= SCR_TERR_BIT; 117 #endif 118 119 #if !HANDLE_EA_EL3_FIRST 120 /* 121 * SCR_EL3.EA: Do not route External Abort and SError Interrupt External 122 * to EL3 when executing at a lower EL. When executing at EL3, External 123 * Aborts are taken to EL3. 124 */ 125 scr_el3 &= ~SCR_EA_BIT; 126 #endif 127 128 #if FAULT_INJECTION_SUPPORT 129 /* Enable fault injection from lower ELs */ 130 scr_el3 |= SCR_FIEN_BIT; 131 #endif 132 133 #if !CTX_INCLUDE_PAUTH_REGS 134 /* 135 * If the pointer authentication registers aren't saved during world 136 * switches the value of the registers can be leaked from the Secure to 137 * the Non-secure world. To prevent this, rather than enabling pointer 138 * authentication everywhere, we only enable it in the Non-secure world. 139 * 140 * If the Secure world wants to use pointer authentication, 141 * CTX_INCLUDE_PAUTH_REGS must be set to 1. 142 */ 143 if (security_state == NON_SECURE) 144 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 145 #endif /* !CTX_INCLUDE_PAUTH_REGS */ 146 147 #if !CTX_INCLUDE_MTE_REGS || ENABLE_ASSERTIONS 148 /* Get Memory Tagging Extension support level */ 149 unsigned int mte = get_armv8_5_mte_support(); 150 #endif 151 /* 152 * Enable MTE support. Support is enabled unilaterally for the normal 153 * world, and only for the secure world when CTX_INCLUDE_MTE_REGS is 154 * set. 155 */ 156 #if CTX_INCLUDE_MTE_REGS 157 assert((mte == MTE_IMPLEMENTED_ELX) || (mte == MTE_IMPLEMENTED_ASY)); 158 scr_el3 |= SCR_ATA_BIT; 159 #else 160 /* 161 * When MTE is only implemented at EL0, it can be enabled 162 * across both worlds as no MTE registers are used. 163 */ 164 if ((mte == MTE_IMPLEMENTED_EL0) || 165 /* 166 * When MTE is implemented at all ELs, it can be only enabled 167 * in Non-Secure world without register saving. 168 */ 169 (((mte == MTE_IMPLEMENTED_ELX) || (mte == MTE_IMPLEMENTED_ASY)) && 170 (security_state == NON_SECURE))) { 171 scr_el3 |= SCR_ATA_BIT; 172 } 173 #endif /* CTX_INCLUDE_MTE_REGS */ 174 175 #ifdef IMAGE_BL31 176 /* 177 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 178 * indicated by the interrupt routing model for BL31. 179 */ 180 scr_el3 |= get_scr_el3_from_routing_model(security_state); 181 182 #if ENABLE_SVE_FOR_NS 183 if (security_state == NON_SECURE) { 184 sve_enable(ctx); 185 } 186 #endif 187 #if ENABLE_SVE_FOR_SWD 188 if (security_state == SECURE) { 189 sve_enable(ctx); 190 } 191 #endif 192 193 #endif 194 195 /* 196 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 197 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 198 * next mode is Hyp. 199 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 200 * same conditions as HVC instructions and when the processor supports 201 * ARMv8.6-FGT. 202 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 203 * CNTPOFF_EL2 register under the same conditions as HVC instructions 204 * and when the processor supports ECV. 205 */ 206 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 207 || ((GET_RW(ep->spsr) != MODE_RW_64) 208 && (GET_M32(ep->spsr) == MODE32_hyp))) { 209 scr_el3 |= SCR_HCE_BIT; 210 211 if (is_armv8_6_fgt_present()) { 212 scr_el3 |= SCR_FGTEN_BIT; 213 } 214 215 if (get_armv8_6_ecv_support() 216 == ID_AA64MMFR0_EL1_ECV_SELF_SYNCH) { 217 scr_el3 |= SCR_ECVEN_BIT; 218 } 219 } 220 221 /* Enable S-EL2 if the next EL is EL2 and security state is secure */ 222 if ((security_state == SECURE) && (GET_EL(ep->spsr) == MODE_EL2)) { 223 if (GET_RW(ep->spsr) != MODE_RW_64) { 224 ERROR("S-EL2 can not be used in AArch32."); 225 panic(); 226 } 227 228 scr_el3 |= SCR_EEL2_BIT; 229 } 230 231 /* 232 * FEAT_AMUv1p1 virtual offset registers are only accessible from EL3 233 * and EL2, when clear, this bit traps accesses from EL2 so we set it 234 * to 1 when EL2 is present. 235 */ 236 if (is_armv8_6_feat_amuv1p1_present() && 237 (el_implemented(2) != EL_IMPL_NONE)) { 238 scr_el3 |= SCR_AMVOFFEN_BIT; 239 } 240 241 /* 242 * Initialise SCTLR_EL1 to the reset value corresponding to the target 243 * execution state setting all fields rather than relying of the hw. 244 * Some fields have architecturally UNKNOWN reset values and these are 245 * set to zero. 246 * 247 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 248 * 249 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 250 * required by PSCI specification) 251 */ 252 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0U; 253 if (GET_RW(ep->spsr) == MODE_RW_64) 254 sctlr_elx |= SCTLR_EL1_RES1; 255 else { 256 /* 257 * If the target execution state is AArch32 then the following 258 * fields need to be set. 259 * 260 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 261 * instructions are not trapped to EL1. 262 * 263 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 264 * instructions are not trapped to EL1. 265 * 266 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 267 * CP15DMB, CP15DSB, and CP15ISB instructions. 268 */ 269 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 270 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 271 } 272 273 #if ERRATA_A75_764081 274 /* 275 * If workaround of errata 764081 for Cortex-A75 is used then set 276 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 277 */ 278 sctlr_elx |= SCTLR_IESB_BIT; 279 #endif 280 281 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 282 if (is_armv8_6_twed_present()) { 283 uint32_t delay = plat_arm_set_twedel_scr_el3(); 284 285 if (delay != TWED_DISABLED) { 286 /* Make sure delay value fits */ 287 assert((delay & ~SCR_TWEDEL_MASK) == 0U); 288 289 /* Set delay in SCR_EL3 */ 290 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 291 scr_el3 |= ((delay & SCR_TWEDEL_MASK) 292 << SCR_TWEDEL_SHIFT); 293 294 /* Enable WFE delay */ 295 scr_el3 |= SCR_TWEDEn_BIT; 296 } 297 } 298 299 /* 300 * Store the initialised SCTLR_EL1 value in the cpu_context - SCTLR_EL2 301 * and other EL2 registers are set up by cm_prepare_el3_exit() as they 302 * are not part of the stored cpu_context. 303 */ 304 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); 305 306 /* 307 * Base the context ACTLR_EL1 on the current value, as it is 308 * implementation defined. The context restore process will write 309 * the value from the context to the actual register and can cause 310 * problems for processor cores that don't expect certain bits to 311 * be zero. 312 */ 313 actlr_elx = read_actlr_el1(); 314 write_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx)); 315 316 /* 317 * Populate EL3 state so that we've the right context 318 * before doing ERET 319 */ 320 state = get_el3state_ctx(ctx); 321 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 322 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 323 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 324 325 /* 326 * Store the X0-X7 value from the entrypoint into the context 327 * Use memcpy as we are in control of the layout of the structures 328 */ 329 gp_regs = get_gpregs_ctx(ctx); 330 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 331 } 332 333 /******************************************************************************* 334 * Enable architecture extensions on first entry to Non-secure world. 335 * When EL2 is implemented but unused `el2_unused` is non-zero, otherwise 336 * it is zero. 337 ******************************************************************************/ 338 static void enable_extensions_nonsecure(bool el2_unused) 339 { 340 #if IMAGE_BL31 341 #if ENABLE_SPE_FOR_LOWER_ELS 342 spe_enable(el2_unused); 343 #endif 344 345 #if ENABLE_AMU 346 amu_enable(el2_unused); 347 #endif 348 349 #if ENABLE_MPAM_FOR_LOWER_ELS 350 mpam_enable(el2_unused); 351 #endif 352 #endif 353 } 354 355 /******************************************************************************* 356 * The following function initializes the cpu_context for a CPU specified by 357 * its `cpu_idx` for first use, and sets the initial entrypoint state as 358 * specified by the entry_point_info structure. 359 ******************************************************************************/ 360 void cm_init_context_by_index(unsigned int cpu_idx, 361 const entry_point_info_t *ep) 362 { 363 cpu_context_t *ctx; 364 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 365 cm_setup_context(ctx, ep); 366 } 367 368 /******************************************************************************* 369 * The following function initializes the cpu_context for the current CPU 370 * for first use, and sets the initial entrypoint state as specified by the 371 * entry_point_info structure. 372 ******************************************************************************/ 373 void cm_init_my_context(const entry_point_info_t *ep) 374 { 375 cpu_context_t *ctx; 376 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 377 cm_setup_context(ctx, ep); 378 } 379 380 /******************************************************************************* 381 * Prepare the CPU system registers for first entry into secure or normal world 382 * 383 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 384 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 385 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 386 * For all entries, the EL1 registers are initialized from the cpu_context 387 ******************************************************************************/ 388 void cm_prepare_el3_exit(uint32_t security_state) 389 { 390 u_register_t sctlr_elx, scr_el3, mdcr_el2; 391 cpu_context_t *ctx = cm_get_context(security_state); 392 bool el2_unused = false; 393 uint64_t hcr_el2 = 0U; 394 395 assert(ctx != NULL); 396 397 if (security_state == NON_SECURE) { 398 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 399 CTX_SCR_EL3); 400 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 401 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */ 402 sctlr_elx = read_ctx_reg(get_el1_sysregs_ctx(ctx), 403 CTX_SCTLR_EL1); 404 sctlr_elx &= SCTLR_EE_BIT; 405 sctlr_elx |= SCTLR_EL2_RES1; 406 #if ERRATA_A75_764081 407 /* 408 * If workaround of errata 764081 for Cortex-A75 is used 409 * then set SCTLR_EL2.IESB to enable Implicit Error 410 * Synchronization Barrier. 411 */ 412 sctlr_elx |= SCTLR_IESB_BIT; 413 #endif 414 write_sctlr_el2(sctlr_elx); 415 } else if (el_implemented(2) != EL_IMPL_NONE) { 416 el2_unused = true; 417 418 /* 419 * EL2 present but unused, need to disable safely. 420 * SCTLR_EL2 can be ignored in this case. 421 * 422 * Set EL2 register width appropriately: Set HCR_EL2 423 * field to match SCR_EL3.RW. 424 */ 425 if ((scr_el3 & SCR_RW_BIT) != 0U) 426 hcr_el2 |= HCR_RW_BIT; 427 428 /* 429 * For Armv8.3 pointer authentication feature, disable 430 * traps to EL2 when accessing key registers or using 431 * pointer authentication instructions from lower ELs. 432 */ 433 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 434 435 write_hcr_el2(hcr_el2); 436 437 /* 438 * Initialise CPTR_EL2 setting all fields rather than 439 * relying on the hw. All fields have architecturally 440 * UNKNOWN reset values. 441 * 442 * CPTR_EL2.TCPAC: Set to zero so that Non-secure EL1 443 * accesses to the CPACR_EL1 or CPACR from both 444 * Execution states do not trap to EL2. 445 * 446 * CPTR_EL2.TTA: Set to zero so that Non-secure System 447 * register accesses to the trace registers from both 448 * Execution states do not trap to EL2. 449 * 450 * CPTR_EL2.TFP: Set to zero so that Non-secure accesses 451 * to SIMD and floating-point functionality from both 452 * Execution states do not trap to EL2. 453 */ 454 write_cptr_el2(CPTR_EL2_RESET_VAL & 455 ~(CPTR_EL2_TCPAC_BIT | CPTR_EL2_TTA_BIT 456 | CPTR_EL2_TFP_BIT)); 457 458 /* 459 * Initialise CNTHCTL_EL2. All fields are 460 * architecturally UNKNOWN on reset and are set to zero 461 * except for field(s) listed below. 462 * 463 * CNTHCTL_EL2.EL1PCEN: Set to one to disable traps to 464 * Hyp mode of Non-secure EL0 and EL1 accesses to the 465 * physical timer registers. 466 * 467 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to 468 * Hyp mode of Non-secure EL0 and EL1 accesses to the 469 * physical counter registers. 470 */ 471 write_cnthctl_el2(CNTHCTL_RESET_VAL | 472 EL1PCEN_BIT | EL1PCTEN_BIT); 473 474 /* 475 * Initialise CNTVOFF_EL2 to zero as it resets to an 476 * architecturally UNKNOWN value. 477 */ 478 write_cntvoff_el2(0); 479 480 /* 481 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and 482 * MPIDR_EL1 respectively. 483 */ 484 write_vpidr_el2(read_midr_el1()); 485 write_vmpidr_el2(read_mpidr_el1()); 486 487 /* 488 * Initialise VTTBR_EL2. All fields are architecturally 489 * UNKNOWN on reset. 490 * 491 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 492 * 2 address translation is disabled, cache maintenance 493 * operations depend on the VMID. 494 * 495 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address 496 * translation is disabled. 497 */ 498 write_vttbr_el2(VTTBR_RESET_VAL & 499 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) 500 | (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 501 502 /* 503 * Initialise MDCR_EL2, setting all fields rather than 504 * relying on hw. Some fields are architecturally 505 * UNKNOWN on reset. 506 * 507 * MDCR_EL2.HLP: Set to one so that event counter 508 * overflow, that is recorded in PMOVSCLR_EL0[0-30], 509 * occurs on the increment that changes 510 * PMEVCNTR<n>_EL0[63] from 1 to 0, when ARMv8.5-PMU is 511 * implemented. This bit is RES0 in versions of the 512 * architecture earlier than ARMv8.5, setting it to 1 513 * doesn't have any effect on them. 514 * 515 * MDCR_EL2.TTRF: Set to zero so that access to Trace 516 * Filter Control register TRFCR_EL1 at EL1 is not 517 * trapped to EL2. This bit is RES0 in versions of 518 * the architecture earlier than ARMv8.4. 519 * 520 * MDCR_EL2.HPMD: Set to one so that event counting is 521 * prohibited at EL2. This bit is RES0 in versions of 522 * the architecture earlier than ARMv8.1, setting it 523 * to 1 doesn't have any effect on them. 524 * 525 * MDCR_EL2.TPMS: Set to zero so that accesses to 526 * Statistical Profiling control registers from EL1 527 * do not trap to EL2. This bit is RES0 when SPE is 528 * not implemented. 529 * 530 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and 531 * EL1 System register accesses to the Debug ROM 532 * registers are not trapped to EL2. 533 * 534 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 535 * System register accesses to the powerdown debug 536 * registers are not trapped to EL2. 537 * 538 * MDCR_EL2.TDA: Set to zero so that System register 539 * accesses to the debug registers do not trap to EL2. 540 * 541 * MDCR_EL2.TDE: Set to zero so that debug exceptions 542 * are not routed to EL2. 543 * 544 * MDCR_EL2.HPME: Set to zero to disable EL2 Performance 545 * Monitors. 546 * 547 * MDCR_EL2.TPM: Set to zero so that Non-secure EL0 and 548 * EL1 accesses to all Performance Monitors registers 549 * are not trapped to EL2. 550 * 551 * MDCR_EL2.TPMCR: Set to zero so that Non-secure EL0 552 * and EL1 accesses to the PMCR_EL0 or PMCR are not 553 * trapped to EL2. 554 * 555 * MDCR_EL2.HPMN: Set to value of PMCR_EL0.N which is the 556 * architecturally-defined reset value. 557 */ 558 mdcr_el2 = ((MDCR_EL2_RESET_VAL | MDCR_EL2_HLP | 559 MDCR_EL2_HPMD) | 560 ((read_pmcr_el0() & PMCR_EL0_N_BITS) 561 >> PMCR_EL0_N_SHIFT)) & 562 ~(MDCR_EL2_TTRF | MDCR_EL2_TPMS | 563 MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | 564 MDCR_EL2_TDA_BIT | MDCR_EL2_TDE_BIT | 565 MDCR_EL2_HPME_BIT | MDCR_EL2_TPM_BIT | 566 MDCR_EL2_TPMCR_BIT); 567 568 write_mdcr_el2(mdcr_el2); 569 570 /* 571 * Initialise HSTR_EL2. All fields are architecturally 572 * UNKNOWN on reset. 573 * 574 * HSTR_EL2.T<n>: Set all these fields to zero so that 575 * Non-secure EL0 or EL1 accesses to System registers 576 * do not trap to EL2. 577 */ 578 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 579 /* 580 * Initialise CNTHP_CTL_EL2. All fields are 581 * architecturally UNKNOWN on reset. 582 * 583 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 584 * physical timer and prevent timer interrupts. 585 */ 586 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & 587 ~(CNTHP_CTL_ENABLE_BIT)); 588 } 589 enable_extensions_nonsecure(el2_unused); 590 } 591 592 cm_el1_sysregs_context_restore(security_state); 593 cm_set_next_eret_context(security_state); 594 } 595 596 #if CTX_INCLUDE_EL2_REGS 597 /******************************************************************************* 598 * Save EL2 sysreg context 599 ******************************************************************************/ 600 void cm_el2_sysregs_context_save(uint32_t security_state) 601 { 602 u_register_t scr_el3 = read_scr(); 603 604 /* 605 * Always save the non-secure EL2 context, only save the 606 * S-EL2 context if S-EL2 is enabled. 607 */ 608 if ((security_state == NON_SECURE) || 609 ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) { 610 cpu_context_t *ctx; 611 612 ctx = cm_get_context(security_state); 613 assert(ctx != NULL); 614 615 el2_sysregs_context_save(get_el2_sysregs_ctx(ctx)); 616 } 617 } 618 619 /******************************************************************************* 620 * Restore EL2 sysreg context 621 ******************************************************************************/ 622 void cm_el2_sysregs_context_restore(uint32_t security_state) 623 { 624 u_register_t scr_el3 = read_scr(); 625 626 /* 627 * Always restore the non-secure EL2 context, only restore the 628 * S-EL2 context if S-EL2 is enabled. 629 */ 630 if ((security_state == NON_SECURE) || 631 ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) { 632 cpu_context_t *ctx; 633 634 ctx = cm_get_context(security_state); 635 assert(ctx != NULL); 636 637 el2_sysregs_context_restore(get_el2_sysregs_ctx(ctx)); 638 } 639 } 640 #endif /* CTX_INCLUDE_EL2_REGS */ 641 642 /******************************************************************************* 643 * The next four functions are used by runtime services to save and restore 644 * EL1 context on the 'cpu_context' structure for the specified security 645 * state. 646 ******************************************************************************/ 647 void cm_el1_sysregs_context_save(uint32_t security_state) 648 { 649 cpu_context_t *ctx; 650 651 ctx = cm_get_context(security_state); 652 assert(ctx != NULL); 653 654 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 655 656 #if IMAGE_BL31 657 if (security_state == SECURE) 658 PUBLISH_EVENT(cm_exited_secure_world); 659 else 660 PUBLISH_EVENT(cm_exited_normal_world); 661 #endif 662 } 663 664 void cm_el1_sysregs_context_restore(uint32_t security_state) 665 { 666 cpu_context_t *ctx; 667 668 ctx = cm_get_context(security_state); 669 assert(ctx != NULL); 670 671 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 672 673 #if IMAGE_BL31 674 if (security_state == SECURE) 675 PUBLISH_EVENT(cm_entering_secure_world); 676 else 677 PUBLISH_EVENT(cm_entering_normal_world); 678 #endif 679 } 680 681 /******************************************************************************* 682 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 683 * given security state with the given entrypoint 684 ******************************************************************************/ 685 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 686 { 687 cpu_context_t *ctx; 688 el3_state_t *state; 689 690 ctx = cm_get_context(security_state); 691 assert(ctx != NULL); 692 693 /* Populate EL3 state so that ERET jumps to the correct entry */ 694 state = get_el3state_ctx(ctx); 695 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 696 } 697 698 /******************************************************************************* 699 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 700 * pertaining to the given security state 701 ******************************************************************************/ 702 void cm_set_elr_spsr_el3(uint32_t security_state, 703 uintptr_t entrypoint, uint32_t spsr) 704 { 705 cpu_context_t *ctx; 706 el3_state_t *state; 707 708 ctx = cm_get_context(security_state); 709 assert(ctx != NULL); 710 711 /* Populate EL3 state so that ERET jumps to the correct entry */ 712 state = get_el3state_ctx(ctx); 713 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 714 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 715 } 716 717 /******************************************************************************* 718 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 719 * pertaining to the given security state using the value and bit position 720 * specified in the parameters. It preserves all other bits. 721 ******************************************************************************/ 722 void cm_write_scr_el3_bit(uint32_t security_state, 723 uint32_t bit_pos, 724 uint32_t value) 725 { 726 cpu_context_t *ctx; 727 el3_state_t *state; 728 u_register_t scr_el3; 729 730 ctx = cm_get_context(security_state); 731 assert(ctx != NULL); 732 733 /* Ensure that the bit position is a valid one */ 734 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 735 736 /* Ensure that the 'value' is only a bit wide */ 737 assert(value <= 1U); 738 739 /* 740 * Get the SCR_EL3 value from the cpu context, clear the desired bit 741 * and set it to its new value. 742 */ 743 state = get_el3state_ctx(ctx); 744 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 745 scr_el3 &= ~(1UL << bit_pos); 746 scr_el3 |= (u_register_t)value << bit_pos; 747 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 748 } 749 750 /******************************************************************************* 751 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 752 * given security state. 753 ******************************************************************************/ 754 u_register_t cm_get_scr_el3(uint32_t security_state) 755 { 756 cpu_context_t *ctx; 757 el3_state_t *state; 758 759 ctx = cm_get_context(security_state); 760 assert(ctx != NULL); 761 762 /* Populate EL3 state so that ERET jumps to the correct entry */ 763 state = get_el3state_ctx(ctx); 764 return read_ctx_reg(state, CTX_SCR_EL3); 765 } 766 767 /******************************************************************************* 768 * This function is used to program the context that's used for exception 769 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 770 * the required security state 771 ******************************************************************************/ 772 void cm_set_next_eret_context(uint32_t security_state) 773 { 774 cpu_context_t *ctx; 775 776 ctx = cm_get_context(security_state); 777 assert(ctx != NULL); 778 779 cm_set_next_context(ctx); 780 } 781