1 /* 2 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 #include <string.h> 10 11 #include <platform_def.h> 12 13 #include <arch.h> 14 #include <arch_helpers.h> 15 #include <bl31/interrupt_mgmt.h> 16 #include <common/bl_common.h> 17 #include <context.h> 18 #include <lib/el3_runtime/context_mgmt.h> 19 #include <lib/el3_runtime/pubsub_events.h> 20 #include <lib/extensions/amu.h> 21 #include <lib/extensions/mpam.h> 22 #include <lib/extensions/spe.h> 23 #include <lib/extensions/sve.h> 24 #include <lib/utils.h> 25 #include <plat/common/platform.h> 26 #include <smccc_helpers.h> 27 28 29 /******************************************************************************* 30 * Context management library initialisation routine. This library is used by 31 * runtime services to share pointers to 'cpu_context' structures for the secure 32 * and non-secure states. Management of the structures and their associated 33 * memory is not done by the context management library e.g. the PSCI service 34 * manages the cpu context used for entry from and exit to the non-secure state. 35 * The Secure payload dispatcher service manages the context(s) corresponding to 36 * the secure state. It also uses this library to get access to the non-secure 37 * state cpu context pointers. 38 * Lastly, this library provides the api to make SP_EL3 point to the cpu context 39 * which will used for programming an entry into a lower EL. The same context 40 * will used to save state upon exception entry from that EL. 41 ******************************************************************************/ 42 void __init cm_init(void) 43 { 44 /* 45 * The context management library has only global data to intialize, but 46 * that will be done when the BSS is zeroed out 47 */ 48 } 49 50 /******************************************************************************* 51 * The following function initializes the cpu_context 'ctx' for 52 * first use, and sets the initial entrypoint state as specified by the 53 * entry_point_info structure. 54 * 55 * The security state to initialize is determined by the SECURE attribute 56 * of the entry_point_info. 57 * 58 * The EE and ST attributes are used to configure the endianness and secure 59 * timer availability for the new execution context. 60 * 61 * To prepare the register state for entry call cm_prepare_el3_exit() and 62 * el3_exit(). For Secure-EL1 cm_prepare_el3_exit() is equivalent to 63 * cm_e1_sysreg_context_restore(). 64 ******************************************************************************/ 65 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 66 { 67 unsigned int security_state; 68 uint32_t scr_el3, pmcr_el0; 69 el3_state_t *state; 70 gp_regs_t *gp_regs; 71 unsigned long sctlr_elx, actlr_elx; 72 73 assert(ctx != NULL); 74 75 security_state = GET_SECURITY_STATE(ep->h.attr); 76 77 /* Clear any residual register values from the context */ 78 zeromem(ctx, sizeof(*ctx)); 79 80 /* 81 * SCR_EL3 was initialised during reset sequence in macro 82 * el3_arch_init_common. This code modifies the SCR_EL3 fields that 83 * affect the next EL. 84 * 85 * The following fields are initially set to zero and then updated to 86 * the required value depending on the state of the SPSR_EL3 and the 87 * Security state and entrypoint attributes of the next EL. 88 */ 89 scr_el3 = (uint32_t)read_scr(); 90 scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT | 91 SCR_ST_BIT | SCR_HCE_BIT); 92 /* 93 * SCR_NS: Set the security state of the next EL. 94 */ 95 if (security_state != SECURE) 96 scr_el3 |= SCR_NS_BIT; 97 /* 98 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 99 * Exception level as specified by SPSR. 100 */ 101 if (GET_RW(ep->spsr) == MODE_RW_64) 102 scr_el3 |= SCR_RW_BIT; 103 /* 104 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 105 * Secure timer registers to EL3, from AArch64 state only, if specified 106 * by the entrypoint attributes. 107 */ 108 if (EP_GET_ST(ep->h.attr) != 0U) 109 scr_el3 |= SCR_ST_BIT; 110 111 #if !HANDLE_EA_EL3_FIRST 112 /* 113 * SCR_EL3.EA: Do not route External Abort and SError Interrupt External 114 * to EL3 when executing at a lower EL. When executing at EL3, External 115 * Aborts are taken to EL3. 116 */ 117 scr_el3 &= ~SCR_EA_BIT; 118 #endif 119 120 #if FAULT_INJECTION_SUPPORT 121 /* Enable fault injection from lower ELs */ 122 scr_el3 |= SCR_FIEN_BIT; 123 #endif 124 125 #ifdef IMAGE_BL31 126 /* 127 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 128 * indicated by the interrupt routing model for BL31. 129 */ 130 scr_el3 |= get_scr_el3_from_routing_model(security_state); 131 #endif 132 133 /* 134 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 135 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 136 * next mode is Hyp. 137 */ 138 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 139 || ((GET_RW(ep->spsr) != MODE_RW_64) 140 && (GET_M32(ep->spsr) == MODE32_hyp))) { 141 scr_el3 |= SCR_HCE_BIT; 142 } 143 144 /* 145 * Initialise SCTLR_EL1 to the reset value corresponding to the target 146 * execution state setting all fields rather than relying of the hw. 147 * Some fields have architecturally UNKNOWN reset values and these are 148 * set to zero. 149 * 150 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 151 * 152 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 153 * required by PSCI specification) 154 */ 155 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0U; 156 if (GET_RW(ep->spsr) == MODE_RW_64) 157 sctlr_elx |= SCTLR_EL1_RES1; 158 else { 159 /* 160 * If the target execution state is AArch32 then the following 161 * fields need to be set. 162 * 163 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 164 * instructions are not trapped to EL1. 165 * 166 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 167 * instructions are not trapped to EL1. 168 * 169 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 170 * CP15DMB, CP15DSB, and CP15ISB instructions. 171 */ 172 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 173 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 174 } 175 176 /* 177 * Store the initialised SCTLR_EL1 value in the cpu_context - SCTLR_EL2 178 * and other EL2 registers are set up by cm_prepare_ns_entry() as they 179 * are not part of the stored cpu_context. 180 */ 181 write_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); 182 183 /* 184 * Base the context ACTLR_EL1 on the current value, as it is 185 * implementation defined. The context restore process will write 186 * the value from the context to the actual register and can cause 187 * problems for processor cores that don't expect certain bits to 188 * be zero. 189 */ 190 actlr_elx = read_actlr_el1(); 191 write_ctx_reg((get_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx)); 192 193 if (security_state == SECURE) { 194 /* 195 * Initialise PMCR_EL0 for secure context only, setting all 196 * fields rather than relying on hw. Some fields are 197 * architecturally UNKNOWN on reset. 198 * 199 * PMCR_EL0.LC: Set to one so that cycle counter overflow, that 200 * is recorded in PMOVSCLR_EL0[31], occurs on the increment 201 * that changes PMCCNTR_EL0[63] from 1 to 0. 202 * 203 * PMCR_EL0.DP: Set to one so that the cycle counter, 204 * PMCCNTR_EL0 does not count when event counting is prohibited. 205 * 206 * PMCR_EL0.X: Set to zero to disable export of events. 207 * 208 * PMCR_EL0.D: Set to zero so that, when enabled, PMCCNTR_EL0 209 * counts on every clock cycle. 210 */ 211 pmcr_el0 = ((PMCR_EL0_RESET_VAL | PMCR_EL0_LC_BIT 212 | PMCR_EL0_DP_BIT) 213 & ~(PMCR_EL0_X_BIT | PMCR_EL0_D_BIT)); 214 write_ctx_reg(get_sysregs_ctx(ctx), CTX_PMCR_EL0, pmcr_el0); 215 } 216 217 /* Populate EL3 state so that we've the right context before doing ERET */ 218 state = get_el3state_ctx(ctx); 219 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 220 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 221 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 222 223 /* 224 * Store the X0-X7 value from the entrypoint into the context 225 * Use memcpy as we are in control of the layout of the structures 226 */ 227 gp_regs = get_gpregs_ctx(ctx); 228 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 229 } 230 231 /******************************************************************************* 232 * Enable architecture extensions on first entry to Non-secure world. 233 * When EL2 is implemented but unused `el2_unused` is non-zero, otherwise 234 * it is zero. 235 ******************************************************************************/ 236 static void enable_extensions_nonsecure(bool el2_unused) 237 { 238 #if IMAGE_BL31 239 #if ENABLE_SPE_FOR_LOWER_ELS 240 spe_enable(el2_unused); 241 #endif 242 243 #if ENABLE_AMU 244 amu_enable(el2_unused); 245 #endif 246 247 #if ENABLE_SVE_FOR_NS 248 sve_enable(el2_unused); 249 #endif 250 251 #if ENABLE_MPAM_FOR_LOWER_ELS 252 mpam_enable(el2_unused); 253 #endif 254 #endif 255 } 256 257 /******************************************************************************* 258 * The following function initializes the cpu_context for a CPU specified by 259 * its `cpu_idx` for first use, and sets the initial entrypoint state as 260 * specified by the entry_point_info structure. 261 ******************************************************************************/ 262 void cm_init_context_by_index(unsigned int cpu_idx, 263 const entry_point_info_t *ep) 264 { 265 cpu_context_t *ctx; 266 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 267 cm_setup_context(ctx, ep); 268 } 269 270 /******************************************************************************* 271 * The following function initializes the cpu_context for the current CPU 272 * for first use, and sets the initial entrypoint state as specified by the 273 * entry_point_info structure. 274 ******************************************************************************/ 275 void cm_init_my_context(const entry_point_info_t *ep) 276 { 277 cpu_context_t *ctx; 278 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 279 cm_setup_context(ctx, ep); 280 } 281 282 /******************************************************************************* 283 * Prepare the CPU system registers for first entry into secure or normal world 284 * 285 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 286 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 287 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 288 * For all entries, the EL1 registers are initialized from the cpu_context 289 ******************************************************************************/ 290 void cm_prepare_el3_exit(uint32_t security_state) 291 { 292 uint32_t sctlr_elx, scr_el3, mdcr_el2; 293 cpu_context_t *ctx = cm_get_context(security_state); 294 bool el2_unused = false; 295 uint64_t hcr_el2 = 0U; 296 297 assert(ctx != NULL); 298 299 if (security_state == NON_SECURE) { 300 scr_el3 = (uint32_t)read_ctx_reg(get_el3state_ctx(ctx), 301 CTX_SCR_EL3); 302 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 303 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */ 304 sctlr_elx = (uint32_t)read_ctx_reg(get_sysregs_ctx(ctx), 305 CTX_SCTLR_EL1); 306 sctlr_elx &= SCTLR_EE_BIT; 307 sctlr_elx |= SCTLR_EL2_RES1; 308 write_sctlr_el2(sctlr_elx); 309 } else if (el_implemented(2) != EL_IMPL_NONE) { 310 el2_unused = true; 311 312 /* 313 * EL2 present but unused, need to disable safely. 314 * SCTLR_EL2 can be ignored in this case. 315 * 316 * Set EL2 register width appropriately: Set HCR_EL2 317 * field to match SCR_EL3.RW. 318 */ 319 if ((scr_el3 & SCR_RW_BIT) != 0U) 320 hcr_el2 |= HCR_RW_BIT; 321 322 /* 323 * For Armv8.3 pointer authentication feature, disable 324 * traps to EL2 when accessing key registers or using 325 * pointer authentication instructions from lower ELs. 326 */ 327 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 328 329 write_hcr_el2(hcr_el2); 330 331 /* 332 * Initialise CPTR_EL2 setting all fields rather than 333 * relying on the hw. All fields have architecturally 334 * UNKNOWN reset values. 335 * 336 * CPTR_EL2.TCPAC: Set to zero so that Non-secure EL1 337 * accesses to the CPACR_EL1 or CPACR from both 338 * Execution states do not trap to EL2. 339 * 340 * CPTR_EL2.TTA: Set to zero so that Non-secure System 341 * register accesses to the trace registers from both 342 * Execution states do not trap to EL2. 343 * 344 * CPTR_EL2.TFP: Set to zero so that Non-secure accesses 345 * to SIMD and floating-point functionality from both 346 * Execution states do not trap to EL2. 347 */ 348 write_cptr_el2(CPTR_EL2_RESET_VAL & 349 ~(CPTR_EL2_TCPAC_BIT | CPTR_EL2_TTA_BIT 350 | CPTR_EL2_TFP_BIT)); 351 352 /* 353 * Initialise CNTHCTL_EL2. All fields are 354 * architecturally UNKNOWN on reset and are set to zero 355 * except for field(s) listed below. 356 * 357 * CNTHCTL_EL2.EL1PCEN: Set to one to disable traps to 358 * Hyp mode of Non-secure EL0 and EL1 accesses to the 359 * physical timer registers. 360 * 361 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to 362 * Hyp mode of Non-secure EL0 and EL1 accesses to the 363 * physical counter registers. 364 */ 365 write_cnthctl_el2(CNTHCTL_RESET_VAL | 366 EL1PCEN_BIT | EL1PCTEN_BIT); 367 368 /* 369 * Initialise CNTVOFF_EL2 to zero as it resets to an 370 * architecturally UNKNOWN value. 371 */ 372 write_cntvoff_el2(0); 373 374 /* 375 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and 376 * MPIDR_EL1 respectively. 377 */ 378 write_vpidr_el2(read_midr_el1()); 379 write_vmpidr_el2(read_mpidr_el1()); 380 381 /* 382 * Initialise VTTBR_EL2. All fields are architecturally 383 * UNKNOWN on reset. 384 * 385 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 386 * 2 address translation is disabled, cache maintenance 387 * operations depend on the VMID. 388 * 389 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address 390 * translation is disabled. 391 */ 392 write_vttbr_el2(VTTBR_RESET_VAL & 393 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) 394 | (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 395 396 /* 397 * Initialise MDCR_EL2, setting all fields rather than 398 * relying on hw. Some fields are architecturally 399 * UNKNOWN on reset. 400 * 401 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and 402 * EL1 System register accesses to the Debug ROM 403 * registers are not trapped to EL2. 404 * 405 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 406 * System register accesses to the powerdown debug 407 * registers are not trapped to EL2. 408 * 409 * MDCR_EL2.TDA: Set to zero so that System register 410 * accesses to the debug registers do not trap to EL2. 411 * 412 * MDCR_EL2.TDE: Set to zero so that debug exceptions 413 * are not routed to EL2. 414 * 415 * MDCR_EL2.HPME: Set to zero to disable EL2 Performance 416 * Monitors. 417 * 418 * MDCR_EL2.TPM: Set to zero so that Non-secure EL0 and 419 * EL1 accesses to all Performance Monitors registers 420 * are not trapped to EL2. 421 * 422 * MDCR_EL2.TPMCR: Set to zero so that Non-secure EL0 423 * and EL1 accesses to the PMCR_EL0 or PMCR are not 424 * trapped to EL2. 425 * 426 * MDCR_EL2.HPMN: Set to value of PMCR_EL0.N which is the 427 * architecturally-defined reset value. 428 */ 429 mdcr_el2 = ((MDCR_EL2_RESET_VAL | 430 ((read_pmcr_el0() & PMCR_EL0_N_BITS) 431 >> PMCR_EL0_N_SHIFT)) & 432 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT 433 | MDCR_EL2_TDA_BIT | MDCR_EL2_TDE_BIT 434 | MDCR_EL2_HPME_BIT | MDCR_EL2_TPM_BIT 435 | MDCR_EL2_TPMCR_BIT)); 436 437 write_mdcr_el2(mdcr_el2); 438 439 /* 440 * Initialise HSTR_EL2. All fields are architecturally 441 * UNKNOWN on reset. 442 * 443 * HSTR_EL2.T<n>: Set all these fields to zero so that 444 * Non-secure EL0 or EL1 accesses to System registers 445 * do not trap to EL2. 446 */ 447 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 448 /* 449 * Initialise CNTHP_CTL_EL2. All fields are 450 * architecturally UNKNOWN on reset. 451 * 452 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 453 * physical timer and prevent timer interrupts. 454 */ 455 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & 456 ~(CNTHP_CTL_ENABLE_BIT)); 457 } 458 enable_extensions_nonsecure(el2_unused); 459 } 460 461 cm_el1_sysregs_context_restore(security_state); 462 cm_set_next_eret_context(security_state); 463 } 464 465 /******************************************************************************* 466 * The next four functions are used by runtime services to save and restore 467 * EL1 context on the 'cpu_context' structure for the specified security 468 * state. 469 ******************************************************************************/ 470 void cm_el1_sysregs_context_save(uint32_t security_state) 471 { 472 cpu_context_t *ctx; 473 474 ctx = cm_get_context(security_state); 475 assert(ctx != NULL); 476 477 el1_sysregs_context_save(get_sysregs_ctx(ctx)); 478 479 #if IMAGE_BL31 480 if (security_state == SECURE) 481 PUBLISH_EVENT(cm_exited_secure_world); 482 else 483 PUBLISH_EVENT(cm_exited_normal_world); 484 #endif 485 } 486 487 void cm_el1_sysregs_context_restore(uint32_t security_state) 488 { 489 cpu_context_t *ctx; 490 491 ctx = cm_get_context(security_state); 492 assert(ctx != NULL); 493 494 el1_sysregs_context_restore(get_sysregs_ctx(ctx)); 495 496 #if IMAGE_BL31 497 if (security_state == SECURE) 498 PUBLISH_EVENT(cm_entering_secure_world); 499 else 500 PUBLISH_EVENT(cm_entering_normal_world); 501 #endif 502 } 503 504 /******************************************************************************* 505 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 506 * given security state with the given entrypoint 507 ******************************************************************************/ 508 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 509 { 510 cpu_context_t *ctx; 511 el3_state_t *state; 512 513 ctx = cm_get_context(security_state); 514 assert(ctx != NULL); 515 516 /* Populate EL3 state so that ERET jumps to the correct entry */ 517 state = get_el3state_ctx(ctx); 518 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 519 } 520 521 /******************************************************************************* 522 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 523 * pertaining to the given security state 524 ******************************************************************************/ 525 void cm_set_elr_spsr_el3(uint32_t security_state, 526 uintptr_t entrypoint, uint32_t spsr) 527 { 528 cpu_context_t *ctx; 529 el3_state_t *state; 530 531 ctx = cm_get_context(security_state); 532 assert(ctx != NULL); 533 534 /* Populate EL3 state so that ERET jumps to the correct entry */ 535 state = get_el3state_ctx(ctx); 536 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 537 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 538 } 539 540 /******************************************************************************* 541 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 542 * pertaining to the given security state using the value and bit position 543 * specified in the parameters. It preserves all other bits. 544 ******************************************************************************/ 545 void cm_write_scr_el3_bit(uint32_t security_state, 546 uint32_t bit_pos, 547 uint32_t value) 548 { 549 cpu_context_t *ctx; 550 el3_state_t *state; 551 uint32_t scr_el3; 552 553 ctx = cm_get_context(security_state); 554 assert(ctx != NULL); 555 556 /* Ensure that the bit position is a valid one */ 557 assert(((1U << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 558 559 /* Ensure that the 'value' is only a bit wide */ 560 assert(value <= 1U); 561 562 /* 563 * Get the SCR_EL3 value from the cpu context, clear the desired bit 564 * and set it to its new value. 565 */ 566 state = get_el3state_ctx(ctx); 567 scr_el3 = (uint32_t)read_ctx_reg(state, CTX_SCR_EL3); 568 scr_el3 &= ~(1U << bit_pos); 569 scr_el3 |= value << bit_pos; 570 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 571 } 572 573 /******************************************************************************* 574 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 575 * given security state. 576 ******************************************************************************/ 577 uint32_t cm_get_scr_el3(uint32_t security_state) 578 { 579 cpu_context_t *ctx; 580 el3_state_t *state; 581 582 ctx = cm_get_context(security_state); 583 assert(ctx != NULL); 584 585 /* Populate EL3 state so that ERET jumps to the correct entry */ 586 state = get_el3state_ctx(ctx); 587 return (uint32_t)read_ctx_reg(state, CTX_SCR_EL3); 588 } 589 590 /******************************************************************************* 591 * This function is used to program the context that's used for exception 592 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 593 * the required security state 594 ******************************************************************************/ 595 void cm_set_next_eret_context(uint32_t security_state) 596 { 597 cpu_context_t *ctx; 598 599 ctx = cm_get_context(security_state); 600 assert(ctx != NULL); 601 602 cm_set_next_context(ctx); 603 } 604