1 /* 2 * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <stdbool.h> 10 #include <string.h> 11 12 #include <platform_def.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <arch_features.h> 17 #include <bl31/interrupt_mgmt.h> 18 #include <common/bl_common.h> 19 #include <common/debug.h> 20 #include <context.h> 21 #include <drivers/arm/gicv3.h> 22 #include <lib/cpus/cpu_ops.h> 23 #include <lib/cpus/errata.h> 24 #include <lib/el3_runtime/context_mgmt.h> 25 #include <lib/el3_runtime/cpu_data.h> 26 #include <lib/el3_runtime/pubsub_events.h> 27 #include <lib/extensions/amu.h> 28 #include <lib/extensions/brbe.h> 29 #include <lib/extensions/debug_v8p9.h> 30 #include <lib/extensions/fgt2.h> 31 #include <lib/extensions/fpmr.h> 32 #include <lib/extensions/mpam.h> 33 #include <lib/extensions/pmuv3.h> 34 #include <lib/extensions/sme.h> 35 #include <lib/extensions/spe.h> 36 #include <lib/extensions/sve.h> 37 #include <lib/extensions/sysreg128.h> 38 #include <lib/extensions/sys_reg_trace.h> 39 #include <lib/extensions/tcr2.h> 40 #include <lib/extensions/trbe.h> 41 #include <lib/extensions/trf.h> 42 #include <lib/utils.h> 43 44 #if ENABLE_FEAT_TWED 45 /* Make sure delay value fits within the range(0-15) */ 46 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check); 47 #endif /* ENABLE_FEAT_TWED */ 48 49 per_world_context_t per_world_context[CPU_DATA_CONTEXT_NUM]; 50 static bool has_secure_perworld_init; 51 52 static void manage_extensions_nonsecure(cpu_context_t *ctx); 53 static void manage_extensions_secure(cpu_context_t *ctx); 54 static void manage_extensions_secure_per_world(void); 55 56 #if ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) 57 static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep) 58 { 59 u_register_t sctlr_elx, actlr_elx; 60 61 /* 62 * Initialise SCTLR_EL1 to the reset value corresponding to the target 63 * execution state setting all fields rather than relying on the hw. 64 * Some fields have architecturally UNKNOWN reset values and these are 65 * set to zero. 66 * 67 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 68 * 69 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 70 * required by PSCI specification) 71 */ 72 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 73 if (GET_RW(ep->spsr) == MODE_RW_64) { 74 sctlr_elx |= SCTLR_EL1_RES1; 75 } else { 76 /* 77 * If the target execution state is AArch32 then the following 78 * fields need to be set. 79 * 80 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 81 * instructions are not trapped to EL1. 82 * 83 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 84 * instructions are not trapped to EL1. 85 * 86 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 87 * CP15DMB, CP15DSB, and CP15ISB instructions. 88 */ 89 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 90 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 91 } 92 93 /* 94 * If workaround of errata 764081 for Cortex-A75 is used then set 95 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 96 */ 97 if (errata_a75_764081_applies()) { 98 sctlr_elx |= SCTLR_IESB_BIT; 99 } 100 101 /* Store the initialised SCTLR_EL1 value in the cpu_context */ 102 write_ctx_sctlr_el1_reg_errata(ctx, sctlr_elx); 103 104 /* 105 * Base the context ACTLR_EL1 on the current value, as it is 106 * implementation defined. The context restore process will write 107 * the value from the context to the actual register and can cause 108 * problems for processor cores that don't expect certain bits to 109 * be zero. 110 */ 111 actlr_elx = read_actlr_el1(); 112 write_el1_ctx_common(get_el1_sysregs_ctx(ctx), actlr_el1, actlr_elx); 113 } 114 #endif /* (IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS)) */ 115 116 /****************************************************************************** 117 * This function performs initializations that are specific to SECURE state 118 * and updates the cpu context specified by 'ctx'. 119 *****************************************************************************/ 120 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep) 121 { 122 u_register_t scr_el3; 123 el3_state_t *state; 124 125 state = get_el3state_ctx(ctx); 126 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 127 128 #if defined(IMAGE_BL31) && !defined(SPD_spmd) 129 /* 130 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 131 * indicated by the interrupt routing model for BL31. 132 */ 133 scr_el3 |= get_scr_el3_from_routing_model(SECURE); 134 #endif 135 136 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 137 if (is_feat_mte2_supported()) { 138 scr_el3 |= SCR_ATA_BIT; 139 } 140 141 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 142 143 /* 144 * Initialize EL1 context registers unless SPMC is running 145 * at S-EL2. 146 */ 147 #if (!SPMD_SPM_AT_SEL2) 148 setup_el1_context(ctx, ep); 149 #endif 150 151 manage_extensions_secure(ctx); 152 153 /** 154 * manage_extensions_secure_per_world api has to be executed once, 155 * as the registers getting initialised, maintain constant value across 156 * all the cpus for the secure world. 157 * Henceforth, this check ensures that the registers are initialised once 158 * and avoids re-initialization from multiple cores. 159 */ 160 if (!has_secure_perworld_init) { 161 manage_extensions_secure_per_world(); 162 } 163 } 164 165 #if ENABLE_RME 166 /****************************************************************************** 167 * This function performs initializations that are specific to REALM state 168 * and updates the cpu context specified by 'ctx'. 169 *****************************************************************************/ 170 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep) 171 { 172 u_register_t scr_el3; 173 el3_state_t *state; 174 175 state = get_el3state_ctx(ctx); 176 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 177 178 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT; 179 180 /* CSV2 version 2 and above */ 181 if (is_feat_csv2_2_supported()) { 182 /* Enable access to the SCXTNUM_ELx registers. */ 183 scr_el3 |= SCR_EnSCXT_BIT; 184 } 185 186 if (is_feat_sctlr2_supported()) { 187 /* Set the SCTLR2En bit in SCR_EL3 to enable access to 188 * SCTLR2_ELx registers. 189 */ 190 scr_el3 |= SCR_SCTLR2En_BIT; 191 } 192 193 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 194 195 if (is_feat_fgt2_supported()) { 196 fgt2_enable(ctx); 197 } 198 199 if (is_feat_debugv8p9_supported()) { 200 debugv8p9_extended_bp_wp_enable(ctx); 201 } 202 203 if (is_feat_brbe_supported()) { 204 brbe_enable(ctx); 205 } 206 207 } 208 #endif /* ENABLE_RME */ 209 210 /****************************************************************************** 211 * This function performs initializations that are specific to NON-SECURE state 212 * and updates the cpu context specified by 'ctx'. 213 *****************************************************************************/ 214 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep) 215 { 216 u_register_t scr_el3; 217 el3_state_t *state; 218 219 state = get_el3state_ctx(ctx); 220 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 221 222 /* SCR_NS: Set the NS bit */ 223 scr_el3 |= SCR_NS_BIT; 224 225 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 226 if (is_feat_mte2_supported()) { 227 scr_el3 |= SCR_ATA_BIT; 228 } 229 230 #if !CTX_INCLUDE_PAUTH_REGS 231 /* 232 * Pointer Authentication feature, if present, is always enabled by default 233 * for Non secure lower exception levels. We do not have an explicit 234 * flag to set it. 235 * CTX_INCLUDE_PAUTH_REGS flag, is explicitly used to enable for lower 236 * exception levels of secure and realm worlds. 237 * 238 * To prevent the leakage between the worlds during world switch, 239 * we enable it only for the non-secure world. 240 * 241 * If the Secure/realm world wants to use pointer authentication, 242 * CTX_INCLUDE_PAUTH_REGS must be explicitly set to 1, in which case 243 * it will be enabled globally for all the contexts. 244 * 245 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 246 * other than EL3 247 * 248 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 249 * than EL3 250 */ 251 if (is_armv8_3_pauth_present()) { 252 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 253 } 254 #endif /* CTX_INCLUDE_PAUTH_REGS */ 255 256 #if HANDLE_EA_EL3_FIRST_NS 257 /* SCR_EL3.EA: Route External Abort and SError Interrupt to EL3. */ 258 scr_el3 |= SCR_EA_BIT; 259 #endif 260 261 #if RAS_TRAP_NS_ERR_REC_ACCESS 262 /* 263 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 264 * and RAS ERX registers from EL1 and EL2(from any security state) 265 * are trapped to EL3. 266 * Set here to trap only for NS EL1/EL2 267 */ 268 scr_el3 |= SCR_TERR_BIT; 269 #endif 270 271 /* CSV2 version 2 and above */ 272 if (is_feat_csv2_2_supported()) { 273 /* Enable access to the SCXTNUM_ELx registers. */ 274 scr_el3 |= SCR_EnSCXT_BIT; 275 } 276 277 #ifdef IMAGE_BL31 278 /* 279 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 280 * indicated by the interrupt routing model for BL31. 281 */ 282 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE); 283 #endif 284 285 if (is_feat_the_supported()) { 286 /* Set the RCWMASKEn bit in SCR_EL3 to enable access to 287 * RCWMASK_EL1 and RCWSMASK_EL1 registers. 288 */ 289 scr_el3 |= SCR_RCWMASKEn_BIT; 290 } 291 292 if (is_feat_sctlr2_supported()) { 293 /* Set the SCTLR2En bit in SCR_EL3 to enable access to 294 * SCTLR2_ELx registers. 295 */ 296 scr_el3 |= SCR_SCTLR2En_BIT; 297 } 298 299 if (is_feat_d128_supported()) { 300 /* Set the D128En bit in SCR_EL3 to enable access to 128-bit 301 * versions of TTBR0_EL1, TTBR1_EL1, RCWMASK_EL1, RCWSMASK_EL1, 302 * PAR_EL1 and TTBR1_EL2, TTBR0_EL2 and VTTBR_EL2 registers. 303 */ 304 scr_el3 |= SCR_D128En_BIT; 305 } 306 307 if (is_feat_fpmr_supported()) { 308 /* Set the EnFPM bit in SCR_EL3 to enable access to FPMR 309 * register. 310 */ 311 scr_el3 |= SCR_EnFPM_BIT; 312 } 313 314 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 315 316 /* Initialize EL2 context registers */ 317 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 318 319 /* 320 * Initialize SCTLR_EL2 context register with reset value. 321 */ 322 write_el2_ctx_common(get_el2_sysregs_ctx(ctx), sctlr_el2, SCTLR_EL2_RES1); 323 324 if (is_feat_hcx_supported()) { 325 /* 326 * Initialize register HCRX_EL2 with its init value. 327 * As the value of HCRX_EL2 is UNKNOWN on reset, there is a 328 * chance that this can lead to unexpected behavior in lower 329 * ELs that have not been updated since the introduction of 330 * this feature if not properly initialized, especially when 331 * it comes to those bits that enable/disable traps. 332 */ 333 write_el2_ctx_hcx(get_el2_sysregs_ctx(ctx), hcrx_el2, 334 HCRX_EL2_INIT_VAL); 335 } 336 337 if (is_feat_fgt_supported()) { 338 /* 339 * Initialize HFG*_EL2 registers with a default value so legacy 340 * systems unaware of FEAT_FGT do not get trapped due to their lack 341 * of initialization for this feature. 342 */ 343 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgitr_el2, 344 HFGITR_EL2_INIT_VAL); 345 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgrtr_el2, 346 HFGRTR_EL2_INIT_VAL); 347 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgwtr_el2, 348 HFGWTR_EL2_INIT_VAL); 349 } 350 #else 351 /* Initialize EL1 context registers */ 352 setup_el1_context(ctx, ep); 353 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 354 355 manage_extensions_nonsecure(ctx); 356 } 357 358 /******************************************************************************* 359 * The following function performs initialization of the cpu_context 'ctx' 360 * for first use that is common to all security states, and sets the 361 * initial entrypoint state as specified by the entry_point_info structure. 362 * 363 * The EE and ST attributes are used to configure the endianness and secure 364 * timer availability for the new execution context. 365 ******************************************************************************/ 366 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 367 { 368 u_register_t scr_el3; 369 u_register_t mdcr_el3; 370 el3_state_t *state; 371 gp_regs_t *gp_regs; 372 373 state = get_el3state_ctx(ctx); 374 375 /* Clear any residual register values from the context */ 376 zeromem(ctx, sizeof(*ctx)); 377 378 /* 379 * The lower-EL context is zeroed so that no stale values leak to a world. 380 * It is assumed that an all-zero lower-EL context is good enough for it 381 * to boot correctly. However, there are very few registers where this 382 * is not true and some values need to be recreated. 383 */ 384 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 385 el2_sysregs_t *el2_ctx = get_el2_sysregs_ctx(ctx); 386 387 /* 388 * These bits are set in the gicv3 driver. Losing them (especially the 389 * SRE bit) is problematic for all worlds. Henceforth recreate them. 390 */ 391 u_register_t icc_sre_el2_val = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | 392 ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT; 393 write_el2_ctx_common(el2_ctx, icc_sre_el2, icc_sre_el2_val); 394 395 /* 396 * The actlr_el2 register can be initialized in platform's reset handler 397 * and it may contain access control bits (e.g. CLUSTERPMUEN bit). 398 */ 399 write_el2_ctx_common(el2_ctx, actlr_el2, read_actlr_el2()); 400 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 401 402 /* Start with a clean SCR_EL3 copy as all relevant values are set */ 403 scr_el3 = SCR_RESET_VAL; 404 405 /* 406 * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at 407 * EL2, EL1 and EL0 are not trapped to EL3. 408 * 409 * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at 410 * EL2, EL1 and EL0 are not trapped to EL3. 411 * 412 * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from 413 * both Security states and both Execution states. 414 * 415 * SCR_EL3.SIF: Set to one to disable secure instruction execution from 416 * Non-secure memory. 417 */ 418 scr_el3 &= ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT); 419 420 scr_el3 |= SCR_SIF_BIT; 421 422 /* 423 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 424 * Exception level as specified by SPSR. 425 */ 426 if (GET_RW(ep->spsr) == MODE_RW_64) { 427 scr_el3 |= SCR_RW_BIT; 428 } 429 430 /* 431 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 432 * Secure timer registers to EL3, from AArch64 state only, if specified 433 * by the entrypoint attributes. If SEL2 is present and enabled, the ST 434 * bit always behaves as 1 (i.e. secure physical timer register access 435 * is not trapped) 436 */ 437 if (EP_GET_ST(ep->h.attr) != 0U) { 438 scr_el3 |= SCR_ST_BIT; 439 } 440 441 /* 442 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting 443 * SCR_EL3.HXEn. 444 */ 445 if (is_feat_hcx_supported()) { 446 scr_el3 |= SCR_HXEn_BIT; 447 } 448 449 /* 450 * If FEAT_LS64_ACCDATA is enabled, enable access to ACCDATA_EL1 by 451 * setting SCR_EL3.ADEn and allow the ST64BV0 instruction by setting 452 * SCR_EL3.EnAS0. 453 */ 454 if (is_feat_ls64_accdata_supported()) { 455 scr_el3 |= SCR_ADEn_BIT | SCR_EnAS0_BIT; 456 } 457 458 /* 459 * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS 460 * registers are trapped to EL3. 461 */ 462 if (is_feat_rng_trap_supported()) { 463 scr_el3 |= SCR_TRNDR_BIT; 464 } 465 466 #if FAULT_INJECTION_SUPPORT 467 /* Enable fault injection from lower ELs */ 468 scr_el3 |= SCR_FIEN_BIT; 469 #endif 470 471 #if CTX_INCLUDE_PAUTH_REGS 472 /* 473 * Enable Pointer Authentication globally for all the worlds. 474 * 475 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 476 * other than EL3 477 * 478 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 479 * than EL3 480 */ 481 if (is_armv8_3_pauth_present()) { 482 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 483 } 484 #endif /* CTX_INCLUDE_PAUTH_REGS */ 485 486 /* 487 * SCR_EL3.TCR2EN: Enable access to TCR2_ELx for AArch64 if present. 488 */ 489 if (is_feat_tcr2_supported() && (GET_RW(ep->spsr) == MODE_RW_64)) { 490 scr_el3 |= SCR_TCR2EN_BIT; 491 } 492 493 /* 494 * SCR_EL3.PIEN: Enable permission indirection and overlay 495 * registers for AArch64 if present. 496 */ 497 if (is_feat_sxpie_supported() || is_feat_sxpoe_supported()) { 498 scr_el3 |= SCR_PIEN_BIT; 499 } 500 501 /* 502 * SCR_EL3.GCSEn: Enable GCS registers for AArch64 if present. 503 */ 504 if ((is_feat_gcs_supported()) && (GET_RW(ep->spsr) == MODE_RW_64)) { 505 scr_el3 |= SCR_GCSEn_BIT; 506 } 507 508 /* 509 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 510 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 511 * next mode is Hyp. 512 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 513 * same conditions as HVC instructions and when the processor supports 514 * ARMv8.6-FGT. 515 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 516 * CNTPOFF_EL2 register under the same conditions as HVC instructions 517 * and when the processor supports ECV. 518 */ 519 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 520 || ((GET_RW(ep->spsr) != MODE_RW_64) 521 && (GET_M32(ep->spsr) == MODE32_hyp))) { 522 scr_el3 |= SCR_HCE_BIT; 523 524 if (is_feat_fgt_supported()) { 525 scr_el3 |= SCR_FGTEN_BIT; 526 } 527 528 if (is_feat_ecv_supported()) { 529 scr_el3 |= SCR_ECVEN_BIT; 530 } 531 } 532 533 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 534 if (is_feat_twed_supported()) { 535 /* Set delay in SCR_EL3 */ 536 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 537 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK) 538 << SCR_TWEDEL_SHIFT); 539 540 /* Enable WFE delay */ 541 scr_el3 |= SCR_TWEDEn_BIT; 542 } 543 544 #if IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2 545 /* Enable S-EL2 if FEAT_SEL2 is implemented for all the contexts. */ 546 if (is_feat_sel2_supported()) { 547 scr_el3 |= SCR_EEL2_BIT; 548 } 549 #endif /* (IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2) */ 550 551 if (is_feat_mec_supported()) { 552 scr_el3 |= SCR_MECEn_BIT; 553 } 554 555 /* 556 * Populate EL3 state so that we've the right context 557 * before doing ERET 558 */ 559 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 560 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 561 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 562 563 /* Start with a clean MDCR_EL3 copy as all relevant values are set */ 564 mdcr_el3 = MDCR_EL3_RESET_VAL; 565 566 /* --------------------------------------------------------------------- 567 * Initialise MDCR_EL3, setting all fields rather than relying on hw. 568 * Some fields are architecturally UNKNOWN on reset. 569 * 570 * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug. 571 * Debug exceptions, other than Breakpoint Instruction exceptions, are 572 * disabled from all ELs in Secure state. 573 * 574 * MDCR_EL3.SPD32: Set to 0b10 to disable AArch32 Secure self-hosted 575 * privileged debug from S-EL1. 576 * 577 * MDCR_EL3.TDOSA: Set to zero so that EL2 and EL2 System register 578 * access to the powerdown debug registers do not trap to EL3. 579 * 580 * MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the 581 * debug registers, other than those registers that are controlled by 582 * MDCR_EL3.TDOSA. 583 */ 584 mdcr_el3 |= ((MDCR_SDD_BIT | MDCR_SPD32(MDCR_SPD32_DISABLE)) 585 & ~(MDCR_TDA_BIT | MDCR_TDOSA_BIT)) ; 586 write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3); 587 588 #if IMAGE_BL31 589 /* Enable FEAT_TRF for Non-Secure and prohibit for Secure state. */ 590 if (is_feat_trf_supported()) { 591 trf_enable(ctx); 592 } 593 594 pmuv3_enable(ctx); 595 #endif /* IMAGE_BL31 */ 596 597 /* 598 * Store the X0-X7 value from the entrypoint into the context 599 * Use memcpy as we are in control of the layout of the structures 600 */ 601 gp_regs = get_gpregs_ctx(ctx); 602 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 603 } 604 605 /******************************************************************************* 606 * Context management library initialization routine. This library is used by 607 * runtime services to share pointers to 'cpu_context' structures for secure 608 * non-secure and realm states. Management of the structures and their associated 609 * memory is not done by the context management library e.g. the PSCI service 610 * manages the cpu context used for entry from and exit to the non-secure state. 611 * The Secure payload dispatcher service manages the context(s) corresponding to 612 * the secure state. It also uses this library to get access to the non-secure 613 * state cpu context pointers. 614 * Lastly, this library provides the API to make SP_EL3 point to the cpu context 615 * which will be used for programming an entry into a lower EL. The same context 616 * will be used to save state upon exception entry from that EL. 617 ******************************************************************************/ 618 void __init cm_init(void) 619 { 620 /* 621 * The context management library has only global data to initialize, but 622 * that will be done when the BSS is zeroed out. 623 */ 624 } 625 626 /******************************************************************************* 627 * This is the high-level function used to initialize the cpu_context 'ctx' for 628 * first use. It performs initializations that are common to all security states 629 * and initializations specific to the security state specified in 'ep' 630 ******************************************************************************/ 631 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 632 { 633 unsigned int security_state; 634 635 assert(ctx != NULL); 636 637 /* 638 * Perform initializations that are common 639 * to all security states 640 */ 641 setup_context_common(ctx, ep); 642 643 security_state = GET_SECURITY_STATE(ep->h.attr); 644 645 /* Perform security state specific initializations */ 646 switch (security_state) { 647 case SECURE: 648 setup_secure_context(ctx, ep); 649 break; 650 #if ENABLE_RME 651 case REALM: 652 setup_realm_context(ctx, ep); 653 break; 654 #endif 655 case NON_SECURE: 656 setup_ns_context(ctx, ep); 657 break; 658 default: 659 ERROR("Invalid security state\n"); 660 panic(); 661 break; 662 } 663 } 664 665 /******************************************************************************* 666 * Enable architecture extensions for EL3 execution. This function only updates 667 * registers in-place which are expected to either never change or be 668 * overwritten by el3_exit. Expects the core_pos of the current core as argument. 669 ******************************************************************************/ 670 #if IMAGE_BL31 671 void cm_manage_extensions_el3(unsigned int my_idx) 672 { 673 if (is_feat_sve_supported()) { 674 sve_init_el3(); 675 } 676 677 if (is_feat_amu_supported()) { 678 amu_init_el3(my_idx); 679 } 680 681 if (is_feat_sme_supported()) { 682 sme_init_el3(); 683 } 684 685 pmuv3_init_el3(); 686 } 687 #endif /* IMAGE_BL31 */ 688 689 /****************************************************************************** 690 * Function to initialise the registers with the RESET values in the context 691 * memory, which are maintained per world. 692 ******************************************************************************/ 693 #if IMAGE_BL31 694 void cm_el3_arch_init_per_world(per_world_context_t *per_world_ctx) 695 { 696 /* 697 * Initialise CPTR_EL3, setting all fields rather than relying on hw. 698 * 699 * CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers 700 * by Advanced SIMD, floating-point or SVE instructions (if 701 * implemented) do not trap to EL3. 702 * 703 * CPTR_EL3.TCPAC: Set to zero so that accesses to CPACR_EL1, 704 * CPTR_EL2,CPACR, or HCPTR do not trap to EL3. 705 */ 706 uint64_t cptr_el3 = CPTR_EL3_RESET_VAL & ~(TCPAC_BIT | TFP_BIT); 707 708 per_world_ctx->ctx_cptr_el3 = cptr_el3; 709 710 /* 711 * Initialize MPAM3_EL3 to its default reset value 712 * 713 * MPAM3_EL3_RESET_VAL sets the MPAM3_EL3.TRAPLOWER bit that forces 714 * all lower ELn MPAM3_EL3 register access to, trap to EL3 715 */ 716 717 per_world_ctx->ctx_mpam3_el3 = MPAM3_EL3_RESET_VAL; 718 } 719 #endif /* IMAGE_BL31 */ 720 721 /******************************************************************************* 722 * Initialise per_world_context for Non-Secure world. 723 * This function enables the architecture extensions, which have same value 724 * across the cores for the non-secure world. 725 ******************************************************************************/ 726 #if IMAGE_BL31 727 void manage_extensions_nonsecure_per_world(void) 728 { 729 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_NS]); 730 731 if (is_feat_sme_supported()) { 732 sme_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 733 } 734 735 if (is_feat_sve_supported()) { 736 sve_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 737 } 738 739 if (is_feat_amu_supported()) { 740 amu_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 741 } 742 743 if (is_feat_sys_reg_trace_supported()) { 744 sys_reg_trace_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 745 } 746 747 if (is_feat_mpam_supported()) { 748 mpam_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 749 } 750 751 if (is_feat_fpmr_supported()) { 752 fpmr_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 753 } 754 } 755 #endif /* IMAGE_BL31 */ 756 757 /******************************************************************************* 758 * Initialise per_world_context for Secure world. 759 * This function enables the architecture extensions, which have same value 760 * across the cores for the secure world. 761 ******************************************************************************/ 762 static void manage_extensions_secure_per_world(void) 763 { 764 #if IMAGE_BL31 765 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 766 767 if (is_feat_sme_supported()) { 768 769 if (ENABLE_SME_FOR_SWD) { 770 /* 771 * Enable SME, SVE, FPU/SIMD in secure context, SPM must ensure 772 * SME, SVE, and FPU/SIMD context properly managed. 773 */ 774 sme_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 775 } else { 776 /* 777 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 778 * world can safely use the associated registers. 779 */ 780 sme_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 781 } 782 } 783 if (is_feat_sve_supported()) { 784 if (ENABLE_SVE_FOR_SWD) { 785 /* 786 * Enable SVE and FPU in secure context, SPM must ensure 787 * that the SVE and FPU register contexts are properly managed. 788 */ 789 sve_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 790 } else { 791 /* 792 * Disable SVE and FPU in secure context so non-secure world 793 * can safely use them. 794 */ 795 sve_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 796 } 797 } 798 799 /* NS can access this but Secure shouldn't */ 800 if (is_feat_sys_reg_trace_supported()) { 801 sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 802 } 803 804 has_secure_perworld_init = true; 805 #endif /* IMAGE_BL31 */ 806 } 807 808 /******************************************************************************* 809 * Enable architecture extensions on first entry to Non-secure world. 810 ******************************************************************************/ 811 static void manage_extensions_nonsecure(cpu_context_t *ctx) 812 { 813 #if IMAGE_BL31 814 /* NOTE: registers are not context switched */ 815 if (is_feat_amu_supported()) { 816 amu_enable(ctx); 817 } 818 819 if (is_feat_sme_supported()) { 820 sme_enable(ctx); 821 } 822 823 if (is_feat_fgt2_supported()) { 824 fgt2_enable(ctx); 825 } 826 827 if (is_feat_debugv8p9_supported()) { 828 debugv8p9_extended_bp_wp_enable(ctx); 829 } 830 831 /* 832 * SPE, TRBE, and BRBE have multi-field enables that affect which world 833 * they apply to. Despite this, it is useful to ignore these for 834 * simplicity in determining the feature's per world enablement status. 835 * This is only possible when context is written per-world. Relied on 836 * by SMCCC_ARCH_FEATURE_AVAILABILITY 837 */ 838 if (is_feat_spe_supported()) { 839 spe_enable(ctx); 840 } 841 842 if (is_feat_trbe_supported()) { 843 trbe_enable(ctx); 844 } 845 846 if (is_feat_brbe_supported()) { 847 brbe_enable(ctx); 848 } 849 #endif /* IMAGE_BL31 */ 850 } 851 852 /* TODO: move to lib/extensions/pauth when it has been ported to FEAT_STATE */ 853 static __unused void enable_pauth_el2(void) 854 { 855 u_register_t hcr_el2 = read_hcr_el2(); 856 /* 857 * For Armv8.3 pointer authentication feature, disable traps to EL2 when 858 * accessing key registers or using pointer authentication instructions 859 * from lower ELs. 860 */ 861 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 862 863 write_hcr_el2(hcr_el2); 864 } 865 866 #if INIT_UNUSED_NS_EL2 867 /******************************************************************************* 868 * Enable architecture extensions in-place at EL2 on first entry to Non-secure 869 * world when EL2 is empty and unused. 870 ******************************************************************************/ 871 static void manage_extensions_nonsecure_el2_unused(void) 872 { 873 #if IMAGE_BL31 874 if (is_feat_spe_supported()) { 875 spe_init_el2_unused(); 876 } 877 878 if (is_feat_amu_supported()) { 879 amu_init_el2_unused(); 880 } 881 882 if (is_feat_mpam_supported()) { 883 mpam_init_el2_unused(); 884 } 885 886 if (is_feat_trbe_supported()) { 887 trbe_init_el2_unused(); 888 } 889 890 if (is_feat_sys_reg_trace_supported()) { 891 sys_reg_trace_init_el2_unused(); 892 } 893 894 if (is_feat_trf_supported()) { 895 trf_init_el2_unused(); 896 } 897 898 pmuv3_init_el2_unused(); 899 900 if (is_feat_sve_supported()) { 901 sve_init_el2_unused(); 902 } 903 904 if (is_feat_sme_supported()) { 905 sme_init_el2_unused(); 906 } 907 908 if (is_feat_mops_supported()) { 909 write_hcrx_el2(read_hcrx_el2() | HCRX_EL2_MSCEn_BIT); 910 } 911 912 #if ENABLE_PAUTH 913 enable_pauth_el2(); 914 #endif /* ENABLE_PAUTH */ 915 #endif /* IMAGE_BL31 */ 916 } 917 #endif /* INIT_UNUSED_NS_EL2 */ 918 919 /******************************************************************************* 920 * Enable architecture extensions on first entry to Secure world. 921 ******************************************************************************/ 922 static void manage_extensions_secure(cpu_context_t *ctx) 923 { 924 #if IMAGE_BL31 925 if (is_feat_sme_supported()) { 926 if (ENABLE_SME_FOR_SWD) { 927 /* 928 * Enable SME, SVE, FPU/SIMD in secure context, secure manager 929 * must ensure SME, SVE, and FPU/SIMD context properly managed. 930 */ 931 sme_init_el3(); 932 sme_enable(ctx); 933 } else { 934 /* 935 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 936 * world can safely use the associated registers. 937 */ 938 sme_disable(ctx); 939 } 940 } 941 942 /* 943 * SPE and TRBE cannot be fully disabled from EL3 registers alone, only 944 * sysreg access can. In case the EL1 controls leave them active on 945 * context switch, we want the owning security state to be NS so Secure 946 * can't be DOSed. 947 */ 948 if (is_feat_spe_supported()) { 949 spe_disable(ctx); 950 } 951 952 if (is_feat_trbe_supported()) { 953 trbe_disable(ctx); 954 } 955 #endif /* IMAGE_BL31 */ 956 } 957 958 #if !IMAGE_BL1 959 /******************************************************************************* 960 * The following function initializes the cpu_context for a CPU specified by 961 * its `cpu_idx` for first use, and sets the initial entrypoint state as 962 * specified by the entry_point_info structure. 963 ******************************************************************************/ 964 void cm_init_context_by_index(unsigned int cpu_idx, 965 const entry_point_info_t *ep) 966 { 967 cpu_context_t *ctx; 968 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 969 cm_setup_context(ctx, ep); 970 } 971 #endif /* !IMAGE_BL1 */ 972 973 /******************************************************************************* 974 * The following function initializes the cpu_context for the current CPU 975 * for first use, and sets the initial entrypoint state as specified by the 976 * entry_point_info structure. 977 ******************************************************************************/ 978 void cm_init_my_context(const entry_point_info_t *ep) 979 { 980 cpu_context_t *ctx; 981 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 982 cm_setup_context(ctx, ep); 983 } 984 985 /* EL2 present but unused, need to disable safely. SCTLR_EL2 can be ignored */ 986 static void init_nonsecure_el2_unused(cpu_context_t *ctx) 987 { 988 #if INIT_UNUSED_NS_EL2 989 u_register_t hcr_el2 = HCR_RESET_VAL; 990 u_register_t mdcr_el2; 991 u_register_t scr_el3; 992 993 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 994 995 /* Set EL2 register width: Set HCR_EL2.RW to match SCR_EL3.RW */ 996 if ((scr_el3 & SCR_RW_BIT) != 0U) { 997 hcr_el2 |= HCR_RW_BIT; 998 } 999 1000 write_hcr_el2(hcr_el2); 1001 1002 /* 1003 * Initialise CPTR_EL2 setting all fields rather than relying on the hw. 1004 * All fields have architecturally UNKNOWN reset values. 1005 */ 1006 write_cptr_el2(CPTR_EL2_RESET_VAL); 1007 1008 /* 1009 * Initialise CNTHCTL_EL2. All fields are architecturally UNKNOWN on 1010 * reset and are set to zero except for field(s) listed below. 1011 * 1012 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to Hyp mode of 1013 * Non-secure EL0 and EL1 accesses to the physical timer registers. 1014 * 1015 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to Hyp mode of 1016 * Non-secure EL0 and EL1 accesses to the physical counter registers. 1017 */ 1018 write_cnthctl_el2(CNTHCTL_RESET_VAL | EL1PCEN_BIT | EL1PCTEN_BIT); 1019 1020 /* 1021 * Initialise CNTVOFF_EL2 to zero as it resets to an architecturally 1022 * UNKNOWN value. 1023 */ 1024 write_cntvoff_el2(0); 1025 1026 /* 1027 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and MPIDR_EL1 1028 * respectively. 1029 */ 1030 write_vpidr_el2(read_midr_el1()); 1031 write_vmpidr_el2(read_mpidr_el1()); 1032 1033 /* 1034 * Initialise VTTBR_EL2. All fields are architecturally UNKNOWN on reset. 1035 * 1036 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 2 address 1037 * translation is disabled, cache maintenance operations depend on the 1038 * VMID. 1039 * 1040 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address translation is 1041 * disabled. 1042 */ 1043 write_vttbr_el2(VTTBR_RESET_VAL & 1044 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) | 1045 (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 1046 1047 /* 1048 * Initialise MDCR_EL2, setting all fields rather than relying on hw. 1049 * Some fields are architecturally UNKNOWN on reset. 1050 * 1051 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and EL1 System 1052 * register accesses to the Debug ROM registers are not trapped to EL2. 1053 * 1054 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 System register 1055 * accesses to the powerdown debug registers are not trapped to EL2. 1056 * 1057 * MDCR_EL2.TDA: Set to zero so that System register accesses to the 1058 * debug registers do not trap to EL2. 1059 * 1060 * MDCR_EL2.TDE: Set to zero so that debug exceptions are not routed to 1061 * EL2. 1062 */ 1063 mdcr_el2 = MDCR_EL2_RESET_VAL & 1064 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | MDCR_EL2_TDA_BIT | 1065 MDCR_EL2_TDE_BIT); 1066 1067 write_mdcr_el2(mdcr_el2); 1068 1069 /* 1070 * Initialise HSTR_EL2. All fields are architecturally UNKNOWN on reset. 1071 * 1072 * HSTR_EL2.T<n>: Set all these fields to zero so that Non-secure EL0 or 1073 * EL1 accesses to System registers do not trap to EL2. 1074 */ 1075 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 1076 1077 /* 1078 * Initialise CNTHP_CTL_EL2. All fields are architecturally UNKNOWN on 1079 * reset. 1080 * 1081 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 physical timer 1082 * and prevent timer interrupts. 1083 */ 1084 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & ~(CNTHP_CTL_ENABLE_BIT)); 1085 1086 manage_extensions_nonsecure_el2_unused(); 1087 #endif /* INIT_UNUSED_NS_EL2 */ 1088 } 1089 1090 /******************************************************************************* 1091 * Prepare the CPU system registers for first entry into realm, secure, or 1092 * normal world. 1093 * 1094 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 1095 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 1096 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 1097 * For all entries, the EL1 registers are initialized from the cpu_context 1098 ******************************************************************************/ 1099 void cm_prepare_el3_exit(uint32_t security_state) 1100 { 1101 u_register_t sctlr_el2, scr_el3; 1102 cpu_context_t *ctx = cm_get_context(security_state); 1103 1104 assert(ctx != NULL); 1105 1106 if (security_state == NON_SECURE) { 1107 uint64_t el2_implemented = el_implemented(2); 1108 1109 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 1110 CTX_SCR_EL3); 1111 1112 if (el2_implemented != EL_IMPL_NONE) { 1113 1114 /* 1115 * If context is not being used for EL2, initialize 1116 * HCRX_EL2 with its init value here. 1117 */ 1118 if (is_feat_hcx_supported()) { 1119 write_hcrx_el2(HCRX_EL2_INIT_VAL); 1120 } 1121 1122 /* 1123 * Initialize Fine-grained trap registers introduced 1124 * by FEAT_FGT so all traps are initially disabled when 1125 * switching to EL2 or a lower EL, preventing undesired 1126 * behavior. 1127 */ 1128 if (is_feat_fgt_supported()) { 1129 /* 1130 * Initialize HFG*_EL2 registers with a default 1131 * value so legacy systems unaware of FEAT_FGT 1132 * do not get trapped due to their lack of 1133 * initialization for this feature. 1134 */ 1135 write_hfgitr_el2(HFGITR_EL2_INIT_VAL); 1136 write_hfgrtr_el2(HFGRTR_EL2_INIT_VAL); 1137 write_hfgwtr_el2(HFGWTR_EL2_INIT_VAL); 1138 } 1139 1140 /* Condition to ensure EL2 is being used. */ 1141 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 1142 /* Initialize SCTLR_EL2 register with reset value. */ 1143 sctlr_el2 = SCTLR_EL2_RES1; 1144 1145 /* 1146 * If workaround of errata 764081 for Cortex-A75 1147 * is used then set SCTLR_EL2.IESB to enable 1148 * Implicit Error Synchronization Barrier. 1149 */ 1150 if (errata_a75_764081_applies()) { 1151 sctlr_el2 |= SCTLR_IESB_BIT; 1152 } 1153 1154 write_sctlr_el2(sctlr_el2); 1155 } else { 1156 /* 1157 * (scr_el3 & SCR_HCE_BIT==0) 1158 * EL2 implemented but unused. 1159 */ 1160 init_nonsecure_el2_unused(ctx); 1161 } 1162 } 1163 } 1164 #if (!CTX_INCLUDE_EL2_REGS) 1165 /* Restore EL1 system registers, only when CTX_INCLUDE_EL2_REGS=0 */ 1166 cm_el1_sysregs_context_restore(security_state); 1167 #endif 1168 cm_set_next_eret_context(security_state); 1169 } 1170 1171 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 1172 1173 static void el2_sysregs_context_save_fgt(el2_sysregs_t *ctx) 1174 { 1175 write_el2_ctx_fgt(ctx, hdfgrtr_el2, read_hdfgrtr_el2()); 1176 if (is_feat_amu_supported()) { 1177 write_el2_ctx_fgt(ctx, hafgrtr_el2, read_hafgrtr_el2()); 1178 } 1179 write_el2_ctx_fgt(ctx, hdfgwtr_el2, read_hdfgwtr_el2()); 1180 write_el2_ctx_fgt(ctx, hfgitr_el2, read_hfgitr_el2()); 1181 write_el2_ctx_fgt(ctx, hfgrtr_el2, read_hfgrtr_el2()); 1182 write_el2_ctx_fgt(ctx, hfgwtr_el2, read_hfgwtr_el2()); 1183 } 1184 1185 static void el2_sysregs_context_restore_fgt(el2_sysregs_t *ctx) 1186 { 1187 write_hdfgrtr_el2(read_el2_ctx_fgt(ctx, hdfgrtr_el2)); 1188 if (is_feat_amu_supported()) { 1189 write_hafgrtr_el2(read_el2_ctx_fgt(ctx, hafgrtr_el2)); 1190 } 1191 write_hdfgwtr_el2(read_el2_ctx_fgt(ctx, hdfgwtr_el2)); 1192 write_hfgitr_el2(read_el2_ctx_fgt(ctx, hfgitr_el2)); 1193 write_hfgrtr_el2(read_el2_ctx_fgt(ctx, hfgrtr_el2)); 1194 write_hfgwtr_el2(read_el2_ctx_fgt(ctx, hfgwtr_el2)); 1195 } 1196 1197 static void el2_sysregs_context_save_fgt2(el2_sysregs_t *ctx) 1198 { 1199 write_el2_ctx_fgt2(ctx, hdfgrtr2_el2, read_hdfgrtr2_el2()); 1200 write_el2_ctx_fgt2(ctx, hdfgwtr2_el2, read_hdfgwtr2_el2()); 1201 write_el2_ctx_fgt2(ctx, hfgitr2_el2, read_hfgitr2_el2()); 1202 write_el2_ctx_fgt2(ctx, hfgrtr2_el2, read_hfgrtr2_el2()); 1203 write_el2_ctx_fgt2(ctx, hfgwtr2_el2, read_hfgwtr2_el2()); 1204 } 1205 1206 static void el2_sysregs_context_restore_fgt2(el2_sysregs_t *ctx) 1207 { 1208 write_hdfgrtr2_el2(read_el2_ctx_fgt2(ctx, hdfgrtr2_el2)); 1209 write_hdfgwtr2_el2(read_el2_ctx_fgt2(ctx, hdfgwtr2_el2)); 1210 write_hfgitr2_el2(read_el2_ctx_fgt2(ctx, hfgitr2_el2)); 1211 write_hfgrtr2_el2(read_el2_ctx_fgt2(ctx, hfgrtr2_el2)); 1212 write_hfgwtr2_el2(read_el2_ctx_fgt2(ctx, hfgwtr2_el2)); 1213 } 1214 1215 static void el2_sysregs_context_save_mpam(el2_sysregs_t *ctx) 1216 { 1217 u_register_t mpam_idr = read_mpamidr_el1(); 1218 1219 write_el2_ctx_mpam(ctx, mpam2_el2, read_mpam2_el2()); 1220 1221 /* 1222 * The context registers that we intend to save would be part of the 1223 * PE's system register frame only if MPAMIDR_EL1.HAS_HCR == 1. 1224 */ 1225 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1226 return; 1227 } 1228 1229 /* 1230 * MPAMHCR_EL2, MPAMVPMV_EL2 and MPAMVPM0_EL2 are always present if 1231 * MPAMIDR_HAS_HCR_BIT == 1. 1232 */ 1233 write_el2_ctx_mpam(ctx, mpamhcr_el2, read_mpamhcr_el2()); 1234 write_el2_ctx_mpam(ctx, mpamvpm0_el2, read_mpamvpm0_el2()); 1235 write_el2_ctx_mpam(ctx, mpamvpmv_el2, read_mpamvpmv_el2()); 1236 1237 /* 1238 * The number of MPAMVPM registers is implementation defined, their 1239 * number is stored in the MPAMIDR_EL1 register. 1240 */ 1241 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1242 case 7: 1243 write_el2_ctx_mpam(ctx, mpamvpm7_el2, read_mpamvpm7_el2()); 1244 __fallthrough; 1245 case 6: 1246 write_el2_ctx_mpam(ctx, mpamvpm6_el2, read_mpamvpm6_el2()); 1247 __fallthrough; 1248 case 5: 1249 write_el2_ctx_mpam(ctx, mpamvpm5_el2, read_mpamvpm5_el2()); 1250 __fallthrough; 1251 case 4: 1252 write_el2_ctx_mpam(ctx, mpamvpm4_el2, read_mpamvpm4_el2()); 1253 __fallthrough; 1254 case 3: 1255 write_el2_ctx_mpam(ctx, mpamvpm3_el2, read_mpamvpm3_el2()); 1256 __fallthrough; 1257 case 2: 1258 write_el2_ctx_mpam(ctx, mpamvpm2_el2, read_mpamvpm2_el2()); 1259 __fallthrough; 1260 case 1: 1261 write_el2_ctx_mpam(ctx, mpamvpm1_el2, read_mpamvpm1_el2()); 1262 break; 1263 } 1264 } 1265 1266 static void el2_sysregs_context_restore_mpam(el2_sysregs_t *ctx) 1267 { 1268 u_register_t mpam_idr = read_mpamidr_el1(); 1269 1270 write_mpam2_el2(read_el2_ctx_mpam(ctx, mpam2_el2)); 1271 1272 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1273 return; 1274 } 1275 1276 write_mpamhcr_el2(read_el2_ctx_mpam(ctx, mpamhcr_el2)); 1277 write_mpamvpm0_el2(read_el2_ctx_mpam(ctx, mpamvpm0_el2)); 1278 write_mpamvpmv_el2(read_el2_ctx_mpam(ctx, mpamvpmv_el2)); 1279 1280 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1281 case 7: 1282 write_mpamvpm7_el2(read_el2_ctx_mpam(ctx, mpamvpm7_el2)); 1283 __fallthrough; 1284 case 6: 1285 write_mpamvpm6_el2(read_el2_ctx_mpam(ctx, mpamvpm6_el2)); 1286 __fallthrough; 1287 case 5: 1288 write_mpamvpm5_el2(read_el2_ctx_mpam(ctx, mpamvpm5_el2)); 1289 __fallthrough; 1290 case 4: 1291 write_mpamvpm4_el2(read_el2_ctx_mpam(ctx, mpamvpm4_el2)); 1292 __fallthrough; 1293 case 3: 1294 write_mpamvpm3_el2(read_el2_ctx_mpam(ctx, mpamvpm3_el2)); 1295 __fallthrough; 1296 case 2: 1297 write_mpamvpm2_el2(read_el2_ctx_mpam(ctx, mpamvpm2_el2)); 1298 __fallthrough; 1299 case 1: 1300 write_mpamvpm1_el2(read_el2_ctx_mpam(ctx, mpamvpm1_el2)); 1301 break; 1302 } 1303 } 1304 1305 /* --------------------------------------------------------------------------- 1306 * The following registers are not added: 1307 * ICH_AP0R<n>_EL2 1308 * ICH_AP1R<n>_EL2 1309 * ICH_LR<n>_EL2 1310 * 1311 * NOTE: For a system with S-EL2 present but not enabled, accessing 1312 * ICC_SRE_EL2 is undefined from EL3. To workaround this change the 1313 * SCR_EL3.NS = 1 before accessing this register. 1314 * --------------------------------------------------------------------------- 1315 */ 1316 static void el2_sysregs_context_save_gic(el2_sysregs_t *ctx, uint32_t security_state) 1317 { 1318 u_register_t scr_el3 = read_scr_el3(); 1319 1320 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1321 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1322 #else 1323 write_scr_el3(scr_el3 | SCR_NS_BIT); 1324 isb(); 1325 1326 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1327 1328 write_scr_el3(scr_el3); 1329 isb(); 1330 #endif 1331 write_el2_ctx_common(ctx, ich_hcr_el2, read_ich_hcr_el2()); 1332 1333 if (errata_ich_vmcr_el2_applies()) { 1334 if (security_state == SECURE) { 1335 write_scr_el3(scr_el3 & ~SCR_NS_BIT); 1336 } else { 1337 write_scr_el3(scr_el3 | SCR_NS_BIT); 1338 } 1339 isb(); 1340 } 1341 1342 write_el2_ctx_common(ctx, ich_vmcr_el2, read_ich_vmcr_el2()); 1343 1344 if (errata_ich_vmcr_el2_applies()) { 1345 write_scr_el3(scr_el3); 1346 isb(); 1347 } 1348 } 1349 1350 static void el2_sysregs_context_restore_gic(el2_sysregs_t *ctx, uint32_t security_state) 1351 { 1352 u_register_t scr_el3 = read_scr_el3(); 1353 1354 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1355 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1356 #else 1357 write_scr_el3(scr_el3 | SCR_NS_BIT); 1358 isb(); 1359 1360 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1361 1362 write_scr_el3(scr_el3); 1363 isb(); 1364 #endif 1365 write_ich_hcr_el2(read_el2_ctx_common(ctx, ich_hcr_el2)); 1366 1367 if (errata_ich_vmcr_el2_applies()) { 1368 if (security_state == SECURE) { 1369 write_scr_el3(scr_el3 & ~SCR_NS_BIT); 1370 } else { 1371 write_scr_el3(scr_el3 | SCR_NS_BIT); 1372 } 1373 isb(); 1374 } 1375 1376 write_ich_vmcr_el2(read_el2_ctx_common(ctx, ich_vmcr_el2)); 1377 1378 if (errata_ich_vmcr_el2_applies()) { 1379 write_scr_el3(scr_el3); 1380 isb(); 1381 } 1382 } 1383 1384 /* ----------------------------------------------------- 1385 * The following registers are not added: 1386 * AMEVCNTVOFF0<n>_EL2 1387 * AMEVCNTVOFF1<n>_EL2 1388 * ----------------------------------------------------- 1389 */ 1390 static void el2_sysregs_context_save_common(el2_sysregs_t *ctx) 1391 { 1392 write_el2_ctx_common(ctx, actlr_el2, read_actlr_el2()); 1393 write_el2_ctx_common(ctx, afsr0_el2, read_afsr0_el2()); 1394 write_el2_ctx_common(ctx, afsr1_el2, read_afsr1_el2()); 1395 write_el2_ctx_common(ctx, amair_el2, read_amair_el2()); 1396 write_el2_ctx_common(ctx, cnthctl_el2, read_cnthctl_el2()); 1397 write_el2_ctx_common(ctx, cntvoff_el2, read_cntvoff_el2()); 1398 write_el2_ctx_common(ctx, cptr_el2, read_cptr_el2()); 1399 if (CTX_INCLUDE_AARCH32_REGS) { 1400 write_el2_ctx_common(ctx, dbgvcr32_el2, read_dbgvcr32_el2()); 1401 } 1402 write_el2_ctx_common(ctx, elr_el2, read_elr_el2()); 1403 write_el2_ctx_common(ctx, esr_el2, read_esr_el2()); 1404 write_el2_ctx_common(ctx, far_el2, read_far_el2()); 1405 write_el2_ctx_common(ctx, hacr_el2, read_hacr_el2()); 1406 write_el2_ctx_common(ctx, hcr_el2, read_hcr_el2()); 1407 write_el2_ctx_common(ctx, hpfar_el2, read_hpfar_el2()); 1408 write_el2_ctx_common(ctx, hstr_el2, read_hstr_el2()); 1409 write_el2_ctx_common(ctx, mair_el2, read_mair_el2()); 1410 write_el2_ctx_common(ctx, mdcr_el2, read_mdcr_el2()); 1411 write_el2_ctx_common(ctx, sctlr_el2, read_sctlr_el2()); 1412 write_el2_ctx_common(ctx, spsr_el2, read_spsr_el2()); 1413 write_el2_ctx_common(ctx, sp_el2, read_sp_el2()); 1414 write_el2_ctx_common(ctx, tcr_el2, read_tcr_el2()); 1415 write_el2_ctx_common(ctx, tpidr_el2, read_tpidr_el2()); 1416 write_el2_ctx_common(ctx, vbar_el2, read_vbar_el2()); 1417 write_el2_ctx_common(ctx, vmpidr_el2, read_vmpidr_el2()); 1418 write_el2_ctx_common(ctx, vpidr_el2, read_vpidr_el2()); 1419 write_el2_ctx_common(ctx, vtcr_el2, read_vtcr_el2()); 1420 1421 write_el2_ctx_common_sysreg128(ctx, ttbr0_el2, read_ttbr0_el2()); 1422 write_el2_ctx_common_sysreg128(ctx, vttbr_el2, read_vttbr_el2()); 1423 } 1424 1425 static void el2_sysregs_context_restore_common(el2_sysregs_t *ctx) 1426 { 1427 write_actlr_el2(read_el2_ctx_common(ctx, actlr_el2)); 1428 write_afsr0_el2(read_el2_ctx_common(ctx, afsr0_el2)); 1429 write_afsr1_el2(read_el2_ctx_common(ctx, afsr1_el2)); 1430 write_amair_el2(read_el2_ctx_common(ctx, amair_el2)); 1431 write_cnthctl_el2(read_el2_ctx_common(ctx, cnthctl_el2)); 1432 write_cntvoff_el2(read_el2_ctx_common(ctx, cntvoff_el2)); 1433 write_cptr_el2(read_el2_ctx_common(ctx, cptr_el2)); 1434 if (CTX_INCLUDE_AARCH32_REGS) { 1435 write_dbgvcr32_el2(read_el2_ctx_common(ctx, dbgvcr32_el2)); 1436 } 1437 write_elr_el2(read_el2_ctx_common(ctx, elr_el2)); 1438 write_esr_el2(read_el2_ctx_common(ctx, esr_el2)); 1439 write_far_el2(read_el2_ctx_common(ctx, far_el2)); 1440 write_hacr_el2(read_el2_ctx_common(ctx, hacr_el2)); 1441 write_hcr_el2(read_el2_ctx_common(ctx, hcr_el2)); 1442 write_hpfar_el2(read_el2_ctx_common(ctx, hpfar_el2)); 1443 write_hstr_el2(read_el2_ctx_common(ctx, hstr_el2)); 1444 write_mair_el2(read_el2_ctx_common(ctx, mair_el2)); 1445 write_mdcr_el2(read_el2_ctx_common(ctx, mdcr_el2)); 1446 write_sctlr_el2(read_el2_ctx_common(ctx, sctlr_el2)); 1447 write_spsr_el2(read_el2_ctx_common(ctx, spsr_el2)); 1448 write_sp_el2(read_el2_ctx_common(ctx, sp_el2)); 1449 write_tcr_el2(read_el2_ctx_common(ctx, tcr_el2)); 1450 write_tpidr_el2(read_el2_ctx_common(ctx, tpidr_el2)); 1451 write_ttbr0_el2(read_el2_ctx_common(ctx, ttbr0_el2)); 1452 write_vbar_el2(read_el2_ctx_common(ctx, vbar_el2)); 1453 write_vmpidr_el2(read_el2_ctx_common(ctx, vmpidr_el2)); 1454 write_vpidr_el2(read_el2_ctx_common(ctx, vpidr_el2)); 1455 write_vtcr_el2(read_el2_ctx_common(ctx, vtcr_el2)); 1456 write_vttbr_el2(read_el2_ctx_common(ctx, vttbr_el2)); 1457 } 1458 1459 /******************************************************************************* 1460 * Save EL2 sysreg context 1461 ******************************************************************************/ 1462 void cm_el2_sysregs_context_save(uint32_t security_state) 1463 { 1464 cpu_context_t *ctx; 1465 el2_sysregs_t *el2_sysregs_ctx; 1466 1467 ctx = cm_get_context(security_state); 1468 assert(ctx != NULL); 1469 1470 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1471 1472 el2_sysregs_context_save_common(el2_sysregs_ctx); 1473 el2_sysregs_context_save_gic(el2_sysregs_ctx, security_state); 1474 1475 if (is_feat_mte2_supported()) { 1476 write_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2, read_tfsr_el2()); 1477 } 1478 1479 if (is_feat_mpam_supported()) { 1480 el2_sysregs_context_save_mpam(el2_sysregs_ctx); 1481 } 1482 1483 if (is_feat_fgt_supported()) { 1484 el2_sysregs_context_save_fgt(el2_sysregs_ctx); 1485 } 1486 1487 if (is_feat_fgt2_supported()) { 1488 el2_sysregs_context_save_fgt2(el2_sysregs_ctx); 1489 } 1490 1491 if (is_feat_ecv_v2_supported()) { 1492 write_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2, read_cntpoff_el2()); 1493 } 1494 1495 if (is_feat_vhe_supported()) { 1496 write_el2_ctx_vhe(el2_sysregs_ctx, contextidr_el2, 1497 read_contextidr_el2()); 1498 write_el2_ctx_vhe_sysreg128(el2_sysregs_ctx, ttbr1_el2, read_ttbr1_el2()); 1499 } 1500 1501 if (is_feat_ras_supported()) { 1502 write_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2, read_vdisr_el2()); 1503 write_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2, read_vsesr_el2()); 1504 } 1505 1506 if (is_feat_nv2_supported()) { 1507 write_el2_ctx_neve(el2_sysregs_ctx, vncr_el2, read_vncr_el2()); 1508 } 1509 1510 if (is_feat_trf_supported()) { 1511 write_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2, read_trfcr_el2()); 1512 } 1513 1514 if (is_feat_csv2_2_supported()) { 1515 write_el2_ctx_csv2_2(el2_sysregs_ctx, scxtnum_el2, 1516 read_scxtnum_el2()); 1517 } 1518 1519 if (is_feat_hcx_supported()) { 1520 write_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2, read_hcrx_el2()); 1521 } 1522 1523 if (is_feat_tcr2_supported()) { 1524 write_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2, read_tcr2_el2()); 1525 } 1526 1527 if (is_feat_sxpie_supported()) { 1528 write_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2, read_pire0_el2()); 1529 write_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2, read_pir_el2()); 1530 } 1531 1532 if (is_feat_sxpoe_supported()) { 1533 write_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2, read_por_el2()); 1534 } 1535 1536 if (is_feat_brbe_supported()) { 1537 write_el2_ctx_brbe(el2_sysregs_ctx, brbcr_el2, read_brbcr_el2()); 1538 } 1539 1540 if (is_feat_s2pie_supported()) { 1541 write_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2, read_s2pir_el2()); 1542 } 1543 1544 if (is_feat_gcs_supported()) { 1545 write_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2, read_gcscr_el2()); 1546 write_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2, read_gcspr_el2()); 1547 } 1548 1549 if (is_feat_sctlr2_supported()) { 1550 write_el2_ctx_sctlr2(el2_sysregs_ctx, sctlr2_el2, read_sctlr2_el2()); 1551 } 1552 } 1553 1554 /******************************************************************************* 1555 * Restore EL2 sysreg context 1556 ******************************************************************************/ 1557 void cm_el2_sysregs_context_restore(uint32_t security_state) 1558 { 1559 cpu_context_t *ctx; 1560 el2_sysregs_t *el2_sysregs_ctx; 1561 1562 ctx = cm_get_context(security_state); 1563 assert(ctx != NULL); 1564 1565 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1566 1567 el2_sysregs_context_restore_common(el2_sysregs_ctx); 1568 el2_sysregs_context_restore_gic(el2_sysregs_ctx, security_state); 1569 1570 if (is_feat_mte2_supported()) { 1571 write_tfsr_el2(read_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2)); 1572 } 1573 1574 if (is_feat_mpam_supported()) { 1575 el2_sysregs_context_restore_mpam(el2_sysregs_ctx); 1576 } 1577 1578 if (is_feat_fgt_supported()) { 1579 el2_sysregs_context_restore_fgt(el2_sysregs_ctx); 1580 } 1581 1582 if (is_feat_fgt2_supported()) { 1583 el2_sysregs_context_restore_fgt2(el2_sysregs_ctx); 1584 } 1585 1586 if (is_feat_ecv_v2_supported()) { 1587 write_cntpoff_el2(read_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2)); 1588 } 1589 1590 if (is_feat_vhe_supported()) { 1591 write_contextidr_el2(read_el2_ctx_vhe(el2_sysregs_ctx, 1592 contextidr_el2)); 1593 write_ttbr1_el2(read_el2_ctx_vhe(el2_sysregs_ctx, ttbr1_el2)); 1594 } 1595 1596 if (is_feat_ras_supported()) { 1597 write_vdisr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2)); 1598 write_vsesr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2)); 1599 } 1600 1601 if (is_feat_nv2_supported()) { 1602 write_vncr_el2(read_el2_ctx_neve(el2_sysregs_ctx, vncr_el2)); 1603 } 1604 1605 if (is_feat_trf_supported()) { 1606 write_trfcr_el2(read_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2)); 1607 } 1608 1609 if (is_feat_csv2_2_supported()) { 1610 write_scxtnum_el2(read_el2_ctx_csv2_2(el2_sysregs_ctx, 1611 scxtnum_el2)); 1612 } 1613 1614 if (is_feat_hcx_supported()) { 1615 write_hcrx_el2(read_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2)); 1616 } 1617 1618 if (is_feat_tcr2_supported()) { 1619 write_tcr2_el2(read_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2)); 1620 } 1621 1622 if (is_feat_sxpie_supported()) { 1623 write_pire0_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2)); 1624 write_pir_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2)); 1625 } 1626 1627 if (is_feat_sxpoe_supported()) { 1628 write_por_el2(read_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2)); 1629 } 1630 1631 if (is_feat_s2pie_supported()) { 1632 write_s2pir_el2(read_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2)); 1633 } 1634 1635 if (is_feat_gcs_supported()) { 1636 write_gcscr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2)); 1637 write_gcspr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2)); 1638 } 1639 1640 if (is_feat_sctlr2_supported()) { 1641 write_sctlr2_el2(read_el2_ctx_sctlr2(el2_sysregs_ctx, sctlr2_el2)); 1642 } 1643 1644 if (is_feat_brbe_supported()) { 1645 write_brbcr_el2(read_el2_ctx_brbe(el2_sysregs_ctx, brbcr_el2)); 1646 } 1647 } 1648 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 1649 1650 #if IMAGE_BL31 1651 /********************************************************************************* 1652 * This function allows Architecture features asymmetry among cores. 1653 * TF-A assumes that all the cores in the platform has architecture feature parity 1654 * and hence the context is setup on different core (e.g. primary sets up the 1655 * context for secondary cores).This assumption may not be true for systems where 1656 * cores are not conforming to same Arch version or there is CPU Erratum which 1657 * requires certain feature to be be disabled only on a given core. 1658 * 1659 * This function is called on secondary cores to override any disparity in context 1660 * setup by primary, this would be called during warmboot path. 1661 *********************************************************************************/ 1662 void cm_handle_asymmetric_features(void) 1663 { 1664 cpu_context_t *ctx __maybe_unused = cm_get_context(NON_SECURE); 1665 1666 assert(ctx != NULL); 1667 1668 #if ENABLE_SPE_FOR_NS == FEAT_STATE_CHECK_ASYMMETRIC 1669 if (is_feat_spe_supported()) { 1670 spe_enable(ctx); 1671 } else { 1672 spe_disable(ctx); 1673 } 1674 #endif 1675 1676 #if ERRATA_A520_2938996 || ERRATA_X4_2726228 1677 if (check_if_affected_core() == ERRATA_APPLIES) { 1678 if (is_feat_trbe_supported()) { 1679 trbe_disable(ctx); 1680 } 1681 } 1682 #endif 1683 1684 #if ENABLE_FEAT_TCR2 == FEAT_STATE_CHECK_ASYMMETRIC 1685 el3_state_t *el3_state = get_el3state_ctx(ctx); 1686 u_register_t spsr = read_ctx_reg(el3_state, CTX_SPSR_EL3); 1687 1688 if (is_feat_tcr2_supported() && (GET_RW(spsr) == MODE_RW_64)) { 1689 tcr2_enable(ctx); 1690 } else { 1691 tcr2_disable(ctx); 1692 } 1693 #endif 1694 1695 } 1696 #endif 1697 1698 /******************************************************************************* 1699 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS 1700 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly 1701 * updating EL1 and EL2 registers. Otherwise, it calls the generic 1702 * cm_prepare_el3_exit function. 1703 ******************************************************************************/ 1704 void cm_prepare_el3_exit_ns(void) 1705 { 1706 #if IMAGE_BL31 1707 /* 1708 * Check and handle Architecture feature asymmetry among cores. 1709 * 1710 * In warmboot path secondary cores context is initialized on core which 1711 * did CPU_ON SMC call, if there is feature asymmetry in these cores handle 1712 * it in this function call. 1713 * For Symmetric cores this is an empty function. 1714 */ 1715 cm_handle_asymmetric_features(); 1716 #endif 1717 1718 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 1719 #if ENABLE_ASSERTIONS 1720 cpu_context_t *ctx = cm_get_context(NON_SECURE); 1721 assert(ctx != NULL); 1722 1723 /* Assert that EL2 is used. */ 1724 u_register_t scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 1725 assert(((scr_el3 & SCR_HCE_BIT) != 0UL) && 1726 (el_implemented(2U) != EL_IMPL_NONE)); 1727 #endif /* ENABLE_ASSERTIONS */ 1728 1729 /* Restore EL2 sysreg contexts */ 1730 cm_el2_sysregs_context_restore(NON_SECURE); 1731 cm_set_next_eret_context(NON_SECURE); 1732 #else 1733 cm_prepare_el3_exit(NON_SECURE); 1734 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 1735 } 1736 1737 #if ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) 1738 /******************************************************************************* 1739 * The next set of six functions are used by runtime services to save and restore 1740 * EL1 context on the 'cpu_context' structure for the specified security state. 1741 ******************************************************************************/ 1742 static void el1_sysregs_context_save(el1_sysregs_t *ctx) 1743 { 1744 write_el1_ctx_common(ctx, spsr_el1, read_spsr_el1()); 1745 write_el1_ctx_common(ctx, elr_el1, read_elr_el1()); 1746 1747 #if (!ERRATA_SPECULATIVE_AT) 1748 write_el1_ctx_common(ctx, sctlr_el1, read_sctlr_el1()); 1749 write_el1_ctx_common(ctx, tcr_el1, read_tcr_el1()); 1750 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1751 1752 write_el1_ctx_common(ctx, cpacr_el1, read_cpacr_el1()); 1753 write_el1_ctx_common(ctx, csselr_el1, read_csselr_el1()); 1754 write_el1_ctx_common(ctx, sp_el1, read_sp_el1()); 1755 write_el1_ctx_common(ctx, esr_el1, read_esr_el1()); 1756 write_el1_ctx_common(ctx, mair_el1, read_mair_el1()); 1757 write_el1_ctx_common(ctx, amair_el1, read_amair_el1()); 1758 write_el1_ctx_common(ctx, actlr_el1, read_actlr_el1()); 1759 write_el1_ctx_common(ctx, tpidr_el1, read_tpidr_el1()); 1760 write_el1_ctx_common(ctx, tpidr_el0, read_tpidr_el0()); 1761 write_el1_ctx_common(ctx, tpidrro_el0, read_tpidrro_el0()); 1762 write_el1_ctx_common(ctx, far_el1, read_far_el1()); 1763 write_el1_ctx_common(ctx, afsr0_el1, read_afsr0_el1()); 1764 write_el1_ctx_common(ctx, afsr1_el1, read_afsr1_el1()); 1765 write_el1_ctx_common(ctx, contextidr_el1, read_contextidr_el1()); 1766 write_el1_ctx_common(ctx, vbar_el1, read_vbar_el1()); 1767 write_el1_ctx_common(ctx, mdccint_el1, read_mdccint_el1()); 1768 write_el1_ctx_common(ctx, mdscr_el1, read_mdscr_el1()); 1769 1770 write_el1_ctx_common_sysreg128(ctx, par_el1, read_par_el1()); 1771 write_el1_ctx_common_sysreg128(ctx, ttbr0_el1, read_ttbr0_el1()); 1772 write_el1_ctx_common_sysreg128(ctx, ttbr1_el1, read_ttbr1_el1()); 1773 1774 if (CTX_INCLUDE_AARCH32_REGS) { 1775 /* Save Aarch32 registers */ 1776 write_el1_ctx_aarch32(ctx, spsr_abt, read_spsr_abt()); 1777 write_el1_ctx_aarch32(ctx, spsr_und, read_spsr_und()); 1778 write_el1_ctx_aarch32(ctx, spsr_irq, read_spsr_irq()); 1779 write_el1_ctx_aarch32(ctx, spsr_fiq, read_spsr_fiq()); 1780 write_el1_ctx_aarch32(ctx, dacr32_el2, read_dacr32_el2()); 1781 write_el1_ctx_aarch32(ctx, ifsr32_el2, read_ifsr32_el2()); 1782 } 1783 1784 if (NS_TIMER_SWITCH) { 1785 /* Save NS Timer registers */ 1786 write_el1_ctx_arch_timer(ctx, cntp_ctl_el0, read_cntp_ctl_el0()); 1787 write_el1_ctx_arch_timer(ctx, cntp_cval_el0, read_cntp_cval_el0()); 1788 write_el1_ctx_arch_timer(ctx, cntv_ctl_el0, read_cntv_ctl_el0()); 1789 write_el1_ctx_arch_timer(ctx, cntv_cval_el0, read_cntv_cval_el0()); 1790 write_el1_ctx_arch_timer(ctx, cntkctl_el1, read_cntkctl_el1()); 1791 } 1792 1793 if (is_feat_mte2_supported()) { 1794 write_el1_ctx_mte2(ctx, tfsre0_el1, read_tfsre0_el1()); 1795 write_el1_ctx_mte2(ctx, tfsr_el1, read_tfsr_el1()); 1796 write_el1_ctx_mte2(ctx, rgsr_el1, read_rgsr_el1()); 1797 write_el1_ctx_mte2(ctx, gcr_el1, read_gcr_el1()); 1798 } 1799 1800 if (is_feat_ras_supported()) { 1801 write_el1_ctx_ras(ctx, disr_el1, read_disr_el1()); 1802 } 1803 1804 if (is_feat_s1pie_supported()) { 1805 write_el1_ctx_s1pie(ctx, pire0_el1, read_pire0_el1()); 1806 write_el1_ctx_s1pie(ctx, pir_el1, read_pir_el1()); 1807 } 1808 1809 if (is_feat_s1poe_supported()) { 1810 write_el1_ctx_s1poe(ctx, por_el1, read_por_el1()); 1811 } 1812 1813 if (is_feat_s2poe_supported()) { 1814 write_el1_ctx_s2poe(ctx, s2por_el1, read_s2por_el1()); 1815 } 1816 1817 if (is_feat_tcr2_supported()) { 1818 write_el1_ctx_tcr2(ctx, tcr2_el1, read_tcr2_el1()); 1819 } 1820 1821 if (is_feat_trf_supported()) { 1822 write_el1_ctx_trf(ctx, trfcr_el1, read_trfcr_el1()); 1823 } 1824 1825 if (is_feat_csv2_2_supported()) { 1826 write_el1_ctx_csv2_2(ctx, scxtnum_el0, read_scxtnum_el0()); 1827 write_el1_ctx_csv2_2(ctx, scxtnum_el1, read_scxtnum_el1()); 1828 } 1829 1830 if (is_feat_gcs_supported()) { 1831 write_el1_ctx_gcs(ctx, gcscr_el1, read_gcscr_el1()); 1832 write_el1_ctx_gcs(ctx, gcscre0_el1, read_gcscre0_el1()); 1833 write_el1_ctx_gcs(ctx, gcspr_el1, read_gcspr_el1()); 1834 write_el1_ctx_gcs(ctx, gcspr_el0, read_gcspr_el0()); 1835 } 1836 1837 if (is_feat_the_supported()) { 1838 write_el1_ctx_the_sysreg128(ctx, rcwmask_el1, read_rcwmask_el1()); 1839 write_el1_ctx_the_sysreg128(ctx, rcwsmask_el1, read_rcwsmask_el1()); 1840 } 1841 1842 if (is_feat_sctlr2_supported()) { 1843 write_el1_ctx_sctlr2(ctx, sctlr2_el1, read_sctlr2_el1()); 1844 } 1845 1846 if (is_feat_ls64_accdata_supported()) { 1847 write_el1_ctx_ls64(ctx, accdata_el1, read_accdata_el1()); 1848 } 1849 } 1850 1851 static void el1_sysregs_context_restore(el1_sysregs_t *ctx) 1852 { 1853 write_spsr_el1(read_el1_ctx_common(ctx, spsr_el1)); 1854 write_elr_el1(read_el1_ctx_common(ctx, elr_el1)); 1855 1856 #if (!ERRATA_SPECULATIVE_AT) 1857 write_sctlr_el1(read_el1_ctx_common(ctx, sctlr_el1)); 1858 write_tcr_el1(read_el1_ctx_common(ctx, tcr_el1)); 1859 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1860 1861 write_cpacr_el1(read_el1_ctx_common(ctx, cpacr_el1)); 1862 write_csselr_el1(read_el1_ctx_common(ctx, csselr_el1)); 1863 write_sp_el1(read_el1_ctx_common(ctx, sp_el1)); 1864 write_esr_el1(read_el1_ctx_common(ctx, esr_el1)); 1865 write_ttbr0_el1(read_el1_ctx_common(ctx, ttbr0_el1)); 1866 write_ttbr1_el1(read_el1_ctx_common(ctx, ttbr1_el1)); 1867 write_mair_el1(read_el1_ctx_common(ctx, mair_el1)); 1868 write_amair_el1(read_el1_ctx_common(ctx, amair_el1)); 1869 write_actlr_el1(read_el1_ctx_common(ctx, actlr_el1)); 1870 write_tpidr_el1(read_el1_ctx_common(ctx, tpidr_el1)); 1871 write_tpidr_el0(read_el1_ctx_common(ctx, tpidr_el0)); 1872 write_tpidrro_el0(read_el1_ctx_common(ctx, tpidrro_el0)); 1873 write_par_el1(read_el1_ctx_common(ctx, par_el1)); 1874 write_far_el1(read_el1_ctx_common(ctx, far_el1)); 1875 write_afsr0_el1(read_el1_ctx_common(ctx, afsr0_el1)); 1876 write_afsr1_el1(read_el1_ctx_common(ctx, afsr1_el1)); 1877 write_contextidr_el1(read_el1_ctx_common(ctx, contextidr_el1)); 1878 write_vbar_el1(read_el1_ctx_common(ctx, vbar_el1)); 1879 write_mdccint_el1(read_el1_ctx_common(ctx, mdccint_el1)); 1880 write_mdscr_el1(read_el1_ctx_common(ctx, mdscr_el1)); 1881 1882 if (CTX_INCLUDE_AARCH32_REGS) { 1883 /* Restore Aarch32 registers */ 1884 write_spsr_abt(read_el1_ctx_aarch32(ctx, spsr_abt)); 1885 write_spsr_und(read_el1_ctx_aarch32(ctx, spsr_und)); 1886 write_spsr_irq(read_el1_ctx_aarch32(ctx, spsr_irq)); 1887 write_spsr_fiq(read_el1_ctx_aarch32(ctx, spsr_fiq)); 1888 write_dacr32_el2(read_el1_ctx_aarch32(ctx, dacr32_el2)); 1889 write_ifsr32_el2(read_el1_ctx_aarch32(ctx, ifsr32_el2)); 1890 } 1891 1892 if (NS_TIMER_SWITCH) { 1893 /* Restore NS Timer registers */ 1894 write_cntp_ctl_el0(read_el1_ctx_arch_timer(ctx, cntp_ctl_el0)); 1895 write_cntp_cval_el0(read_el1_ctx_arch_timer(ctx, cntp_cval_el0)); 1896 write_cntv_ctl_el0(read_el1_ctx_arch_timer(ctx, cntv_ctl_el0)); 1897 write_cntv_cval_el0(read_el1_ctx_arch_timer(ctx, cntv_cval_el0)); 1898 write_cntkctl_el1(read_el1_ctx_arch_timer(ctx, cntkctl_el1)); 1899 } 1900 1901 if (is_feat_mte2_supported()) { 1902 write_tfsre0_el1(read_el1_ctx_mte2(ctx, tfsre0_el1)); 1903 write_tfsr_el1(read_el1_ctx_mte2(ctx, tfsr_el1)); 1904 write_rgsr_el1(read_el1_ctx_mte2(ctx, rgsr_el1)); 1905 write_gcr_el1(read_el1_ctx_mte2(ctx, gcr_el1)); 1906 } 1907 1908 if (is_feat_ras_supported()) { 1909 write_disr_el1(read_el1_ctx_ras(ctx, disr_el1)); 1910 } 1911 1912 if (is_feat_s1pie_supported()) { 1913 write_pire0_el1(read_el1_ctx_s1pie(ctx, pire0_el1)); 1914 write_pir_el1(read_el1_ctx_s1pie(ctx, pir_el1)); 1915 } 1916 1917 if (is_feat_s1poe_supported()) { 1918 write_por_el1(read_el1_ctx_s1poe(ctx, por_el1)); 1919 } 1920 1921 if (is_feat_s2poe_supported()) { 1922 write_s2por_el1(read_el1_ctx_s2poe(ctx, s2por_el1)); 1923 } 1924 1925 if (is_feat_tcr2_supported()) { 1926 write_tcr2_el1(read_el1_ctx_tcr2(ctx, tcr2_el1)); 1927 } 1928 1929 if (is_feat_trf_supported()) { 1930 write_trfcr_el1(read_el1_ctx_trf(ctx, trfcr_el1)); 1931 } 1932 1933 if (is_feat_csv2_2_supported()) { 1934 write_scxtnum_el0(read_el1_ctx_csv2_2(ctx, scxtnum_el0)); 1935 write_scxtnum_el1(read_el1_ctx_csv2_2(ctx, scxtnum_el1)); 1936 } 1937 1938 if (is_feat_gcs_supported()) { 1939 write_gcscr_el1(read_el1_ctx_gcs(ctx, gcscr_el1)); 1940 write_gcscre0_el1(read_el1_ctx_gcs(ctx, gcscre0_el1)); 1941 write_gcspr_el1(read_el1_ctx_gcs(ctx, gcspr_el1)); 1942 write_gcspr_el0(read_el1_ctx_gcs(ctx, gcspr_el0)); 1943 } 1944 1945 if (is_feat_the_supported()) { 1946 write_rcwmask_el1(read_el1_ctx_the(ctx, rcwmask_el1)); 1947 write_rcwsmask_el1(read_el1_ctx_the(ctx, rcwsmask_el1)); 1948 } 1949 1950 if (is_feat_sctlr2_supported()) { 1951 write_sctlr2_el1(read_el1_ctx_sctlr2(ctx, sctlr2_el1)); 1952 } 1953 1954 if (is_feat_ls64_accdata_supported()) { 1955 write_accdata_el1(read_el1_ctx_ls64(ctx, accdata_el1)); 1956 } 1957 } 1958 1959 /******************************************************************************* 1960 * The next couple of functions are used by runtime services to save and restore 1961 * EL1 context on the 'cpu_context' structure for the specified security state. 1962 ******************************************************************************/ 1963 void cm_el1_sysregs_context_save(uint32_t security_state) 1964 { 1965 cpu_context_t *ctx; 1966 1967 ctx = cm_get_context(security_state); 1968 assert(ctx != NULL); 1969 1970 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 1971 1972 #if IMAGE_BL31 1973 if (security_state == SECURE) { 1974 PUBLISH_EVENT(cm_exited_secure_world); 1975 } else { 1976 PUBLISH_EVENT(cm_exited_normal_world); 1977 } 1978 #endif 1979 } 1980 1981 void cm_el1_sysregs_context_restore(uint32_t security_state) 1982 { 1983 cpu_context_t *ctx; 1984 1985 ctx = cm_get_context(security_state); 1986 assert(ctx != NULL); 1987 1988 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 1989 1990 #if IMAGE_BL31 1991 if (security_state == SECURE) { 1992 PUBLISH_EVENT(cm_entering_secure_world); 1993 } else { 1994 PUBLISH_EVENT(cm_entering_normal_world); 1995 } 1996 #endif 1997 } 1998 1999 #endif /* ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) */ 2000 2001 /******************************************************************************* 2002 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 2003 * given security state with the given entrypoint 2004 ******************************************************************************/ 2005 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 2006 { 2007 cpu_context_t *ctx; 2008 el3_state_t *state; 2009 2010 ctx = cm_get_context(security_state); 2011 assert(ctx != NULL); 2012 2013 /* Populate EL3 state so that ERET jumps to the correct entry */ 2014 state = get_el3state_ctx(ctx); 2015 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 2016 } 2017 2018 /******************************************************************************* 2019 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 2020 * pertaining to the given security state 2021 ******************************************************************************/ 2022 void cm_set_elr_spsr_el3(uint32_t security_state, 2023 uintptr_t entrypoint, uint32_t spsr) 2024 { 2025 cpu_context_t *ctx; 2026 el3_state_t *state; 2027 2028 ctx = cm_get_context(security_state); 2029 assert(ctx != NULL); 2030 2031 /* Populate EL3 state so that ERET jumps to the correct entry */ 2032 state = get_el3state_ctx(ctx); 2033 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 2034 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 2035 } 2036 2037 /******************************************************************************* 2038 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 2039 * pertaining to the given security state using the value and bit position 2040 * specified in the parameters. It preserves all other bits. 2041 ******************************************************************************/ 2042 void cm_write_scr_el3_bit(uint32_t security_state, 2043 uint32_t bit_pos, 2044 uint32_t value) 2045 { 2046 cpu_context_t *ctx; 2047 el3_state_t *state; 2048 u_register_t scr_el3; 2049 2050 ctx = cm_get_context(security_state); 2051 assert(ctx != NULL); 2052 2053 /* Ensure that the bit position is a valid one */ 2054 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 2055 2056 /* Ensure that the 'value' is only a bit wide */ 2057 assert(value <= 1U); 2058 2059 /* 2060 * Get the SCR_EL3 value from the cpu context, clear the desired bit 2061 * and set it to its new value. 2062 */ 2063 state = get_el3state_ctx(ctx); 2064 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 2065 scr_el3 &= ~(1UL << bit_pos); 2066 scr_el3 |= (u_register_t)value << bit_pos; 2067 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 2068 } 2069 2070 /******************************************************************************* 2071 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 2072 * given security state. 2073 ******************************************************************************/ 2074 u_register_t cm_get_scr_el3(uint32_t security_state) 2075 { 2076 cpu_context_t *ctx; 2077 el3_state_t *state; 2078 2079 ctx = cm_get_context(security_state); 2080 assert(ctx != NULL); 2081 2082 /* Populate EL3 state so that ERET jumps to the correct entry */ 2083 state = get_el3state_ctx(ctx); 2084 return read_ctx_reg(state, CTX_SCR_EL3); 2085 } 2086 2087 /******************************************************************************* 2088 * This function is used to program the context that's used for exception 2089 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 2090 * the required security state 2091 ******************************************************************************/ 2092 void cm_set_next_eret_context(uint32_t security_state) 2093 { 2094 cpu_context_t *ctx; 2095 2096 ctx = cm_get_context(security_state); 2097 assert(ctx != NULL); 2098 2099 cm_set_next_context(ctx); 2100 } 2101