1 /* 2 * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 #include <string.h> 10 11 #include <platform_def.h> 12 13 #include <arch.h> 14 #include <arch_helpers.h> 15 #include <arch_features.h> 16 #include <bl31/interrupt_mgmt.h> 17 #include <common/bl_common.h> 18 #include <context.h> 19 #include <lib/el3_runtime/context_mgmt.h> 20 #include <lib/el3_runtime/pubsub_events.h> 21 #include <lib/extensions/amu.h> 22 #include <lib/extensions/mpam.h> 23 #include <lib/extensions/spe.h> 24 #include <lib/extensions/sve.h> 25 #include <lib/extensions/twed.h> 26 #include <lib/utils.h> 27 28 29 /******************************************************************************* 30 * Context management library initialisation routine. This library is used by 31 * runtime services to share pointers to 'cpu_context' structures for the secure 32 * and non-secure states. Management of the structures and their associated 33 * memory is not done by the context management library e.g. the PSCI service 34 * manages the cpu context used for entry from and exit to the non-secure state. 35 * The Secure payload dispatcher service manages the context(s) corresponding to 36 * the secure state. It also uses this library to get access to the non-secure 37 * state cpu context pointers. 38 * Lastly, this library provides the api to make SP_EL3 point to the cpu context 39 * which will used for programming an entry into a lower EL. The same context 40 * will used to save state upon exception entry from that EL. 41 ******************************************************************************/ 42 void __init cm_init(void) 43 { 44 /* 45 * The context management library has only global data to intialize, but 46 * that will be done when the BSS is zeroed out 47 */ 48 } 49 50 /******************************************************************************* 51 * The following function initializes the cpu_context 'ctx' for 52 * first use, and sets the initial entrypoint state as specified by the 53 * entry_point_info structure. 54 * 55 * The security state to initialize is determined by the SECURE attribute 56 * of the entry_point_info. 57 * 58 * The EE and ST attributes are used to configure the endianness and secure 59 * timer availability for the new execution context. 60 * 61 * To prepare the register state for entry call cm_prepare_el3_exit() and 62 * el3_exit(). For Secure-EL1 cm_prepare_el3_exit() is equivalent to 63 * cm_e1_sysreg_context_restore(). 64 ******************************************************************************/ 65 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 66 { 67 unsigned int security_state; 68 u_register_t scr_el3; 69 el3_state_t *state; 70 gp_regs_t *gp_regs; 71 u_register_t sctlr_elx, actlr_elx; 72 73 assert(ctx != NULL); 74 75 security_state = GET_SECURITY_STATE(ep->h.attr); 76 77 /* Clear any residual register values from the context */ 78 zeromem(ctx, sizeof(*ctx)); 79 80 /* 81 * SCR_EL3 was initialised during reset sequence in macro 82 * el3_arch_init_common. This code modifies the SCR_EL3 fields that 83 * affect the next EL. 84 * 85 * The following fields are initially set to zero and then updated to 86 * the required value depending on the state of the SPSR_EL3 and the 87 * Security state and entrypoint attributes of the next EL. 88 */ 89 scr_el3 = read_scr(); 90 scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT | 91 SCR_ST_BIT | SCR_HCE_BIT); 92 /* 93 * SCR_NS: Set the security state of the next EL. 94 */ 95 if (security_state != SECURE) 96 scr_el3 |= SCR_NS_BIT; 97 /* 98 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 99 * Exception level as specified by SPSR. 100 */ 101 if (GET_RW(ep->spsr) == MODE_RW_64) 102 scr_el3 |= SCR_RW_BIT; 103 /* 104 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 105 * Secure timer registers to EL3, from AArch64 state only, if specified 106 * by the entrypoint attributes. 107 */ 108 if (EP_GET_ST(ep->h.attr) != 0U) 109 scr_el3 |= SCR_ST_BIT; 110 111 #if RAS_TRAP_LOWER_EL_ERR_ACCESS 112 /* 113 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 114 * and RAS ERX registers from EL1 and EL2 are trapped to EL3. 115 */ 116 scr_el3 |= SCR_TERR_BIT; 117 #endif 118 119 #if !HANDLE_EA_EL3_FIRST 120 /* 121 * SCR_EL3.EA: Do not route External Abort and SError Interrupt External 122 * to EL3 when executing at a lower EL. When executing at EL3, External 123 * Aborts are taken to EL3. 124 */ 125 scr_el3 &= ~SCR_EA_BIT; 126 #endif 127 128 #if FAULT_INJECTION_SUPPORT 129 /* Enable fault injection from lower ELs */ 130 scr_el3 |= SCR_FIEN_BIT; 131 #endif 132 133 #if !CTX_INCLUDE_PAUTH_REGS 134 /* 135 * If the pointer authentication registers aren't saved during world 136 * switches the value of the registers can be leaked from the Secure to 137 * the Non-secure world. To prevent this, rather than enabling pointer 138 * authentication everywhere, we only enable it in the Non-secure world. 139 * 140 * If the Secure world wants to use pointer authentication, 141 * CTX_INCLUDE_PAUTH_REGS must be set to 1. 142 */ 143 if (security_state == NON_SECURE) 144 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 145 #endif /* !CTX_INCLUDE_PAUTH_REGS */ 146 147 #if !CTX_INCLUDE_MTE_REGS || ENABLE_ASSERTIONS 148 /* Get Memory Tagging Extension support level */ 149 unsigned int mte = get_armv8_5_mte_support(); 150 #endif 151 /* 152 * Enable MTE support. Support is enabled unilaterally for the normal 153 * world, and only for the secure world when CTX_INCLUDE_MTE_REGS is 154 * set. 155 */ 156 #if CTX_INCLUDE_MTE_REGS 157 assert((mte == MTE_IMPLEMENTED_ELX) || (mte == MTE_IMPLEMENTED_ASY)); 158 scr_el3 |= SCR_ATA_BIT; 159 #else 160 /* 161 * When MTE is only implemented at EL0, it can be enabled 162 * across both worlds as no MTE registers are used. 163 */ 164 if ((mte == MTE_IMPLEMENTED_EL0) || 165 /* 166 * When MTE is implemented at all ELs, it can be only enabled 167 * in Non-Secure world without register saving. 168 */ 169 (((mte == MTE_IMPLEMENTED_ELX) || (mte == MTE_IMPLEMENTED_ASY)) && 170 (security_state == NON_SECURE))) { 171 scr_el3 |= SCR_ATA_BIT; 172 } 173 #endif /* CTX_INCLUDE_MTE_REGS */ 174 175 #ifdef IMAGE_BL31 176 /* 177 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 178 * indicated by the interrupt routing model for BL31. 179 */ 180 scr_el3 |= get_scr_el3_from_routing_model(security_state); 181 #endif 182 183 /* 184 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 185 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 186 * next mode is Hyp. 187 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 188 * same conditions as HVC instructions and when the processor supports 189 * ARMv8.6-FGT. 190 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 191 * CNTPOFF_EL2 register under the same conditions as HVC instructions 192 * and when the processor supports ECV. 193 */ 194 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 195 || ((GET_RW(ep->spsr) != MODE_RW_64) 196 && (GET_M32(ep->spsr) == MODE32_hyp))) { 197 scr_el3 |= SCR_HCE_BIT; 198 199 if (is_armv8_6_fgt_present()) { 200 scr_el3 |= SCR_FGTEN_BIT; 201 } 202 203 if (get_armv8_6_ecv_support() 204 == ID_AA64MMFR0_EL1_ECV_SELF_SYNCH) { 205 scr_el3 |= SCR_ECVEN_BIT; 206 } 207 } 208 209 /* Enable S-EL2 if the next EL is EL2 and security state is secure */ 210 if ((security_state == SECURE) && (GET_EL(ep->spsr) == MODE_EL2)) { 211 if (GET_RW(ep->spsr) != MODE_RW_64) { 212 ERROR("S-EL2 can not be used in AArch32."); 213 panic(); 214 } 215 216 scr_el3 |= SCR_EEL2_BIT; 217 } 218 219 /* 220 * FEAT_AMUv1p1 virtual offset registers are only accessible from EL3 221 * and EL2, when clear, this bit traps accesses from EL2 so we set it 222 * to 1 when EL2 is present. 223 */ 224 if (is_armv8_6_feat_amuv1p1_present() && 225 (el_implemented(2) != EL_IMPL_NONE)) { 226 scr_el3 |= SCR_AMVOFFEN_BIT; 227 } 228 229 /* 230 * Initialise SCTLR_EL1 to the reset value corresponding to the target 231 * execution state setting all fields rather than relying of the hw. 232 * Some fields have architecturally UNKNOWN reset values and these are 233 * set to zero. 234 * 235 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 236 * 237 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 238 * required by PSCI specification) 239 */ 240 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0U; 241 if (GET_RW(ep->spsr) == MODE_RW_64) 242 sctlr_elx |= SCTLR_EL1_RES1; 243 else { 244 /* 245 * If the target execution state is AArch32 then the following 246 * fields need to be set. 247 * 248 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 249 * instructions are not trapped to EL1. 250 * 251 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 252 * instructions are not trapped to EL1. 253 * 254 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 255 * CP15DMB, CP15DSB, and CP15ISB instructions. 256 */ 257 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 258 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 259 } 260 261 #if ERRATA_A75_764081 262 /* 263 * If workaround of errata 764081 for Cortex-A75 is used then set 264 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 265 */ 266 sctlr_elx |= SCTLR_IESB_BIT; 267 #endif 268 269 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 270 if (is_armv8_6_twed_present()) { 271 uint32_t delay = plat_arm_set_twedel_scr_el3(); 272 273 if (delay != TWED_DISABLED) { 274 /* Make sure delay value fits */ 275 assert((delay & ~SCR_TWEDEL_MASK) == 0U); 276 277 /* Set delay in SCR_EL3 */ 278 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 279 scr_el3 |= ((delay & SCR_TWEDEL_MASK) 280 << SCR_TWEDEL_SHIFT); 281 282 /* Enable WFE delay */ 283 scr_el3 |= SCR_TWEDEn_BIT; 284 } 285 } 286 287 /* 288 * Store the initialised SCTLR_EL1 value in the cpu_context - SCTLR_EL2 289 * and other EL2 registers are set up by cm_prepare_ns_entry() as they 290 * are not part of the stored cpu_context. 291 */ 292 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); 293 294 /* 295 * Base the context ACTLR_EL1 on the current value, as it is 296 * implementation defined. The context restore process will write 297 * the value from the context to the actual register and can cause 298 * problems for processor cores that don't expect certain bits to 299 * be zero. 300 */ 301 actlr_elx = read_actlr_el1(); 302 write_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx)); 303 304 /* 305 * Populate EL3 state so that we've the right context 306 * before doing ERET 307 */ 308 state = get_el3state_ctx(ctx); 309 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 310 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 311 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 312 313 /* 314 * Store the X0-X7 value from the entrypoint into the context 315 * Use memcpy as we are in control of the layout of the structures 316 */ 317 gp_regs = get_gpregs_ctx(ctx); 318 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 319 } 320 321 /******************************************************************************* 322 * Enable architecture extensions on first entry to Non-secure world. 323 * When EL2 is implemented but unused `el2_unused` is non-zero, otherwise 324 * it is zero. 325 ******************************************************************************/ 326 static void enable_extensions_nonsecure(bool el2_unused) 327 { 328 #if IMAGE_BL31 329 #if ENABLE_SPE_FOR_LOWER_ELS 330 spe_enable(el2_unused); 331 #endif 332 333 #if ENABLE_AMU 334 amu_enable(el2_unused); 335 #endif 336 337 #if ENABLE_SVE_FOR_NS 338 sve_enable(el2_unused); 339 #endif 340 341 #if ENABLE_MPAM_FOR_LOWER_ELS 342 mpam_enable(el2_unused); 343 #endif 344 #endif 345 } 346 347 /******************************************************************************* 348 * The following function initializes the cpu_context for a CPU specified by 349 * its `cpu_idx` for first use, and sets the initial entrypoint state as 350 * specified by the entry_point_info structure. 351 ******************************************************************************/ 352 void cm_init_context_by_index(unsigned int cpu_idx, 353 const entry_point_info_t *ep) 354 { 355 cpu_context_t *ctx; 356 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 357 cm_setup_context(ctx, ep); 358 } 359 360 /******************************************************************************* 361 * The following function initializes the cpu_context for the current CPU 362 * for first use, and sets the initial entrypoint state as specified by the 363 * entry_point_info structure. 364 ******************************************************************************/ 365 void cm_init_my_context(const entry_point_info_t *ep) 366 { 367 cpu_context_t *ctx; 368 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 369 cm_setup_context(ctx, ep); 370 } 371 372 /******************************************************************************* 373 * Prepare the CPU system registers for first entry into secure or normal world 374 * 375 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 376 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 377 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 378 * For all entries, the EL1 registers are initialized from the cpu_context 379 ******************************************************************************/ 380 void cm_prepare_el3_exit(uint32_t security_state) 381 { 382 u_register_t sctlr_elx, scr_el3, mdcr_el2; 383 cpu_context_t *ctx = cm_get_context(security_state); 384 bool el2_unused = false; 385 uint64_t hcr_el2 = 0U; 386 387 assert(ctx != NULL); 388 389 if (security_state == NON_SECURE) { 390 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 391 CTX_SCR_EL3); 392 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 393 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */ 394 sctlr_elx = read_ctx_reg(get_el1_sysregs_ctx(ctx), 395 CTX_SCTLR_EL1); 396 sctlr_elx &= SCTLR_EE_BIT; 397 sctlr_elx |= SCTLR_EL2_RES1; 398 #if ERRATA_A75_764081 399 /* 400 * If workaround of errata 764081 for Cortex-A75 is used 401 * then set SCTLR_EL2.IESB to enable Implicit Error 402 * Synchronization Barrier. 403 */ 404 sctlr_elx |= SCTLR_IESB_BIT; 405 #endif 406 write_sctlr_el2(sctlr_elx); 407 } else if (el_implemented(2) != EL_IMPL_NONE) { 408 el2_unused = true; 409 410 /* 411 * EL2 present but unused, need to disable safely. 412 * SCTLR_EL2 can be ignored in this case. 413 * 414 * Set EL2 register width appropriately: Set HCR_EL2 415 * field to match SCR_EL3.RW. 416 */ 417 if ((scr_el3 & SCR_RW_BIT) != 0U) 418 hcr_el2 |= HCR_RW_BIT; 419 420 /* 421 * For Armv8.3 pointer authentication feature, disable 422 * traps to EL2 when accessing key registers or using 423 * pointer authentication instructions from lower ELs. 424 */ 425 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 426 427 write_hcr_el2(hcr_el2); 428 429 /* 430 * Initialise CPTR_EL2 setting all fields rather than 431 * relying on the hw. All fields have architecturally 432 * UNKNOWN reset values. 433 * 434 * CPTR_EL2.TCPAC: Set to zero so that Non-secure EL1 435 * accesses to the CPACR_EL1 or CPACR from both 436 * Execution states do not trap to EL2. 437 * 438 * CPTR_EL2.TTA: Set to zero so that Non-secure System 439 * register accesses to the trace registers from both 440 * Execution states do not trap to EL2. 441 * 442 * CPTR_EL2.TFP: Set to zero so that Non-secure accesses 443 * to SIMD and floating-point functionality from both 444 * Execution states do not trap to EL2. 445 */ 446 write_cptr_el2(CPTR_EL2_RESET_VAL & 447 ~(CPTR_EL2_TCPAC_BIT | CPTR_EL2_TTA_BIT 448 | CPTR_EL2_TFP_BIT)); 449 450 /* 451 * Initialise CNTHCTL_EL2. All fields are 452 * architecturally UNKNOWN on reset and are set to zero 453 * except for field(s) listed below. 454 * 455 * CNTHCTL_EL2.EL1PCEN: Set to one to disable traps to 456 * Hyp mode of Non-secure EL0 and EL1 accesses to the 457 * physical timer registers. 458 * 459 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to 460 * Hyp mode of Non-secure EL0 and EL1 accesses to the 461 * physical counter registers. 462 */ 463 write_cnthctl_el2(CNTHCTL_RESET_VAL | 464 EL1PCEN_BIT | EL1PCTEN_BIT); 465 466 /* 467 * Initialise CNTVOFF_EL2 to zero as it resets to an 468 * architecturally UNKNOWN value. 469 */ 470 write_cntvoff_el2(0); 471 472 /* 473 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and 474 * MPIDR_EL1 respectively. 475 */ 476 write_vpidr_el2(read_midr_el1()); 477 write_vmpidr_el2(read_mpidr_el1()); 478 479 /* 480 * Initialise VTTBR_EL2. All fields are architecturally 481 * UNKNOWN on reset. 482 * 483 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 484 * 2 address translation is disabled, cache maintenance 485 * operations depend on the VMID. 486 * 487 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address 488 * translation is disabled. 489 */ 490 write_vttbr_el2(VTTBR_RESET_VAL & 491 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) 492 | (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 493 494 /* 495 * Initialise MDCR_EL2, setting all fields rather than 496 * relying on hw. Some fields are architecturally 497 * UNKNOWN on reset. 498 * 499 * MDCR_EL2.HLP: Set to one so that event counter 500 * overflow, that is recorded in PMOVSCLR_EL0[0-30], 501 * occurs on the increment that changes 502 * PMEVCNTR<n>_EL0[63] from 1 to 0, when ARMv8.5-PMU is 503 * implemented. This bit is RES0 in versions of the 504 * architecture earlier than ARMv8.5, setting it to 1 505 * doesn't have any effect on them. 506 * 507 * MDCR_EL2.TTRF: Set to zero so that access to Trace 508 * Filter Control register TRFCR_EL1 at EL1 is not 509 * trapped to EL2. This bit is RES0 in versions of 510 * the architecture earlier than ARMv8.4. 511 * 512 * MDCR_EL2.HPMD: Set to one so that event counting is 513 * prohibited at EL2. This bit is RES0 in versions of 514 * the architecture earlier than ARMv8.1, setting it 515 * to 1 doesn't have any effect on them. 516 * 517 * MDCR_EL2.TPMS: Set to zero so that accesses to 518 * Statistical Profiling control registers from EL1 519 * do not trap to EL2. This bit is RES0 when SPE is 520 * not implemented. 521 * 522 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and 523 * EL1 System register accesses to the Debug ROM 524 * registers are not trapped to EL2. 525 * 526 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 527 * System register accesses to the powerdown debug 528 * registers are not trapped to EL2. 529 * 530 * MDCR_EL2.TDA: Set to zero so that System register 531 * accesses to the debug registers do not trap to EL2. 532 * 533 * MDCR_EL2.TDE: Set to zero so that debug exceptions 534 * are not routed to EL2. 535 * 536 * MDCR_EL2.HPME: Set to zero to disable EL2 Performance 537 * Monitors. 538 * 539 * MDCR_EL2.TPM: Set to zero so that Non-secure EL0 and 540 * EL1 accesses to all Performance Monitors registers 541 * are not trapped to EL2. 542 * 543 * MDCR_EL2.TPMCR: Set to zero so that Non-secure EL0 544 * and EL1 accesses to the PMCR_EL0 or PMCR are not 545 * trapped to EL2. 546 * 547 * MDCR_EL2.HPMN: Set to value of PMCR_EL0.N which is the 548 * architecturally-defined reset value. 549 */ 550 mdcr_el2 = ((MDCR_EL2_RESET_VAL | MDCR_EL2_HLP | 551 MDCR_EL2_HPMD) | 552 ((read_pmcr_el0() & PMCR_EL0_N_BITS) 553 >> PMCR_EL0_N_SHIFT)) & 554 ~(MDCR_EL2_TTRF | MDCR_EL2_TPMS | 555 MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | 556 MDCR_EL2_TDA_BIT | MDCR_EL2_TDE_BIT | 557 MDCR_EL2_HPME_BIT | MDCR_EL2_TPM_BIT | 558 MDCR_EL2_TPMCR_BIT); 559 560 write_mdcr_el2(mdcr_el2); 561 562 /* 563 * Initialise HSTR_EL2. All fields are architecturally 564 * UNKNOWN on reset. 565 * 566 * HSTR_EL2.T<n>: Set all these fields to zero so that 567 * Non-secure EL0 or EL1 accesses to System registers 568 * do not trap to EL2. 569 */ 570 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 571 /* 572 * Initialise CNTHP_CTL_EL2. All fields are 573 * architecturally UNKNOWN on reset. 574 * 575 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 576 * physical timer and prevent timer interrupts. 577 */ 578 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & 579 ~(CNTHP_CTL_ENABLE_BIT)); 580 } 581 enable_extensions_nonsecure(el2_unused); 582 } 583 584 cm_el1_sysregs_context_restore(security_state); 585 cm_set_next_eret_context(security_state); 586 } 587 588 #if CTX_INCLUDE_EL2_REGS 589 /******************************************************************************* 590 * Save EL2 sysreg context 591 ******************************************************************************/ 592 void cm_el2_sysregs_context_save(uint32_t security_state) 593 { 594 u_register_t scr_el3 = read_scr(); 595 596 /* 597 * Always save the non-secure EL2 context, only save the 598 * S-EL2 context if S-EL2 is enabled. 599 */ 600 if ((security_state == NON_SECURE) || 601 ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) { 602 cpu_context_t *ctx; 603 604 ctx = cm_get_context(security_state); 605 assert(ctx != NULL); 606 607 el2_sysregs_context_save(get_el2_sysregs_ctx(ctx)); 608 } 609 } 610 611 /******************************************************************************* 612 * Restore EL2 sysreg context 613 ******************************************************************************/ 614 void cm_el2_sysregs_context_restore(uint32_t security_state) 615 { 616 u_register_t scr_el3 = read_scr(); 617 618 /* 619 * Always restore the non-secure EL2 context, only restore the 620 * S-EL2 context if S-EL2 is enabled. 621 */ 622 if ((security_state == NON_SECURE) || 623 ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) { 624 cpu_context_t *ctx; 625 626 ctx = cm_get_context(security_state); 627 assert(ctx != NULL); 628 629 el2_sysregs_context_restore(get_el2_sysregs_ctx(ctx)); 630 } 631 } 632 #endif /* CTX_INCLUDE_EL2_REGS */ 633 634 /******************************************************************************* 635 * The next four functions are used by runtime services to save and restore 636 * EL1 context on the 'cpu_context' structure for the specified security 637 * state. 638 ******************************************************************************/ 639 void cm_el1_sysregs_context_save(uint32_t security_state) 640 { 641 cpu_context_t *ctx; 642 643 ctx = cm_get_context(security_state); 644 assert(ctx != NULL); 645 646 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 647 648 #if IMAGE_BL31 649 if (security_state == SECURE) 650 PUBLISH_EVENT(cm_exited_secure_world); 651 else 652 PUBLISH_EVENT(cm_exited_normal_world); 653 #endif 654 } 655 656 void cm_el1_sysregs_context_restore(uint32_t security_state) 657 { 658 cpu_context_t *ctx; 659 660 ctx = cm_get_context(security_state); 661 assert(ctx != NULL); 662 663 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 664 665 #if IMAGE_BL31 666 if (security_state == SECURE) 667 PUBLISH_EVENT(cm_entering_secure_world); 668 else 669 PUBLISH_EVENT(cm_entering_normal_world); 670 #endif 671 } 672 673 /******************************************************************************* 674 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 675 * given security state with the given entrypoint 676 ******************************************************************************/ 677 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 678 { 679 cpu_context_t *ctx; 680 el3_state_t *state; 681 682 ctx = cm_get_context(security_state); 683 assert(ctx != NULL); 684 685 /* Populate EL3 state so that ERET jumps to the correct entry */ 686 state = get_el3state_ctx(ctx); 687 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 688 } 689 690 /******************************************************************************* 691 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 692 * pertaining to the given security state 693 ******************************************************************************/ 694 void cm_set_elr_spsr_el3(uint32_t security_state, 695 uintptr_t entrypoint, uint32_t spsr) 696 { 697 cpu_context_t *ctx; 698 el3_state_t *state; 699 700 ctx = cm_get_context(security_state); 701 assert(ctx != NULL); 702 703 /* Populate EL3 state so that ERET jumps to the correct entry */ 704 state = get_el3state_ctx(ctx); 705 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 706 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 707 } 708 709 /******************************************************************************* 710 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 711 * pertaining to the given security state using the value and bit position 712 * specified in the parameters. It preserves all other bits. 713 ******************************************************************************/ 714 void cm_write_scr_el3_bit(uint32_t security_state, 715 uint32_t bit_pos, 716 uint32_t value) 717 { 718 cpu_context_t *ctx; 719 el3_state_t *state; 720 u_register_t scr_el3; 721 722 ctx = cm_get_context(security_state); 723 assert(ctx != NULL); 724 725 /* Ensure that the bit position is a valid one */ 726 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 727 728 /* Ensure that the 'value' is only a bit wide */ 729 assert(value <= 1U); 730 731 /* 732 * Get the SCR_EL3 value from the cpu context, clear the desired bit 733 * and set it to its new value. 734 */ 735 state = get_el3state_ctx(ctx); 736 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 737 scr_el3 &= ~(1UL << bit_pos); 738 scr_el3 |= (u_register_t)value << bit_pos; 739 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 740 } 741 742 /******************************************************************************* 743 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 744 * given security state. 745 ******************************************************************************/ 746 u_register_t cm_get_scr_el3(uint32_t security_state) 747 { 748 cpu_context_t *ctx; 749 el3_state_t *state; 750 751 ctx = cm_get_context(security_state); 752 assert(ctx != NULL); 753 754 /* Populate EL3 state so that ERET jumps to the correct entry */ 755 state = get_el3state_ctx(ctx); 756 return read_ctx_reg(state, CTX_SCR_EL3); 757 } 758 759 /******************************************************************************* 760 * This function is used to program the context that's used for exception 761 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 762 * the required security state 763 ******************************************************************************/ 764 void cm_set_next_eret_context(uint32_t security_state) 765 { 766 cpu_context_t *ctx; 767 768 ctx = cm_get_context(security_state); 769 assert(ctx != NULL); 770 771 cm_set_next_context(ctx); 772 } 773