1 /* 2 * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <stdbool.h> 10 #include <string.h> 11 12 #include <platform_def.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <arch_features.h> 17 #include <bl31/interrupt_mgmt.h> 18 #include <common/bl_common.h> 19 #include <common/debug.h> 20 #include <context.h> 21 #include <drivers/arm/gicv3.h> 22 #include <lib/cpus/cpu_ops.h> 23 #include <lib/cpus/errata.h> 24 #include <lib/el3_runtime/context_mgmt.h> 25 #include <lib/el3_runtime/cpu_data.h> 26 #include <lib/el3_runtime/pubsub_events.h> 27 #include <lib/extensions/amu.h> 28 #include <lib/extensions/brbe.h> 29 #include <lib/extensions/debug_v8p9.h> 30 #include <lib/extensions/fgt2.h> 31 #include <lib/extensions/fpmr.h> 32 #include <lib/extensions/mpam.h> 33 #include <lib/extensions/pauth.h> 34 #include <lib/extensions/pmuv3.h> 35 #include <lib/extensions/sme.h> 36 #include <lib/extensions/spe.h> 37 #include <lib/extensions/sve.h> 38 #include <lib/extensions/sysreg128.h> 39 #include <lib/extensions/sys_reg_trace.h> 40 #include <lib/extensions/tcr2.h> 41 #include <lib/extensions/trbe.h> 42 #include <lib/extensions/trf.h> 43 #include <lib/utils.h> 44 45 #if ENABLE_FEAT_TWED 46 /* Make sure delay value fits within the range(0-15) */ 47 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check); 48 #endif /* ENABLE_FEAT_TWED */ 49 50 per_world_context_t per_world_context[CPU_DATA_CONTEXT_NUM]; 51 static bool has_secure_perworld_init; 52 53 static void manage_extensions_nonsecure(cpu_context_t *ctx); 54 static void manage_extensions_secure(cpu_context_t *ctx); 55 static void manage_extensions_secure_per_world(void); 56 57 #if ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) 58 static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep) 59 { 60 u_register_t sctlr_elx, actlr_elx; 61 62 /* 63 * Initialise SCTLR_EL1 to the reset value corresponding to the target 64 * execution state setting all fields rather than relying on the hw. 65 * Some fields have architecturally UNKNOWN reset values and these are 66 * set to zero. 67 * 68 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 69 * 70 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 71 * required by PSCI specification) 72 */ 73 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 74 if (GET_RW(ep->spsr) == MODE_RW_64) { 75 sctlr_elx |= SCTLR_EL1_RES1; 76 } else { 77 /* 78 * If the target execution state is AArch32 then the following 79 * fields need to be set. 80 * 81 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 82 * instructions are not trapped to EL1. 83 * 84 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 85 * instructions are not trapped to EL1. 86 * 87 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 88 * CP15DMB, CP15DSB, and CP15ISB instructions. 89 */ 90 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 91 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 92 } 93 94 /* 95 * If workaround of errata 764081 for Cortex-A75 is used then set 96 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 97 */ 98 if (errata_a75_764081_applies()) { 99 sctlr_elx |= SCTLR_IESB_BIT; 100 } 101 102 /* Store the initialised SCTLR_EL1 value in the cpu_context */ 103 write_ctx_sctlr_el1_reg_errata(ctx, sctlr_elx); 104 105 /* 106 * Base the context ACTLR_EL1 on the current value, as it is 107 * implementation defined. The context restore process will write 108 * the value from the context to the actual register and can cause 109 * problems for processor cores that don't expect certain bits to 110 * be zero. 111 */ 112 actlr_elx = read_actlr_el1(); 113 write_el1_ctx_common(get_el1_sysregs_ctx(ctx), actlr_el1, actlr_elx); 114 } 115 #endif /* (IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS)) */ 116 117 /****************************************************************************** 118 * This function performs initializations that are specific to SECURE state 119 * and updates the cpu context specified by 'ctx'. 120 *****************************************************************************/ 121 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep) 122 { 123 u_register_t scr_el3; 124 el3_state_t *state; 125 126 state = get_el3state_ctx(ctx); 127 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 128 129 #if defined(IMAGE_BL31) && !defined(SPD_spmd) 130 /* 131 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 132 * indicated by the interrupt routing model for BL31. 133 */ 134 scr_el3 |= get_scr_el3_from_routing_model(SECURE); 135 #endif 136 137 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 138 if (is_feat_mte2_supported()) { 139 scr_el3 |= SCR_ATA_BIT; 140 } 141 142 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 143 144 /* 145 * Initialize EL1 context registers unless SPMC is running 146 * at S-EL2. 147 */ 148 #if (!SPMD_SPM_AT_SEL2) 149 setup_el1_context(ctx, ep); 150 #endif 151 152 manage_extensions_secure(ctx); 153 154 /** 155 * manage_extensions_secure_per_world api has to be executed once, 156 * as the registers getting initialised, maintain constant value across 157 * all the cpus for the secure world. 158 * Henceforth, this check ensures that the registers are initialised once 159 * and avoids re-initialization from multiple cores. 160 */ 161 if (!has_secure_perworld_init) { 162 manage_extensions_secure_per_world(); 163 } 164 } 165 166 #if ENABLE_RME 167 /****************************************************************************** 168 * This function performs initializations that are specific to REALM state 169 * and updates the cpu context specified by 'ctx'. 170 *****************************************************************************/ 171 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep) 172 { 173 u_register_t scr_el3; 174 el3_state_t *state; 175 176 state = get_el3state_ctx(ctx); 177 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 178 179 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT; 180 181 /* CSV2 version 2 and above */ 182 if (is_feat_csv2_2_supported()) { 183 /* Enable access to the SCXTNUM_ELx registers. */ 184 scr_el3 |= SCR_EnSCXT_BIT; 185 } 186 187 if (is_feat_sctlr2_supported()) { 188 /* Set the SCTLR2En bit in SCR_EL3 to enable access to 189 * SCTLR2_ELx registers. 190 */ 191 scr_el3 |= SCR_SCTLR2En_BIT; 192 } 193 194 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 195 196 if (is_feat_fgt2_supported()) { 197 fgt2_enable(ctx); 198 } 199 200 if (is_feat_debugv8p9_supported()) { 201 debugv8p9_extended_bp_wp_enable(ctx); 202 } 203 204 if (is_feat_brbe_supported()) { 205 brbe_enable(ctx); 206 } 207 208 } 209 #endif /* ENABLE_RME */ 210 211 /****************************************************************************** 212 * This function performs initializations that are specific to NON-SECURE state 213 * and updates the cpu context specified by 'ctx'. 214 *****************************************************************************/ 215 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep) 216 { 217 u_register_t scr_el3; 218 el3_state_t *state; 219 220 state = get_el3state_ctx(ctx); 221 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 222 223 /* SCR_NS: Set the NS bit */ 224 scr_el3 |= SCR_NS_BIT; 225 226 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 227 if (is_feat_mte2_supported()) { 228 scr_el3 |= SCR_ATA_BIT; 229 } 230 231 /* 232 * Pointer Authentication feature, if present, is always enabled by 233 * default for Non secure lower exception levels. We do not have an 234 * explicit flag to set it. To prevent the leakage between the worlds 235 * during world switch, we enable it only for the non-secure world. 236 * 237 * CTX_INCLUDE_PAUTH_REGS flag, is explicitly used to enable for lower 238 * exception levels of secure and realm worlds. 239 * 240 * If the Secure/realm world wants to use pointer authentication, 241 * CTX_INCLUDE_PAUTH_REGS must be explicitly set to 1, in which case 242 * it will be enabled globally for all the contexts. 243 * 244 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 245 * other than EL3 246 * 247 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 248 * than EL3 249 */ 250 if (!is_ctx_pauth_supported()) { 251 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 252 } 253 254 #if HANDLE_EA_EL3_FIRST_NS 255 /* SCR_EL3.EA: Route External Abort and SError Interrupt to EL3. */ 256 scr_el3 |= SCR_EA_BIT; 257 #endif 258 259 #if RAS_TRAP_NS_ERR_REC_ACCESS 260 /* 261 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 262 * and RAS ERX registers from EL1 and EL2(from any security state) 263 * are trapped to EL3. 264 * Set here to trap only for NS EL1/EL2 265 */ 266 scr_el3 |= SCR_TERR_BIT; 267 #endif 268 269 /* CSV2 version 2 and above */ 270 if (is_feat_csv2_2_supported()) { 271 /* Enable access to the SCXTNUM_ELx registers. */ 272 scr_el3 |= SCR_EnSCXT_BIT; 273 } 274 275 #ifdef IMAGE_BL31 276 /* 277 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 278 * indicated by the interrupt routing model for BL31. 279 */ 280 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE); 281 #endif 282 283 if (is_feat_the_supported()) { 284 /* Set the RCWMASKEn bit in SCR_EL3 to enable access to 285 * RCWMASK_EL1 and RCWSMASK_EL1 registers. 286 */ 287 scr_el3 |= SCR_RCWMASKEn_BIT; 288 } 289 290 if (is_feat_sctlr2_supported()) { 291 /* Set the SCTLR2En bit in SCR_EL3 to enable access to 292 * SCTLR2_ELx registers. 293 */ 294 scr_el3 |= SCR_SCTLR2En_BIT; 295 } 296 297 if (is_feat_d128_supported()) { 298 /* Set the D128En bit in SCR_EL3 to enable access to 128-bit 299 * versions of TTBR0_EL1, TTBR1_EL1, RCWMASK_EL1, RCWSMASK_EL1, 300 * PAR_EL1 and TTBR1_EL2, TTBR0_EL2 and VTTBR_EL2 registers. 301 */ 302 scr_el3 |= SCR_D128En_BIT; 303 } 304 305 if (is_feat_fpmr_supported()) { 306 /* Set the EnFPM bit in SCR_EL3 to enable access to FPMR 307 * register. 308 */ 309 scr_el3 |= SCR_EnFPM_BIT; 310 } 311 312 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 313 314 /* Initialize EL2 context registers */ 315 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 316 317 /* 318 * Initialize SCTLR_EL2 context register with reset value. 319 */ 320 write_el2_ctx_common(get_el2_sysregs_ctx(ctx), sctlr_el2, SCTLR_EL2_RES1); 321 322 if (is_feat_hcx_supported()) { 323 /* 324 * Initialize register HCRX_EL2 with its init value. 325 * As the value of HCRX_EL2 is UNKNOWN on reset, there is a 326 * chance that this can lead to unexpected behavior in lower 327 * ELs that have not been updated since the introduction of 328 * this feature if not properly initialized, especially when 329 * it comes to those bits that enable/disable traps. 330 */ 331 write_el2_ctx_hcx(get_el2_sysregs_ctx(ctx), hcrx_el2, 332 HCRX_EL2_INIT_VAL); 333 } 334 335 if (is_feat_fgt_supported()) { 336 /* 337 * Initialize HFG*_EL2 registers with a default value so legacy 338 * systems unaware of FEAT_FGT do not get trapped due to their lack 339 * of initialization for this feature. 340 */ 341 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgitr_el2, 342 HFGITR_EL2_INIT_VAL); 343 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgrtr_el2, 344 HFGRTR_EL2_INIT_VAL); 345 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgwtr_el2, 346 HFGWTR_EL2_INIT_VAL); 347 } 348 #else 349 /* Initialize EL1 context registers */ 350 setup_el1_context(ctx, ep); 351 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 352 353 manage_extensions_nonsecure(ctx); 354 } 355 356 /******************************************************************************* 357 * The following function performs initialization of the cpu_context 'ctx' 358 * for first use that is common to all security states, and sets the 359 * initial entrypoint state as specified by the entry_point_info structure. 360 * 361 * The EE and ST attributes are used to configure the endianness and secure 362 * timer availability for the new execution context. 363 ******************************************************************************/ 364 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 365 { 366 u_register_t scr_el3; 367 u_register_t mdcr_el3; 368 el3_state_t *state; 369 gp_regs_t *gp_regs; 370 371 state = get_el3state_ctx(ctx); 372 373 /* Clear any residual register values from the context */ 374 zeromem(ctx, sizeof(*ctx)); 375 376 /* 377 * The lower-EL context is zeroed so that no stale values leak to a world. 378 * It is assumed that an all-zero lower-EL context is good enough for it 379 * to boot correctly. However, there are very few registers where this 380 * is not true and some values need to be recreated. 381 */ 382 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 383 el2_sysregs_t *el2_ctx = get_el2_sysregs_ctx(ctx); 384 385 /* 386 * These bits are set in the gicv3 driver. Losing them (especially the 387 * SRE bit) is problematic for all worlds. Henceforth recreate them. 388 */ 389 u_register_t icc_sre_el2_val = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | 390 ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT; 391 write_el2_ctx_common(el2_ctx, icc_sre_el2, icc_sre_el2_val); 392 393 /* 394 * The actlr_el2 register can be initialized in platform's reset handler 395 * and it may contain access control bits (e.g. CLUSTERPMUEN bit). 396 */ 397 write_el2_ctx_common(el2_ctx, actlr_el2, read_actlr_el2()); 398 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 399 400 /* Start with a clean SCR_EL3 copy as all relevant values are set */ 401 scr_el3 = SCR_RESET_VAL; 402 403 /* 404 * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at 405 * EL2, EL1 and EL0 are not trapped to EL3. 406 * 407 * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at 408 * EL2, EL1 and EL0 are not trapped to EL3. 409 * 410 * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from 411 * both Security states and both Execution states. 412 * 413 * SCR_EL3.SIF: Set to one to disable secure instruction execution from 414 * Non-secure memory. 415 */ 416 scr_el3 &= ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT); 417 418 scr_el3 |= SCR_SIF_BIT; 419 420 /* 421 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 422 * Exception level as specified by SPSR. 423 */ 424 if (GET_RW(ep->spsr) == MODE_RW_64) { 425 scr_el3 |= SCR_RW_BIT; 426 } 427 428 /* 429 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 430 * Secure timer registers to EL3, from AArch64 state only, if specified 431 * by the entrypoint attributes. If SEL2 is present and enabled, the ST 432 * bit always behaves as 1 (i.e. secure physical timer register access 433 * is not trapped) 434 */ 435 if (EP_GET_ST(ep->h.attr) != 0U) { 436 scr_el3 |= SCR_ST_BIT; 437 } 438 439 /* 440 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting 441 * SCR_EL3.HXEn. 442 */ 443 if (is_feat_hcx_supported()) { 444 scr_el3 |= SCR_HXEn_BIT; 445 } 446 447 /* 448 * If FEAT_LS64_ACCDATA is enabled, enable access to ACCDATA_EL1 by 449 * setting SCR_EL3.ADEn and allow the ST64BV0 instruction by setting 450 * SCR_EL3.EnAS0. 451 */ 452 if (is_feat_ls64_accdata_supported()) { 453 scr_el3 |= SCR_ADEn_BIT | SCR_EnAS0_BIT; 454 } 455 456 /* 457 * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS 458 * registers are trapped to EL3. 459 */ 460 if (is_feat_rng_trap_supported()) { 461 scr_el3 |= SCR_TRNDR_BIT; 462 } 463 464 #if FAULT_INJECTION_SUPPORT 465 /* Enable fault injection from lower ELs */ 466 scr_el3 |= SCR_FIEN_BIT; 467 #endif 468 469 /* 470 * Enable Pointer Authentication globally for all the worlds. 471 * 472 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 473 * other than EL3 474 * 475 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 476 * than EL3 477 */ 478 if (is_ctx_pauth_supported()) { 479 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 480 } 481 482 /* 483 * SCR_EL3.PIEN: Enable permission indirection and overlay 484 * registers for AArch64 if present. 485 */ 486 if (is_feat_sxpie_supported() || is_feat_sxpoe_supported()) { 487 scr_el3 |= SCR_PIEN_BIT; 488 } 489 490 /* 491 * SCR_EL3.GCSEn: Enable GCS registers for AArch64 if present. 492 */ 493 if ((is_feat_gcs_supported()) && (GET_RW(ep->spsr) == MODE_RW_64)) { 494 scr_el3 |= SCR_GCSEn_BIT; 495 } 496 497 /* 498 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 499 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 500 * next mode is Hyp. 501 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 502 * same conditions as HVC instructions and when the processor supports 503 * ARMv8.6-FGT. 504 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 505 * CNTPOFF_EL2 register under the same conditions as HVC instructions 506 * and when the processor supports ECV. 507 */ 508 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 509 || ((GET_RW(ep->spsr) != MODE_RW_64) 510 && (GET_M32(ep->spsr) == MODE32_hyp))) { 511 scr_el3 |= SCR_HCE_BIT; 512 513 if (is_feat_fgt_supported()) { 514 scr_el3 |= SCR_FGTEN_BIT; 515 } 516 517 if (is_feat_ecv_supported()) { 518 scr_el3 |= SCR_ECVEN_BIT; 519 } 520 } 521 522 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 523 if (is_feat_twed_supported()) { 524 /* Set delay in SCR_EL3 */ 525 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 526 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK) 527 << SCR_TWEDEL_SHIFT); 528 529 /* Enable WFE delay */ 530 scr_el3 |= SCR_TWEDEn_BIT; 531 } 532 533 #if IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2 534 /* Enable S-EL2 if FEAT_SEL2 is implemented for all the contexts. */ 535 if (is_feat_sel2_supported()) { 536 scr_el3 |= SCR_EEL2_BIT; 537 } 538 #endif /* (IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2) */ 539 540 if (is_feat_mec_supported()) { 541 scr_el3 |= SCR_MECEn_BIT; 542 } 543 544 /* 545 * Populate EL3 state so that we've the right context 546 * before doing ERET 547 */ 548 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 549 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 550 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 551 552 /* Start with a clean MDCR_EL3 copy as all relevant values are set */ 553 mdcr_el3 = MDCR_EL3_RESET_VAL; 554 555 /* --------------------------------------------------------------------- 556 * Initialise MDCR_EL3, setting all fields rather than relying on hw. 557 * Some fields are architecturally UNKNOWN on reset. 558 * 559 * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug. 560 * Debug exceptions, other than Breakpoint Instruction exceptions, are 561 * disabled from all ELs in Secure state. 562 * 563 * MDCR_EL3.SPD32: Set to 0b10 to disable AArch32 Secure self-hosted 564 * privileged debug from S-EL1. 565 * 566 * MDCR_EL3.TDOSA: Set to zero so that EL2 and EL2 System register 567 * access to the powerdown debug registers do not trap to EL3. 568 * 569 * MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the 570 * debug registers, other than those registers that are controlled by 571 * MDCR_EL3.TDOSA. 572 */ 573 mdcr_el3 |= ((MDCR_SDD_BIT | MDCR_SPD32(MDCR_SPD32_DISABLE)) 574 & ~(MDCR_TDA_BIT | MDCR_TDOSA_BIT)) ; 575 write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3); 576 577 #if IMAGE_BL31 578 /* Enable FEAT_TRF for Non-Secure and prohibit for Secure state. */ 579 if (is_feat_trf_supported()) { 580 trf_enable(ctx); 581 } 582 583 if (is_feat_tcr2_supported()) { 584 tcr2_enable(ctx); 585 } 586 587 pmuv3_enable(ctx); 588 #endif /* IMAGE_BL31 */ 589 590 /* 591 * Store the X0-X7 value from the entrypoint into the context 592 * Use memcpy as we are in control of the layout of the structures 593 */ 594 gp_regs = get_gpregs_ctx(ctx); 595 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 596 } 597 598 /******************************************************************************* 599 * Context management library initialization routine. This library is used by 600 * runtime services to share pointers to 'cpu_context' structures for secure 601 * non-secure and realm states. Management of the structures and their associated 602 * memory is not done by the context management library e.g. the PSCI service 603 * manages the cpu context used for entry from and exit to the non-secure state. 604 * The Secure payload dispatcher service manages the context(s) corresponding to 605 * the secure state. It also uses this library to get access to the non-secure 606 * state cpu context pointers. 607 * Lastly, this library provides the API to make SP_EL3 point to the cpu context 608 * which will be used for programming an entry into a lower EL. The same context 609 * will be used to save state upon exception entry from that EL. 610 ******************************************************************************/ 611 void __init cm_init(void) 612 { 613 /* 614 * The context management library has only global data to initialize, but 615 * that will be done when the BSS is zeroed out. 616 */ 617 } 618 619 /******************************************************************************* 620 * This is the high-level function used to initialize the cpu_context 'ctx' for 621 * first use. It performs initializations that are common to all security states 622 * and initializations specific to the security state specified in 'ep' 623 ******************************************************************************/ 624 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 625 { 626 unsigned int security_state; 627 628 assert(ctx != NULL); 629 630 /* 631 * Perform initializations that are common 632 * to all security states 633 */ 634 setup_context_common(ctx, ep); 635 636 security_state = GET_SECURITY_STATE(ep->h.attr); 637 638 /* Perform security state specific initializations */ 639 switch (security_state) { 640 case SECURE: 641 setup_secure_context(ctx, ep); 642 break; 643 #if ENABLE_RME 644 case REALM: 645 setup_realm_context(ctx, ep); 646 break; 647 #endif 648 case NON_SECURE: 649 setup_ns_context(ctx, ep); 650 break; 651 default: 652 ERROR("Invalid security state\n"); 653 panic(); 654 break; 655 } 656 } 657 658 /******************************************************************************* 659 * Enable architecture extensions for EL3 execution. This function only updates 660 * registers in-place which are expected to either never change or be 661 * overwritten by el3_exit. Expects the core_pos of the current core as argument. 662 ******************************************************************************/ 663 #if IMAGE_BL31 664 void cm_manage_extensions_el3(unsigned int my_idx) 665 { 666 if (is_feat_sve_supported()) { 667 sve_init_el3(); 668 } 669 670 if (is_feat_amu_supported()) { 671 amu_init_el3(my_idx); 672 } 673 674 if (is_feat_sme_supported()) { 675 sme_init_el3(); 676 } 677 678 pmuv3_init_el3(); 679 } 680 #endif /* IMAGE_BL31 */ 681 682 /****************************************************************************** 683 * Function to initialise the registers with the RESET values in the context 684 * memory, which are maintained per world. 685 ******************************************************************************/ 686 #if IMAGE_BL31 687 void cm_el3_arch_init_per_world(per_world_context_t *per_world_ctx) 688 { 689 /* 690 * Initialise CPTR_EL3, setting all fields rather than relying on hw. 691 * 692 * CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers 693 * by Advanced SIMD, floating-point or SVE instructions (if 694 * implemented) do not trap to EL3. 695 * 696 * CPTR_EL3.TCPAC: Set to zero so that accesses to CPACR_EL1, 697 * CPTR_EL2,CPACR, or HCPTR do not trap to EL3. 698 */ 699 uint64_t cptr_el3 = CPTR_EL3_RESET_VAL & ~(TCPAC_BIT | TFP_BIT); 700 701 per_world_ctx->ctx_cptr_el3 = cptr_el3; 702 703 /* 704 * Initialize MPAM3_EL3 to its default reset value 705 * 706 * MPAM3_EL3_RESET_VAL sets the MPAM3_EL3.TRAPLOWER bit that forces 707 * all lower ELn MPAM3_EL3 register access to, trap to EL3 708 */ 709 710 per_world_ctx->ctx_mpam3_el3 = MPAM3_EL3_RESET_VAL; 711 } 712 #endif /* IMAGE_BL31 */ 713 714 /******************************************************************************* 715 * Initialise per_world_context for Non-Secure world. 716 * This function enables the architecture extensions, which have same value 717 * across the cores for the non-secure world. 718 ******************************************************************************/ 719 #if IMAGE_BL31 720 void manage_extensions_nonsecure_per_world(void) 721 { 722 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_NS]); 723 724 if (is_feat_sme_supported()) { 725 sme_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 726 } 727 728 if (is_feat_sve_supported()) { 729 sve_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 730 } 731 732 if (is_feat_amu_supported()) { 733 amu_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 734 } 735 736 if (is_feat_sys_reg_trace_supported()) { 737 sys_reg_trace_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 738 } 739 740 if (is_feat_mpam_supported()) { 741 mpam_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 742 } 743 744 if (is_feat_fpmr_supported()) { 745 fpmr_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 746 } 747 } 748 #endif /* IMAGE_BL31 */ 749 750 /******************************************************************************* 751 * Initialise per_world_context for Secure world. 752 * This function enables the architecture extensions, which have same value 753 * across the cores for the secure world. 754 ******************************************************************************/ 755 static void manage_extensions_secure_per_world(void) 756 { 757 #if IMAGE_BL31 758 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 759 760 if (is_feat_sme_supported()) { 761 762 if (ENABLE_SME_FOR_SWD) { 763 /* 764 * Enable SME, SVE, FPU/SIMD in secure context, SPM must ensure 765 * SME, SVE, and FPU/SIMD context properly managed. 766 */ 767 sme_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 768 } else { 769 /* 770 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 771 * world can safely use the associated registers. 772 */ 773 sme_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 774 } 775 } 776 if (is_feat_sve_supported()) { 777 if (ENABLE_SVE_FOR_SWD) { 778 /* 779 * Enable SVE and FPU in secure context, SPM must ensure 780 * that the SVE and FPU register contexts are properly managed. 781 */ 782 sve_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 783 } else { 784 /* 785 * Disable SVE and FPU in secure context so non-secure world 786 * can safely use them. 787 */ 788 sve_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 789 } 790 } 791 792 /* NS can access this but Secure shouldn't */ 793 if (is_feat_sys_reg_trace_supported()) { 794 sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 795 } 796 797 has_secure_perworld_init = true; 798 #endif /* IMAGE_BL31 */ 799 } 800 801 /******************************************************************************* 802 * Enable architecture extensions on first entry to Non-secure world. 803 ******************************************************************************/ 804 static void manage_extensions_nonsecure(cpu_context_t *ctx) 805 { 806 #if IMAGE_BL31 807 /* NOTE: registers are not context switched */ 808 if (is_feat_amu_supported()) { 809 amu_enable(ctx); 810 } 811 812 if (is_feat_sme_supported()) { 813 sme_enable(ctx); 814 } 815 816 if (is_feat_fgt2_supported()) { 817 fgt2_enable(ctx); 818 } 819 820 if (is_feat_debugv8p9_supported()) { 821 debugv8p9_extended_bp_wp_enable(ctx); 822 } 823 824 /* 825 * SPE, TRBE, and BRBE have multi-field enables that affect which world 826 * they apply to. Despite this, it is useful to ignore these for 827 * simplicity in determining the feature's per world enablement status. 828 * This is only possible when context is written per-world. Relied on 829 * by SMCCC_ARCH_FEATURE_AVAILABILITY 830 */ 831 if (is_feat_spe_supported()) { 832 spe_enable(ctx); 833 } 834 835 if (!check_if_trbe_disable_affected_core()) { 836 if (is_feat_trbe_supported()) { 837 trbe_enable(ctx); 838 } 839 } 840 841 if (is_feat_brbe_supported()) { 842 brbe_enable(ctx); 843 } 844 #endif /* IMAGE_BL31 */ 845 } 846 847 #if INIT_UNUSED_NS_EL2 848 /******************************************************************************* 849 * Enable architecture extensions in-place at EL2 on first entry to Non-secure 850 * world when EL2 is empty and unused. 851 ******************************************************************************/ 852 static void manage_extensions_nonsecure_el2_unused(void) 853 { 854 #if IMAGE_BL31 855 if (is_feat_spe_supported()) { 856 spe_init_el2_unused(); 857 } 858 859 if (is_feat_amu_supported()) { 860 amu_init_el2_unused(); 861 } 862 863 if (is_feat_mpam_supported()) { 864 mpam_init_el2_unused(); 865 } 866 867 if (is_feat_trbe_supported()) { 868 trbe_init_el2_unused(); 869 } 870 871 if (is_feat_sys_reg_trace_supported()) { 872 sys_reg_trace_init_el2_unused(); 873 } 874 875 if (is_feat_trf_supported()) { 876 trf_init_el2_unused(); 877 } 878 879 pmuv3_init_el2_unused(); 880 881 if (is_feat_sve_supported()) { 882 sve_init_el2_unused(); 883 } 884 885 if (is_feat_sme_supported()) { 886 sme_init_el2_unused(); 887 } 888 889 if (is_feat_mops_supported() && is_feat_hcx_supported()) { 890 write_hcrx_el2(read_hcrx_el2() | HCRX_EL2_MSCEn_BIT); 891 } 892 893 if (is_feat_pauth_supported()) { 894 pauth_enable_el2(); 895 } 896 #endif /* IMAGE_BL31 */ 897 } 898 #endif /* INIT_UNUSED_NS_EL2 */ 899 900 /******************************************************************************* 901 * Enable architecture extensions on first entry to Secure world. 902 ******************************************************************************/ 903 static void manage_extensions_secure(cpu_context_t *ctx) 904 { 905 #if IMAGE_BL31 906 if (is_feat_sme_supported()) { 907 if (ENABLE_SME_FOR_SWD) { 908 /* 909 * Enable SME, SVE, FPU/SIMD in secure context, secure manager 910 * must ensure SME, SVE, and FPU/SIMD context properly managed. 911 */ 912 sme_init_el3(); 913 sme_enable(ctx); 914 } else { 915 /* 916 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 917 * world can safely use the associated registers. 918 */ 919 sme_disable(ctx); 920 } 921 } 922 923 /* 924 * SPE and TRBE cannot be fully disabled from EL3 registers alone, only 925 * sysreg access can. In case the EL1 controls leave them active on 926 * context switch, we want the owning security state to be NS so Secure 927 * can't be DOSed. 928 */ 929 if (is_feat_spe_supported()) { 930 spe_disable(ctx); 931 } 932 933 if (is_feat_trbe_supported()) { 934 trbe_disable(ctx); 935 } 936 #endif /* IMAGE_BL31 */ 937 } 938 939 /******************************************************************************* 940 * The following function initializes the cpu_context for the current CPU 941 * for first use, and sets the initial entrypoint state as specified by the 942 * entry_point_info structure. 943 ******************************************************************************/ 944 void cm_init_my_context(const entry_point_info_t *ep) 945 { 946 cpu_context_t *ctx; 947 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 948 cm_setup_context(ctx, ep); 949 } 950 951 /* EL2 present but unused, need to disable safely. SCTLR_EL2 can be ignored */ 952 static void init_nonsecure_el2_unused(cpu_context_t *ctx) 953 { 954 #if INIT_UNUSED_NS_EL2 955 u_register_t hcr_el2 = HCR_RESET_VAL; 956 u_register_t mdcr_el2; 957 u_register_t scr_el3; 958 959 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 960 961 /* Set EL2 register width: Set HCR_EL2.RW to match SCR_EL3.RW */ 962 if ((scr_el3 & SCR_RW_BIT) != 0U) { 963 hcr_el2 |= HCR_RW_BIT; 964 } 965 966 write_hcr_el2(hcr_el2); 967 968 /* 969 * Initialise CPTR_EL2 setting all fields rather than relying on the hw. 970 * All fields have architecturally UNKNOWN reset values. 971 */ 972 write_cptr_el2(CPTR_EL2_RESET_VAL); 973 974 /* 975 * Initialise CNTHCTL_EL2. All fields are architecturally UNKNOWN on 976 * reset and are set to zero except for field(s) listed below. 977 * 978 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to Hyp mode of 979 * Non-secure EL0 and EL1 accesses to the physical timer registers. 980 * 981 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to Hyp mode of 982 * Non-secure EL0 and EL1 accesses to the physical counter registers. 983 */ 984 write_cnthctl_el2(CNTHCTL_RESET_VAL | EL1PCEN_BIT | EL1PCTEN_BIT); 985 986 /* 987 * Initialise CNTVOFF_EL2 to zero as it resets to an architecturally 988 * UNKNOWN value. 989 */ 990 write_cntvoff_el2(0); 991 992 /* 993 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and MPIDR_EL1 994 * respectively. 995 */ 996 write_vpidr_el2(read_midr_el1()); 997 write_vmpidr_el2(read_mpidr_el1()); 998 999 /* 1000 * Initialise VTTBR_EL2. All fields are architecturally UNKNOWN on reset. 1001 * 1002 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 2 address 1003 * translation is disabled, cache maintenance operations depend on the 1004 * VMID. 1005 * 1006 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address translation is 1007 * disabled. 1008 */ 1009 write_vttbr_el2(VTTBR_RESET_VAL & 1010 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) | 1011 (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 1012 1013 /* 1014 * Initialise MDCR_EL2, setting all fields rather than relying on hw. 1015 * Some fields are architecturally UNKNOWN on reset. 1016 * 1017 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and EL1 System 1018 * register accesses to the Debug ROM registers are not trapped to EL2. 1019 * 1020 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 System register 1021 * accesses to the powerdown debug registers are not trapped to EL2. 1022 * 1023 * MDCR_EL2.TDA: Set to zero so that System register accesses to the 1024 * debug registers do not trap to EL2. 1025 * 1026 * MDCR_EL2.TDE: Set to zero so that debug exceptions are not routed to 1027 * EL2. 1028 */ 1029 mdcr_el2 = MDCR_EL2_RESET_VAL & 1030 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | MDCR_EL2_TDA_BIT | 1031 MDCR_EL2_TDE_BIT); 1032 1033 write_mdcr_el2(mdcr_el2); 1034 1035 /* 1036 * Initialise HSTR_EL2. All fields are architecturally UNKNOWN on reset. 1037 * 1038 * HSTR_EL2.T<n>: Set all these fields to zero so that Non-secure EL0 or 1039 * EL1 accesses to System registers do not trap to EL2. 1040 */ 1041 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 1042 1043 /* 1044 * Initialise CNTHP_CTL_EL2. All fields are architecturally UNKNOWN on 1045 * reset. 1046 * 1047 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 physical timer 1048 * and prevent timer interrupts. 1049 */ 1050 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & ~(CNTHP_CTL_ENABLE_BIT)); 1051 1052 manage_extensions_nonsecure_el2_unused(); 1053 #endif /* INIT_UNUSED_NS_EL2 */ 1054 } 1055 1056 /******************************************************************************* 1057 * Prepare the CPU system registers for first entry into realm, secure, or 1058 * normal world. 1059 * 1060 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 1061 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 1062 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 1063 * For all entries, the EL1 registers are initialized from the cpu_context 1064 ******************************************************************************/ 1065 void cm_prepare_el3_exit(uint32_t security_state) 1066 { 1067 u_register_t sctlr_el2, scr_el3; 1068 cpu_context_t *ctx = cm_get_context(security_state); 1069 1070 assert(ctx != NULL); 1071 1072 if (security_state == NON_SECURE) { 1073 uint64_t el2_implemented = el_implemented(2); 1074 1075 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 1076 CTX_SCR_EL3); 1077 1078 if (el2_implemented != EL_IMPL_NONE) { 1079 1080 /* 1081 * If context is not being used for EL2, initialize 1082 * HCRX_EL2 with its init value here. 1083 */ 1084 if (is_feat_hcx_supported()) { 1085 write_hcrx_el2(HCRX_EL2_INIT_VAL); 1086 } 1087 1088 /* 1089 * Initialize Fine-grained trap registers introduced 1090 * by FEAT_FGT so all traps are initially disabled when 1091 * switching to EL2 or a lower EL, preventing undesired 1092 * behavior. 1093 */ 1094 if (is_feat_fgt_supported()) { 1095 /* 1096 * Initialize HFG*_EL2 registers with a default 1097 * value so legacy systems unaware of FEAT_FGT 1098 * do not get trapped due to their lack of 1099 * initialization for this feature. 1100 */ 1101 write_hfgitr_el2(HFGITR_EL2_INIT_VAL); 1102 write_hfgrtr_el2(HFGRTR_EL2_INIT_VAL); 1103 write_hfgwtr_el2(HFGWTR_EL2_INIT_VAL); 1104 } 1105 1106 /* Condition to ensure EL2 is being used. */ 1107 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 1108 /* Initialize SCTLR_EL2 register with reset value. */ 1109 sctlr_el2 = SCTLR_EL2_RES1; 1110 1111 /* 1112 * If workaround of errata 764081 for Cortex-A75 1113 * is used then set SCTLR_EL2.IESB to enable 1114 * Implicit Error Synchronization Barrier. 1115 */ 1116 if (errata_a75_764081_applies()) { 1117 sctlr_el2 |= SCTLR_IESB_BIT; 1118 } 1119 1120 write_sctlr_el2(sctlr_el2); 1121 } else { 1122 /* 1123 * (scr_el3 & SCR_HCE_BIT==0) 1124 * EL2 implemented but unused. 1125 */ 1126 init_nonsecure_el2_unused(ctx); 1127 } 1128 } 1129 } 1130 #if (!CTX_INCLUDE_EL2_REGS) 1131 /* Restore EL1 system registers, only when CTX_INCLUDE_EL2_REGS=0 */ 1132 cm_el1_sysregs_context_restore(security_state); 1133 #endif 1134 cm_set_next_eret_context(security_state); 1135 } 1136 1137 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 1138 1139 static void el2_sysregs_context_save_fgt(el2_sysregs_t *ctx) 1140 { 1141 write_el2_ctx_fgt(ctx, hdfgrtr_el2, read_hdfgrtr_el2()); 1142 if (is_feat_amu_supported()) { 1143 write_el2_ctx_fgt(ctx, hafgrtr_el2, read_hafgrtr_el2()); 1144 } 1145 write_el2_ctx_fgt(ctx, hdfgwtr_el2, read_hdfgwtr_el2()); 1146 write_el2_ctx_fgt(ctx, hfgitr_el2, read_hfgitr_el2()); 1147 write_el2_ctx_fgt(ctx, hfgrtr_el2, read_hfgrtr_el2()); 1148 write_el2_ctx_fgt(ctx, hfgwtr_el2, read_hfgwtr_el2()); 1149 } 1150 1151 static void el2_sysregs_context_restore_fgt(el2_sysregs_t *ctx) 1152 { 1153 write_hdfgrtr_el2(read_el2_ctx_fgt(ctx, hdfgrtr_el2)); 1154 if (is_feat_amu_supported()) { 1155 write_hafgrtr_el2(read_el2_ctx_fgt(ctx, hafgrtr_el2)); 1156 } 1157 write_hdfgwtr_el2(read_el2_ctx_fgt(ctx, hdfgwtr_el2)); 1158 write_hfgitr_el2(read_el2_ctx_fgt(ctx, hfgitr_el2)); 1159 write_hfgrtr_el2(read_el2_ctx_fgt(ctx, hfgrtr_el2)); 1160 write_hfgwtr_el2(read_el2_ctx_fgt(ctx, hfgwtr_el2)); 1161 } 1162 1163 static void el2_sysregs_context_save_fgt2(el2_sysregs_t *ctx) 1164 { 1165 write_el2_ctx_fgt2(ctx, hdfgrtr2_el2, read_hdfgrtr2_el2()); 1166 write_el2_ctx_fgt2(ctx, hdfgwtr2_el2, read_hdfgwtr2_el2()); 1167 write_el2_ctx_fgt2(ctx, hfgitr2_el2, read_hfgitr2_el2()); 1168 write_el2_ctx_fgt2(ctx, hfgrtr2_el2, read_hfgrtr2_el2()); 1169 write_el2_ctx_fgt2(ctx, hfgwtr2_el2, read_hfgwtr2_el2()); 1170 } 1171 1172 static void el2_sysregs_context_restore_fgt2(el2_sysregs_t *ctx) 1173 { 1174 write_hdfgrtr2_el2(read_el2_ctx_fgt2(ctx, hdfgrtr2_el2)); 1175 write_hdfgwtr2_el2(read_el2_ctx_fgt2(ctx, hdfgwtr2_el2)); 1176 write_hfgitr2_el2(read_el2_ctx_fgt2(ctx, hfgitr2_el2)); 1177 write_hfgrtr2_el2(read_el2_ctx_fgt2(ctx, hfgrtr2_el2)); 1178 write_hfgwtr2_el2(read_el2_ctx_fgt2(ctx, hfgwtr2_el2)); 1179 } 1180 1181 static void el2_sysregs_context_save_mpam(el2_sysregs_t *ctx) 1182 { 1183 u_register_t mpam_idr = read_mpamidr_el1(); 1184 1185 write_el2_ctx_mpam(ctx, mpam2_el2, read_mpam2_el2()); 1186 1187 /* 1188 * The context registers that we intend to save would be part of the 1189 * PE's system register frame only if MPAMIDR_EL1.HAS_HCR == 1. 1190 */ 1191 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1192 return; 1193 } 1194 1195 /* 1196 * MPAMHCR_EL2, MPAMVPMV_EL2 and MPAMVPM0_EL2 are always present if 1197 * MPAMIDR_HAS_HCR_BIT == 1. 1198 */ 1199 write_el2_ctx_mpam(ctx, mpamhcr_el2, read_mpamhcr_el2()); 1200 write_el2_ctx_mpam(ctx, mpamvpm0_el2, read_mpamvpm0_el2()); 1201 write_el2_ctx_mpam(ctx, mpamvpmv_el2, read_mpamvpmv_el2()); 1202 1203 /* 1204 * The number of MPAMVPM registers is implementation defined, their 1205 * number is stored in the MPAMIDR_EL1 register. 1206 */ 1207 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1208 case 7: 1209 write_el2_ctx_mpam(ctx, mpamvpm7_el2, read_mpamvpm7_el2()); 1210 __fallthrough; 1211 case 6: 1212 write_el2_ctx_mpam(ctx, mpamvpm6_el2, read_mpamvpm6_el2()); 1213 __fallthrough; 1214 case 5: 1215 write_el2_ctx_mpam(ctx, mpamvpm5_el2, read_mpamvpm5_el2()); 1216 __fallthrough; 1217 case 4: 1218 write_el2_ctx_mpam(ctx, mpamvpm4_el2, read_mpamvpm4_el2()); 1219 __fallthrough; 1220 case 3: 1221 write_el2_ctx_mpam(ctx, mpamvpm3_el2, read_mpamvpm3_el2()); 1222 __fallthrough; 1223 case 2: 1224 write_el2_ctx_mpam(ctx, mpamvpm2_el2, read_mpamvpm2_el2()); 1225 __fallthrough; 1226 case 1: 1227 write_el2_ctx_mpam(ctx, mpamvpm1_el2, read_mpamvpm1_el2()); 1228 break; 1229 } 1230 } 1231 1232 static void el2_sysregs_context_restore_mpam(el2_sysregs_t *ctx) 1233 { 1234 u_register_t mpam_idr = read_mpamidr_el1(); 1235 1236 write_mpam2_el2(read_el2_ctx_mpam(ctx, mpam2_el2)); 1237 1238 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1239 return; 1240 } 1241 1242 write_mpamhcr_el2(read_el2_ctx_mpam(ctx, mpamhcr_el2)); 1243 write_mpamvpm0_el2(read_el2_ctx_mpam(ctx, mpamvpm0_el2)); 1244 write_mpamvpmv_el2(read_el2_ctx_mpam(ctx, mpamvpmv_el2)); 1245 1246 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1247 case 7: 1248 write_mpamvpm7_el2(read_el2_ctx_mpam(ctx, mpamvpm7_el2)); 1249 __fallthrough; 1250 case 6: 1251 write_mpamvpm6_el2(read_el2_ctx_mpam(ctx, mpamvpm6_el2)); 1252 __fallthrough; 1253 case 5: 1254 write_mpamvpm5_el2(read_el2_ctx_mpam(ctx, mpamvpm5_el2)); 1255 __fallthrough; 1256 case 4: 1257 write_mpamvpm4_el2(read_el2_ctx_mpam(ctx, mpamvpm4_el2)); 1258 __fallthrough; 1259 case 3: 1260 write_mpamvpm3_el2(read_el2_ctx_mpam(ctx, mpamvpm3_el2)); 1261 __fallthrough; 1262 case 2: 1263 write_mpamvpm2_el2(read_el2_ctx_mpam(ctx, mpamvpm2_el2)); 1264 __fallthrough; 1265 case 1: 1266 write_mpamvpm1_el2(read_el2_ctx_mpam(ctx, mpamvpm1_el2)); 1267 break; 1268 } 1269 } 1270 1271 /* --------------------------------------------------------------------------- 1272 * The following registers are not added: 1273 * ICH_AP0R<n>_EL2 1274 * ICH_AP1R<n>_EL2 1275 * ICH_LR<n>_EL2 1276 * 1277 * NOTE: For a system with S-EL2 present but not enabled, accessing 1278 * ICC_SRE_EL2 is undefined from EL3. To workaround this change the 1279 * SCR_EL3.NS = 1 before accessing this register. 1280 * --------------------------------------------------------------------------- 1281 */ 1282 static void el2_sysregs_context_save_gic(el2_sysregs_t *ctx, uint32_t security_state) 1283 { 1284 u_register_t scr_el3 = read_scr_el3(); 1285 1286 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1287 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1288 #else 1289 write_scr_el3(scr_el3 | SCR_NS_BIT); 1290 isb(); 1291 1292 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1293 1294 write_scr_el3(scr_el3); 1295 isb(); 1296 #endif 1297 write_el2_ctx_common(ctx, ich_hcr_el2, read_ich_hcr_el2()); 1298 1299 if (errata_ich_vmcr_el2_applies()) { 1300 if (security_state == SECURE) { 1301 write_scr_el3(scr_el3 & ~SCR_NS_BIT); 1302 } else { 1303 write_scr_el3(scr_el3 | SCR_NS_BIT); 1304 } 1305 isb(); 1306 } 1307 1308 write_el2_ctx_common(ctx, ich_vmcr_el2, read_ich_vmcr_el2()); 1309 1310 if (errata_ich_vmcr_el2_applies()) { 1311 write_scr_el3(scr_el3); 1312 isb(); 1313 } 1314 } 1315 1316 static void el2_sysregs_context_restore_gic(el2_sysregs_t *ctx, uint32_t security_state) 1317 { 1318 u_register_t scr_el3 = read_scr_el3(); 1319 1320 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1321 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1322 #else 1323 write_scr_el3(scr_el3 | SCR_NS_BIT); 1324 isb(); 1325 1326 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1327 1328 write_scr_el3(scr_el3); 1329 isb(); 1330 #endif 1331 write_ich_hcr_el2(read_el2_ctx_common(ctx, ich_hcr_el2)); 1332 1333 if (errata_ich_vmcr_el2_applies()) { 1334 if (security_state == SECURE) { 1335 write_scr_el3(scr_el3 & ~SCR_NS_BIT); 1336 } else { 1337 write_scr_el3(scr_el3 | SCR_NS_BIT); 1338 } 1339 isb(); 1340 } 1341 1342 write_ich_vmcr_el2(read_el2_ctx_common(ctx, ich_vmcr_el2)); 1343 1344 if (errata_ich_vmcr_el2_applies()) { 1345 write_scr_el3(scr_el3); 1346 isb(); 1347 } 1348 } 1349 1350 /* ----------------------------------------------------- 1351 * The following registers are not added: 1352 * AMEVCNTVOFF0<n>_EL2 1353 * AMEVCNTVOFF1<n>_EL2 1354 * ----------------------------------------------------- 1355 */ 1356 static void el2_sysregs_context_save_common(el2_sysregs_t *ctx) 1357 { 1358 write_el2_ctx_common(ctx, actlr_el2, read_actlr_el2()); 1359 write_el2_ctx_common(ctx, afsr0_el2, read_afsr0_el2()); 1360 write_el2_ctx_common(ctx, afsr1_el2, read_afsr1_el2()); 1361 write_el2_ctx_common(ctx, amair_el2, read_amair_el2()); 1362 write_el2_ctx_common(ctx, cnthctl_el2, read_cnthctl_el2()); 1363 write_el2_ctx_common(ctx, cntvoff_el2, read_cntvoff_el2()); 1364 write_el2_ctx_common(ctx, cptr_el2, read_cptr_el2()); 1365 if (CTX_INCLUDE_AARCH32_REGS) { 1366 write_el2_ctx_common(ctx, dbgvcr32_el2, read_dbgvcr32_el2()); 1367 } 1368 write_el2_ctx_common(ctx, elr_el2, read_elr_el2()); 1369 write_el2_ctx_common(ctx, esr_el2, read_esr_el2()); 1370 write_el2_ctx_common(ctx, far_el2, read_far_el2()); 1371 write_el2_ctx_common(ctx, hacr_el2, read_hacr_el2()); 1372 write_el2_ctx_common(ctx, hcr_el2, read_hcr_el2()); 1373 write_el2_ctx_common(ctx, hpfar_el2, read_hpfar_el2()); 1374 write_el2_ctx_common(ctx, hstr_el2, read_hstr_el2()); 1375 write_el2_ctx_common(ctx, mair_el2, read_mair_el2()); 1376 write_el2_ctx_common(ctx, mdcr_el2, read_mdcr_el2()); 1377 write_el2_ctx_common(ctx, sctlr_el2, read_sctlr_el2()); 1378 write_el2_ctx_common(ctx, spsr_el2, read_spsr_el2()); 1379 write_el2_ctx_common(ctx, sp_el2, read_sp_el2()); 1380 write_el2_ctx_common(ctx, tcr_el2, read_tcr_el2()); 1381 write_el2_ctx_common(ctx, tpidr_el2, read_tpidr_el2()); 1382 write_el2_ctx_common(ctx, vbar_el2, read_vbar_el2()); 1383 write_el2_ctx_common(ctx, vmpidr_el2, read_vmpidr_el2()); 1384 write_el2_ctx_common(ctx, vpidr_el2, read_vpidr_el2()); 1385 write_el2_ctx_common(ctx, vtcr_el2, read_vtcr_el2()); 1386 1387 write_el2_ctx_common_sysreg128(ctx, ttbr0_el2, read_ttbr0_el2()); 1388 write_el2_ctx_common_sysreg128(ctx, vttbr_el2, read_vttbr_el2()); 1389 } 1390 1391 static void el2_sysregs_context_restore_common(el2_sysregs_t *ctx) 1392 { 1393 write_actlr_el2(read_el2_ctx_common(ctx, actlr_el2)); 1394 write_afsr0_el2(read_el2_ctx_common(ctx, afsr0_el2)); 1395 write_afsr1_el2(read_el2_ctx_common(ctx, afsr1_el2)); 1396 write_amair_el2(read_el2_ctx_common(ctx, amair_el2)); 1397 write_cnthctl_el2(read_el2_ctx_common(ctx, cnthctl_el2)); 1398 write_cntvoff_el2(read_el2_ctx_common(ctx, cntvoff_el2)); 1399 write_cptr_el2(read_el2_ctx_common(ctx, cptr_el2)); 1400 if (CTX_INCLUDE_AARCH32_REGS) { 1401 write_dbgvcr32_el2(read_el2_ctx_common(ctx, dbgvcr32_el2)); 1402 } 1403 write_elr_el2(read_el2_ctx_common(ctx, elr_el2)); 1404 write_esr_el2(read_el2_ctx_common(ctx, esr_el2)); 1405 write_far_el2(read_el2_ctx_common(ctx, far_el2)); 1406 write_hacr_el2(read_el2_ctx_common(ctx, hacr_el2)); 1407 write_hcr_el2(read_el2_ctx_common(ctx, hcr_el2)); 1408 write_hpfar_el2(read_el2_ctx_common(ctx, hpfar_el2)); 1409 write_hstr_el2(read_el2_ctx_common(ctx, hstr_el2)); 1410 write_mair_el2(read_el2_ctx_common(ctx, mair_el2)); 1411 write_mdcr_el2(read_el2_ctx_common(ctx, mdcr_el2)); 1412 write_sctlr_el2(read_el2_ctx_common(ctx, sctlr_el2)); 1413 write_spsr_el2(read_el2_ctx_common(ctx, spsr_el2)); 1414 write_sp_el2(read_el2_ctx_common(ctx, sp_el2)); 1415 write_tcr_el2(read_el2_ctx_common(ctx, tcr_el2)); 1416 write_tpidr_el2(read_el2_ctx_common(ctx, tpidr_el2)); 1417 write_ttbr0_el2(read_el2_ctx_common(ctx, ttbr0_el2)); 1418 write_vbar_el2(read_el2_ctx_common(ctx, vbar_el2)); 1419 write_vmpidr_el2(read_el2_ctx_common(ctx, vmpidr_el2)); 1420 write_vpidr_el2(read_el2_ctx_common(ctx, vpidr_el2)); 1421 write_vtcr_el2(read_el2_ctx_common(ctx, vtcr_el2)); 1422 write_vttbr_el2(read_el2_ctx_common(ctx, vttbr_el2)); 1423 } 1424 1425 /******************************************************************************* 1426 * Save EL2 sysreg context 1427 ******************************************************************************/ 1428 void cm_el2_sysregs_context_save(uint32_t security_state) 1429 { 1430 cpu_context_t *ctx; 1431 el2_sysregs_t *el2_sysregs_ctx; 1432 1433 ctx = cm_get_context(security_state); 1434 assert(ctx != NULL); 1435 1436 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1437 1438 el2_sysregs_context_save_common(el2_sysregs_ctx); 1439 el2_sysregs_context_save_gic(el2_sysregs_ctx, security_state); 1440 1441 if (is_feat_mte2_supported()) { 1442 write_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2, read_tfsr_el2()); 1443 } 1444 1445 if (is_feat_mpam_supported()) { 1446 el2_sysregs_context_save_mpam(el2_sysregs_ctx); 1447 } 1448 1449 if (is_feat_fgt_supported()) { 1450 el2_sysregs_context_save_fgt(el2_sysregs_ctx); 1451 } 1452 1453 if (is_feat_fgt2_supported()) { 1454 el2_sysregs_context_save_fgt2(el2_sysregs_ctx); 1455 } 1456 1457 if (is_feat_ecv_v2_supported()) { 1458 write_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2, read_cntpoff_el2()); 1459 } 1460 1461 if (is_feat_vhe_supported()) { 1462 write_el2_ctx_vhe(el2_sysregs_ctx, contextidr_el2, 1463 read_contextidr_el2()); 1464 write_el2_ctx_vhe_sysreg128(el2_sysregs_ctx, ttbr1_el2, read_ttbr1_el2()); 1465 } 1466 1467 if (is_feat_ras_supported()) { 1468 write_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2, read_vdisr_el2()); 1469 write_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2, read_vsesr_el2()); 1470 } 1471 1472 if (is_feat_nv2_supported()) { 1473 write_el2_ctx_neve(el2_sysregs_ctx, vncr_el2, read_vncr_el2()); 1474 } 1475 1476 if (is_feat_trf_supported()) { 1477 write_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2, read_trfcr_el2()); 1478 } 1479 1480 if (is_feat_csv2_2_supported()) { 1481 write_el2_ctx_csv2_2(el2_sysregs_ctx, scxtnum_el2, 1482 read_scxtnum_el2()); 1483 } 1484 1485 if (is_feat_hcx_supported()) { 1486 write_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2, read_hcrx_el2()); 1487 } 1488 1489 if (is_feat_tcr2_supported()) { 1490 write_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2, read_tcr2_el2()); 1491 } 1492 1493 if (is_feat_sxpie_supported()) { 1494 write_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2, read_pire0_el2()); 1495 write_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2, read_pir_el2()); 1496 } 1497 1498 if (is_feat_sxpoe_supported()) { 1499 write_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2, read_por_el2()); 1500 } 1501 1502 if (is_feat_brbe_supported()) { 1503 write_el2_ctx_brbe(el2_sysregs_ctx, brbcr_el2, read_brbcr_el2()); 1504 } 1505 1506 if (is_feat_s2pie_supported()) { 1507 write_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2, read_s2pir_el2()); 1508 } 1509 1510 if (is_feat_gcs_supported()) { 1511 write_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2, read_gcscr_el2()); 1512 write_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2, read_gcspr_el2()); 1513 } 1514 1515 if (is_feat_sctlr2_supported()) { 1516 write_el2_ctx_sctlr2(el2_sysregs_ctx, sctlr2_el2, read_sctlr2_el2()); 1517 } 1518 } 1519 1520 /******************************************************************************* 1521 * Restore EL2 sysreg context 1522 ******************************************************************************/ 1523 void cm_el2_sysregs_context_restore(uint32_t security_state) 1524 { 1525 cpu_context_t *ctx; 1526 el2_sysregs_t *el2_sysregs_ctx; 1527 1528 ctx = cm_get_context(security_state); 1529 assert(ctx != NULL); 1530 1531 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1532 1533 el2_sysregs_context_restore_common(el2_sysregs_ctx); 1534 el2_sysregs_context_restore_gic(el2_sysregs_ctx, security_state); 1535 1536 if (is_feat_mte2_supported()) { 1537 write_tfsr_el2(read_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2)); 1538 } 1539 1540 if (is_feat_mpam_supported()) { 1541 el2_sysregs_context_restore_mpam(el2_sysregs_ctx); 1542 } 1543 1544 if (is_feat_fgt_supported()) { 1545 el2_sysregs_context_restore_fgt(el2_sysregs_ctx); 1546 } 1547 1548 if (is_feat_fgt2_supported()) { 1549 el2_sysregs_context_restore_fgt2(el2_sysregs_ctx); 1550 } 1551 1552 if (is_feat_ecv_v2_supported()) { 1553 write_cntpoff_el2(read_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2)); 1554 } 1555 1556 if (is_feat_vhe_supported()) { 1557 write_contextidr_el2(read_el2_ctx_vhe(el2_sysregs_ctx, 1558 contextidr_el2)); 1559 write_ttbr1_el2(read_el2_ctx_vhe(el2_sysregs_ctx, ttbr1_el2)); 1560 } 1561 1562 if (is_feat_ras_supported()) { 1563 write_vdisr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2)); 1564 write_vsesr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2)); 1565 } 1566 1567 if (is_feat_nv2_supported()) { 1568 write_vncr_el2(read_el2_ctx_neve(el2_sysregs_ctx, vncr_el2)); 1569 } 1570 1571 if (is_feat_trf_supported()) { 1572 write_trfcr_el2(read_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2)); 1573 } 1574 1575 if (is_feat_csv2_2_supported()) { 1576 write_scxtnum_el2(read_el2_ctx_csv2_2(el2_sysregs_ctx, 1577 scxtnum_el2)); 1578 } 1579 1580 if (is_feat_hcx_supported()) { 1581 write_hcrx_el2(read_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2)); 1582 } 1583 1584 if (is_feat_tcr2_supported()) { 1585 write_tcr2_el2(read_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2)); 1586 } 1587 1588 if (is_feat_sxpie_supported()) { 1589 write_pire0_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2)); 1590 write_pir_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2)); 1591 } 1592 1593 if (is_feat_sxpoe_supported()) { 1594 write_por_el2(read_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2)); 1595 } 1596 1597 if (is_feat_s2pie_supported()) { 1598 write_s2pir_el2(read_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2)); 1599 } 1600 1601 if (is_feat_gcs_supported()) { 1602 write_gcscr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2)); 1603 write_gcspr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2)); 1604 } 1605 1606 if (is_feat_sctlr2_supported()) { 1607 write_sctlr2_el2(read_el2_ctx_sctlr2(el2_sysregs_ctx, sctlr2_el2)); 1608 } 1609 1610 if (is_feat_brbe_supported()) { 1611 write_brbcr_el2(read_el2_ctx_brbe(el2_sysregs_ctx, brbcr_el2)); 1612 } 1613 } 1614 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 1615 1616 /******************************************************************************* 1617 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS 1618 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly 1619 * updating EL1 and EL2 registers. Otherwise, it calls the generic 1620 * cm_prepare_el3_exit function. 1621 ******************************************************************************/ 1622 void cm_prepare_el3_exit_ns(void) 1623 { 1624 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 1625 #if ENABLE_ASSERTIONS 1626 cpu_context_t *ctx = cm_get_context(NON_SECURE); 1627 assert(ctx != NULL); 1628 1629 /* Assert that EL2 is used. */ 1630 u_register_t scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 1631 assert(((scr_el3 & SCR_HCE_BIT) != 0UL) && 1632 (el_implemented(2U) != EL_IMPL_NONE)); 1633 #endif /* ENABLE_ASSERTIONS */ 1634 1635 /* Restore EL2 sysreg contexts */ 1636 cm_el2_sysregs_context_restore(NON_SECURE); 1637 cm_set_next_eret_context(NON_SECURE); 1638 #else 1639 cm_prepare_el3_exit(NON_SECURE); 1640 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 1641 } 1642 1643 #if ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) 1644 /******************************************************************************* 1645 * The next set of six functions are used by runtime services to save and restore 1646 * EL1 context on the 'cpu_context' structure for the specified security state. 1647 ******************************************************************************/ 1648 static void el1_sysregs_context_save(el1_sysregs_t *ctx) 1649 { 1650 write_el1_ctx_common(ctx, spsr_el1, read_spsr_el1()); 1651 write_el1_ctx_common(ctx, elr_el1, read_elr_el1()); 1652 1653 #if (!ERRATA_SPECULATIVE_AT) 1654 write_el1_ctx_common(ctx, sctlr_el1, read_sctlr_el1()); 1655 write_el1_ctx_common(ctx, tcr_el1, read_tcr_el1()); 1656 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1657 1658 write_el1_ctx_common(ctx, cpacr_el1, read_cpacr_el1()); 1659 write_el1_ctx_common(ctx, csselr_el1, read_csselr_el1()); 1660 write_el1_ctx_common(ctx, sp_el1, read_sp_el1()); 1661 write_el1_ctx_common(ctx, esr_el1, read_esr_el1()); 1662 write_el1_ctx_common(ctx, mair_el1, read_mair_el1()); 1663 write_el1_ctx_common(ctx, amair_el1, read_amair_el1()); 1664 write_el1_ctx_common(ctx, actlr_el1, read_actlr_el1()); 1665 write_el1_ctx_common(ctx, tpidr_el1, read_tpidr_el1()); 1666 write_el1_ctx_common(ctx, tpidr_el0, read_tpidr_el0()); 1667 write_el1_ctx_common(ctx, tpidrro_el0, read_tpidrro_el0()); 1668 write_el1_ctx_common(ctx, far_el1, read_far_el1()); 1669 write_el1_ctx_common(ctx, afsr0_el1, read_afsr0_el1()); 1670 write_el1_ctx_common(ctx, afsr1_el1, read_afsr1_el1()); 1671 write_el1_ctx_common(ctx, contextidr_el1, read_contextidr_el1()); 1672 write_el1_ctx_common(ctx, vbar_el1, read_vbar_el1()); 1673 write_el1_ctx_common(ctx, mdccint_el1, read_mdccint_el1()); 1674 write_el1_ctx_common(ctx, mdscr_el1, read_mdscr_el1()); 1675 1676 write_el1_ctx_common_sysreg128(ctx, par_el1, read_par_el1()); 1677 write_el1_ctx_common_sysreg128(ctx, ttbr0_el1, read_ttbr0_el1()); 1678 write_el1_ctx_common_sysreg128(ctx, ttbr1_el1, read_ttbr1_el1()); 1679 1680 if (CTX_INCLUDE_AARCH32_REGS) { 1681 /* Save Aarch32 registers */ 1682 write_el1_ctx_aarch32(ctx, spsr_abt, read_spsr_abt()); 1683 write_el1_ctx_aarch32(ctx, spsr_und, read_spsr_und()); 1684 write_el1_ctx_aarch32(ctx, spsr_irq, read_spsr_irq()); 1685 write_el1_ctx_aarch32(ctx, spsr_fiq, read_spsr_fiq()); 1686 write_el1_ctx_aarch32(ctx, dacr32_el2, read_dacr32_el2()); 1687 write_el1_ctx_aarch32(ctx, ifsr32_el2, read_ifsr32_el2()); 1688 } 1689 1690 if (NS_TIMER_SWITCH) { 1691 /* Save NS Timer registers */ 1692 write_el1_ctx_arch_timer(ctx, cntp_ctl_el0, read_cntp_ctl_el0()); 1693 write_el1_ctx_arch_timer(ctx, cntp_cval_el0, read_cntp_cval_el0()); 1694 write_el1_ctx_arch_timer(ctx, cntv_ctl_el0, read_cntv_ctl_el0()); 1695 write_el1_ctx_arch_timer(ctx, cntv_cval_el0, read_cntv_cval_el0()); 1696 write_el1_ctx_arch_timer(ctx, cntkctl_el1, read_cntkctl_el1()); 1697 } 1698 1699 if (is_feat_mte2_supported()) { 1700 write_el1_ctx_mte2(ctx, tfsre0_el1, read_tfsre0_el1()); 1701 write_el1_ctx_mte2(ctx, tfsr_el1, read_tfsr_el1()); 1702 write_el1_ctx_mte2(ctx, rgsr_el1, read_rgsr_el1()); 1703 write_el1_ctx_mte2(ctx, gcr_el1, read_gcr_el1()); 1704 } 1705 1706 if (is_feat_ras_supported()) { 1707 write_el1_ctx_ras(ctx, disr_el1, read_disr_el1()); 1708 } 1709 1710 if (is_feat_s1pie_supported()) { 1711 write_el1_ctx_s1pie(ctx, pire0_el1, read_pire0_el1()); 1712 write_el1_ctx_s1pie(ctx, pir_el1, read_pir_el1()); 1713 } 1714 1715 if (is_feat_s1poe_supported()) { 1716 write_el1_ctx_s1poe(ctx, por_el1, read_por_el1()); 1717 } 1718 1719 if (is_feat_s2poe_supported()) { 1720 write_el1_ctx_s2poe(ctx, s2por_el1, read_s2por_el1()); 1721 } 1722 1723 if (is_feat_tcr2_supported()) { 1724 write_el1_ctx_tcr2(ctx, tcr2_el1, read_tcr2_el1()); 1725 } 1726 1727 if (is_feat_trf_supported()) { 1728 write_el1_ctx_trf(ctx, trfcr_el1, read_trfcr_el1()); 1729 } 1730 1731 if (is_feat_csv2_2_supported()) { 1732 write_el1_ctx_csv2_2(ctx, scxtnum_el0, read_scxtnum_el0()); 1733 write_el1_ctx_csv2_2(ctx, scxtnum_el1, read_scxtnum_el1()); 1734 } 1735 1736 if (is_feat_gcs_supported()) { 1737 write_el1_ctx_gcs(ctx, gcscr_el1, read_gcscr_el1()); 1738 write_el1_ctx_gcs(ctx, gcscre0_el1, read_gcscre0_el1()); 1739 write_el1_ctx_gcs(ctx, gcspr_el1, read_gcspr_el1()); 1740 write_el1_ctx_gcs(ctx, gcspr_el0, read_gcspr_el0()); 1741 } 1742 1743 if (is_feat_the_supported()) { 1744 write_el1_ctx_the_sysreg128(ctx, rcwmask_el1, read_rcwmask_el1()); 1745 write_el1_ctx_the_sysreg128(ctx, rcwsmask_el1, read_rcwsmask_el1()); 1746 } 1747 1748 if (is_feat_sctlr2_supported()) { 1749 write_el1_ctx_sctlr2(ctx, sctlr2_el1, read_sctlr2_el1()); 1750 } 1751 1752 if (is_feat_ls64_accdata_supported()) { 1753 write_el1_ctx_ls64(ctx, accdata_el1, read_accdata_el1()); 1754 } 1755 } 1756 1757 static void el1_sysregs_context_restore(el1_sysregs_t *ctx) 1758 { 1759 write_spsr_el1(read_el1_ctx_common(ctx, spsr_el1)); 1760 write_elr_el1(read_el1_ctx_common(ctx, elr_el1)); 1761 1762 #if (!ERRATA_SPECULATIVE_AT) 1763 write_sctlr_el1(read_el1_ctx_common(ctx, sctlr_el1)); 1764 write_tcr_el1(read_el1_ctx_common(ctx, tcr_el1)); 1765 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1766 1767 write_cpacr_el1(read_el1_ctx_common(ctx, cpacr_el1)); 1768 write_csselr_el1(read_el1_ctx_common(ctx, csselr_el1)); 1769 write_sp_el1(read_el1_ctx_common(ctx, sp_el1)); 1770 write_esr_el1(read_el1_ctx_common(ctx, esr_el1)); 1771 write_ttbr0_el1(read_el1_ctx_common(ctx, ttbr0_el1)); 1772 write_ttbr1_el1(read_el1_ctx_common(ctx, ttbr1_el1)); 1773 write_mair_el1(read_el1_ctx_common(ctx, mair_el1)); 1774 write_amair_el1(read_el1_ctx_common(ctx, amair_el1)); 1775 write_actlr_el1(read_el1_ctx_common(ctx, actlr_el1)); 1776 write_tpidr_el1(read_el1_ctx_common(ctx, tpidr_el1)); 1777 write_tpidr_el0(read_el1_ctx_common(ctx, tpidr_el0)); 1778 write_tpidrro_el0(read_el1_ctx_common(ctx, tpidrro_el0)); 1779 write_par_el1(read_el1_ctx_common(ctx, par_el1)); 1780 write_far_el1(read_el1_ctx_common(ctx, far_el1)); 1781 write_afsr0_el1(read_el1_ctx_common(ctx, afsr0_el1)); 1782 write_afsr1_el1(read_el1_ctx_common(ctx, afsr1_el1)); 1783 write_contextidr_el1(read_el1_ctx_common(ctx, contextidr_el1)); 1784 write_vbar_el1(read_el1_ctx_common(ctx, vbar_el1)); 1785 write_mdccint_el1(read_el1_ctx_common(ctx, mdccint_el1)); 1786 write_mdscr_el1(read_el1_ctx_common(ctx, mdscr_el1)); 1787 1788 if (CTX_INCLUDE_AARCH32_REGS) { 1789 /* Restore Aarch32 registers */ 1790 write_spsr_abt(read_el1_ctx_aarch32(ctx, spsr_abt)); 1791 write_spsr_und(read_el1_ctx_aarch32(ctx, spsr_und)); 1792 write_spsr_irq(read_el1_ctx_aarch32(ctx, spsr_irq)); 1793 write_spsr_fiq(read_el1_ctx_aarch32(ctx, spsr_fiq)); 1794 write_dacr32_el2(read_el1_ctx_aarch32(ctx, dacr32_el2)); 1795 write_ifsr32_el2(read_el1_ctx_aarch32(ctx, ifsr32_el2)); 1796 } 1797 1798 if (NS_TIMER_SWITCH) { 1799 /* Restore NS Timer registers */ 1800 write_cntp_ctl_el0(read_el1_ctx_arch_timer(ctx, cntp_ctl_el0)); 1801 write_cntp_cval_el0(read_el1_ctx_arch_timer(ctx, cntp_cval_el0)); 1802 write_cntv_ctl_el0(read_el1_ctx_arch_timer(ctx, cntv_ctl_el0)); 1803 write_cntv_cval_el0(read_el1_ctx_arch_timer(ctx, cntv_cval_el0)); 1804 write_cntkctl_el1(read_el1_ctx_arch_timer(ctx, cntkctl_el1)); 1805 } 1806 1807 if (is_feat_mte2_supported()) { 1808 write_tfsre0_el1(read_el1_ctx_mte2(ctx, tfsre0_el1)); 1809 write_tfsr_el1(read_el1_ctx_mte2(ctx, tfsr_el1)); 1810 write_rgsr_el1(read_el1_ctx_mte2(ctx, rgsr_el1)); 1811 write_gcr_el1(read_el1_ctx_mte2(ctx, gcr_el1)); 1812 } 1813 1814 if (is_feat_ras_supported()) { 1815 write_disr_el1(read_el1_ctx_ras(ctx, disr_el1)); 1816 } 1817 1818 if (is_feat_s1pie_supported()) { 1819 write_pire0_el1(read_el1_ctx_s1pie(ctx, pire0_el1)); 1820 write_pir_el1(read_el1_ctx_s1pie(ctx, pir_el1)); 1821 } 1822 1823 if (is_feat_s1poe_supported()) { 1824 write_por_el1(read_el1_ctx_s1poe(ctx, por_el1)); 1825 } 1826 1827 if (is_feat_s2poe_supported()) { 1828 write_s2por_el1(read_el1_ctx_s2poe(ctx, s2por_el1)); 1829 } 1830 1831 if (is_feat_tcr2_supported()) { 1832 write_tcr2_el1(read_el1_ctx_tcr2(ctx, tcr2_el1)); 1833 } 1834 1835 if (is_feat_trf_supported()) { 1836 write_trfcr_el1(read_el1_ctx_trf(ctx, trfcr_el1)); 1837 } 1838 1839 if (is_feat_csv2_2_supported()) { 1840 write_scxtnum_el0(read_el1_ctx_csv2_2(ctx, scxtnum_el0)); 1841 write_scxtnum_el1(read_el1_ctx_csv2_2(ctx, scxtnum_el1)); 1842 } 1843 1844 if (is_feat_gcs_supported()) { 1845 write_gcscr_el1(read_el1_ctx_gcs(ctx, gcscr_el1)); 1846 write_gcscre0_el1(read_el1_ctx_gcs(ctx, gcscre0_el1)); 1847 write_gcspr_el1(read_el1_ctx_gcs(ctx, gcspr_el1)); 1848 write_gcspr_el0(read_el1_ctx_gcs(ctx, gcspr_el0)); 1849 } 1850 1851 if (is_feat_the_supported()) { 1852 write_rcwmask_el1(read_el1_ctx_the(ctx, rcwmask_el1)); 1853 write_rcwsmask_el1(read_el1_ctx_the(ctx, rcwsmask_el1)); 1854 } 1855 1856 if (is_feat_sctlr2_supported()) { 1857 write_sctlr2_el1(read_el1_ctx_sctlr2(ctx, sctlr2_el1)); 1858 } 1859 1860 if (is_feat_ls64_accdata_supported()) { 1861 write_accdata_el1(read_el1_ctx_ls64(ctx, accdata_el1)); 1862 } 1863 } 1864 1865 /******************************************************************************* 1866 * The next couple of functions are used by runtime services to save and restore 1867 * EL1 context on the 'cpu_context' structure for the specified security state. 1868 ******************************************************************************/ 1869 void cm_el1_sysregs_context_save(uint32_t security_state) 1870 { 1871 cpu_context_t *ctx; 1872 1873 ctx = cm_get_context(security_state); 1874 assert(ctx != NULL); 1875 1876 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 1877 1878 #if IMAGE_BL31 1879 if (security_state == SECURE) { 1880 PUBLISH_EVENT(cm_exited_secure_world); 1881 } else { 1882 PUBLISH_EVENT(cm_exited_normal_world); 1883 } 1884 #endif 1885 } 1886 1887 void cm_el1_sysregs_context_restore(uint32_t security_state) 1888 { 1889 cpu_context_t *ctx; 1890 1891 ctx = cm_get_context(security_state); 1892 assert(ctx != NULL); 1893 1894 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 1895 1896 #if IMAGE_BL31 1897 if (security_state == SECURE) { 1898 PUBLISH_EVENT(cm_entering_secure_world); 1899 } else { 1900 PUBLISH_EVENT(cm_entering_normal_world); 1901 } 1902 #endif 1903 } 1904 1905 #endif /* ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) */ 1906 1907 /******************************************************************************* 1908 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 1909 * given security state with the given entrypoint 1910 ******************************************************************************/ 1911 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 1912 { 1913 cpu_context_t *ctx; 1914 el3_state_t *state; 1915 1916 ctx = cm_get_context(security_state); 1917 assert(ctx != NULL); 1918 1919 /* Populate EL3 state so that ERET jumps to the correct entry */ 1920 state = get_el3state_ctx(ctx); 1921 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1922 } 1923 1924 /******************************************************************************* 1925 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 1926 * pertaining to the given security state 1927 ******************************************************************************/ 1928 void cm_set_elr_spsr_el3(uint32_t security_state, 1929 uintptr_t entrypoint, uint32_t spsr) 1930 { 1931 cpu_context_t *ctx; 1932 el3_state_t *state; 1933 1934 ctx = cm_get_context(security_state); 1935 assert(ctx != NULL); 1936 1937 /* Populate EL3 state so that ERET jumps to the correct entry */ 1938 state = get_el3state_ctx(ctx); 1939 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1940 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 1941 } 1942 1943 /******************************************************************************* 1944 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 1945 * pertaining to the given security state using the value and bit position 1946 * specified in the parameters. It preserves all other bits. 1947 ******************************************************************************/ 1948 void cm_write_scr_el3_bit(uint32_t security_state, 1949 uint32_t bit_pos, 1950 uint32_t value) 1951 { 1952 cpu_context_t *ctx; 1953 el3_state_t *state; 1954 u_register_t scr_el3; 1955 1956 ctx = cm_get_context(security_state); 1957 assert(ctx != NULL); 1958 1959 /* Ensure that the bit position is a valid one */ 1960 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 1961 1962 /* Ensure that the 'value' is only a bit wide */ 1963 assert(value <= 1U); 1964 1965 /* 1966 * Get the SCR_EL3 value from the cpu context, clear the desired bit 1967 * and set it to its new value. 1968 */ 1969 state = get_el3state_ctx(ctx); 1970 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 1971 scr_el3 &= ~(1UL << bit_pos); 1972 scr_el3 |= (u_register_t)value << bit_pos; 1973 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 1974 } 1975 1976 /******************************************************************************* 1977 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 1978 * given security state. 1979 ******************************************************************************/ 1980 u_register_t cm_get_scr_el3(uint32_t security_state) 1981 { 1982 const cpu_context_t *ctx; 1983 const el3_state_t *state; 1984 1985 ctx = cm_get_context(security_state); 1986 assert(ctx != NULL); 1987 1988 /* Populate EL3 state so that ERET jumps to the correct entry */ 1989 state = get_el3state_ctx(ctx); 1990 return read_ctx_reg(state, CTX_SCR_EL3); 1991 } 1992 1993 /******************************************************************************* 1994 * This function is used to program the context that's used for exception 1995 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 1996 * the required security state 1997 ******************************************************************************/ 1998 void cm_set_next_eret_context(uint32_t security_state) 1999 { 2000 cpu_context_t *ctx; 2001 2002 ctx = cm_get_context(security_state); 2003 assert(ctx != NULL); 2004 2005 cm_set_next_context(ctx); 2006 } 2007