1 /* 2 * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 #include <string.h> 10 11 #include <platform_def.h> 12 13 #include <arch.h> 14 #include <arch_helpers.h> 15 #include <arch_features.h> 16 #include <bl31/interrupt_mgmt.h> 17 #include <common/bl_common.h> 18 #include <context.h> 19 #include <lib/el3_runtime/context_mgmt.h> 20 #include <lib/el3_runtime/pubsub_events.h> 21 #include <lib/extensions/amu.h> 22 #include <lib/extensions/mpam.h> 23 #include <lib/extensions/spe.h> 24 #include <lib/extensions/sve.h> 25 #include <lib/extensions/twed.h> 26 #include <lib/utils.h> 27 28 static void enable_extensions_secure(cpu_context_t *ctx); 29 30 /******************************************************************************* 31 * Context management library initialisation routine. This library is used by 32 * runtime services to share pointers to 'cpu_context' structures for the secure 33 * and non-secure states. Management of the structures and their associated 34 * memory is not done by the context management library e.g. the PSCI service 35 * manages the cpu context used for entry from and exit to the non-secure state. 36 * The Secure payload dispatcher service manages the context(s) corresponding to 37 * the secure state. It also uses this library to get access to the non-secure 38 * state cpu context pointers. 39 * Lastly, this library provides the api to make SP_EL3 point to the cpu context 40 * which will used for programming an entry into a lower EL. The same context 41 * will used to save state upon exception entry from that EL. 42 ******************************************************************************/ 43 void __init cm_init(void) 44 { 45 /* 46 * The context management library has only global data to intialize, but 47 * that will be done when the BSS is zeroed out 48 */ 49 } 50 51 /******************************************************************************* 52 * The following function initializes the cpu_context 'ctx' for 53 * first use, and sets the initial entrypoint state as specified by the 54 * entry_point_info structure. 55 * 56 * The security state to initialize is determined by the SECURE attribute 57 * of the entry_point_info. 58 * 59 * The EE and ST attributes are used to configure the endianness and secure 60 * timer availability for the new execution context. 61 * 62 * To prepare the register state for entry call cm_prepare_el3_exit() and 63 * el3_exit(). For Secure-EL1 cm_prepare_el3_exit() is equivalent to 64 * cm_el1_sysregs_context_restore(). 65 ******************************************************************************/ 66 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 67 { 68 unsigned int security_state; 69 u_register_t scr_el3; 70 el3_state_t *state; 71 gp_regs_t *gp_regs; 72 u_register_t sctlr_elx, actlr_elx; 73 74 assert(ctx != NULL); 75 76 security_state = GET_SECURITY_STATE(ep->h.attr); 77 78 /* Clear any residual register values from the context */ 79 zeromem(ctx, sizeof(*ctx)); 80 81 /* 82 * SCR_EL3 was initialised during reset sequence in macro 83 * el3_arch_init_common. This code modifies the SCR_EL3 fields that 84 * affect the next EL. 85 * 86 * The following fields are initially set to zero and then updated to 87 * the required value depending on the state of the SPSR_EL3 and the 88 * Security state and entrypoint attributes of the next EL. 89 */ 90 scr_el3 = read_scr(); 91 scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT | 92 SCR_ST_BIT | SCR_HCE_BIT); 93 /* 94 * SCR_NS: Set the security state of the next EL. 95 */ 96 if (security_state != SECURE) 97 scr_el3 |= SCR_NS_BIT; 98 /* 99 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 100 * Exception level as specified by SPSR. 101 */ 102 if (GET_RW(ep->spsr) == MODE_RW_64) 103 scr_el3 |= SCR_RW_BIT; 104 /* 105 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 106 * Secure timer registers to EL3, from AArch64 state only, if specified 107 * by the entrypoint attributes. 108 */ 109 if (EP_GET_ST(ep->h.attr) != 0U) 110 scr_el3 |= SCR_ST_BIT; 111 112 #if RAS_TRAP_LOWER_EL_ERR_ACCESS 113 /* 114 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 115 * and RAS ERX registers from EL1 and EL2 are trapped to EL3. 116 */ 117 scr_el3 |= SCR_TERR_BIT; 118 #endif 119 120 #if !HANDLE_EA_EL3_FIRST 121 /* 122 * SCR_EL3.EA: Do not route External Abort and SError Interrupt External 123 * to EL3 when executing at a lower EL. When executing at EL3, External 124 * Aborts are taken to EL3. 125 */ 126 scr_el3 &= ~SCR_EA_BIT; 127 #endif 128 129 #if FAULT_INJECTION_SUPPORT 130 /* Enable fault injection from lower ELs */ 131 scr_el3 |= SCR_FIEN_BIT; 132 #endif 133 134 #if !CTX_INCLUDE_PAUTH_REGS 135 /* 136 * If the pointer authentication registers aren't saved during world 137 * switches the value of the registers can be leaked from the Secure to 138 * the Non-secure world. To prevent this, rather than enabling pointer 139 * authentication everywhere, we only enable it in the Non-secure world. 140 * 141 * If the Secure world wants to use pointer authentication, 142 * CTX_INCLUDE_PAUTH_REGS must be set to 1. 143 */ 144 if (security_state == NON_SECURE) 145 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 146 #endif /* !CTX_INCLUDE_PAUTH_REGS */ 147 148 #if !CTX_INCLUDE_MTE_REGS || ENABLE_ASSERTIONS 149 /* Get Memory Tagging Extension support level */ 150 unsigned int mte = get_armv8_5_mte_support(); 151 #endif 152 /* 153 * Enable MTE support. Support is enabled unilaterally for the normal 154 * world, and only for the secure world when CTX_INCLUDE_MTE_REGS is 155 * set. 156 */ 157 #if CTX_INCLUDE_MTE_REGS 158 assert((mte == MTE_IMPLEMENTED_ELX) || (mte == MTE_IMPLEMENTED_ASY)); 159 scr_el3 |= SCR_ATA_BIT; 160 #else 161 /* 162 * When MTE is only implemented at EL0, it can be enabled 163 * across both worlds as no MTE registers are used. 164 */ 165 if ((mte == MTE_IMPLEMENTED_EL0) || 166 /* 167 * When MTE is implemented at all ELs, it can be only enabled 168 * in Non-Secure world without register saving. 169 */ 170 (((mte == MTE_IMPLEMENTED_ELX) || (mte == MTE_IMPLEMENTED_ASY)) && 171 (security_state == NON_SECURE))) { 172 scr_el3 |= SCR_ATA_BIT; 173 } 174 #endif /* CTX_INCLUDE_MTE_REGS */ 175 176 #ifdef IMAGE_BL31 177 /* 178 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 179 * indicated by the interrupt routing model for BL31. 180 */ 181 scr_el3 |= get_scr_el3_from_routing_model(security_state); 182 #endif 183 184 /* Save the initialized value of CPTR_EL3 register */ 185 write_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3, read_cptr_el3()); 186 if (security_state == SECURE) { 187 enable_extensions_secure(ctx); 188 } 189 190 /* 191 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 192 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 193 * next mode is Hyp. 194 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 195 * same conditions as HVC instructions and when the processor supports 196 * ARMv8.6-FGT. 197 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 198 * CNTPOFF_EL2 register under the same conditions as HVC instructions 199 * and when the processor supports ECV. 200 */ 201 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 202 || ((GET_RW(ep->spsr) != MODE_RW_64) 203 && (GET_M32(ep->spsr) == MODE32_hyp))) { 204 scr_el3 |= SCR_HCE_BIT; 205 206 if (is_armv8_6_fgt_present()) { 207 scr_el3 |= SCR_FGTEN_BIT; 208 } 209 210 if (get_armv8_6_ecv_support() 211 == ID_AA64MMFR0_EL1_ECV_SELF_SYNCH) { 212 scr_el3 |= SCR_ECVEN_BIT; 213 } 214 } 215 216 /* Enable S-EL2 if the next EL is EL2 and security state is secure */ 217 if ((security_state == SECURE) && (GET_EL(ep->spsr) == MODE_EL2)) { 218 if (GET_RW(ep->spsr) != MODE_RW_64) { 219 ERROR("S-EL2 can not be used in AArch32."); 220 panic(); 221 } 222 223 scr_el3 |= SCR_EEL2_BIT; 224 } 225 226 /* 227 * FEAT_AMUv1p1 virtual offset registers are only accessible from EL3 228 * and EL2, when clear, this bit traps accesses from EL2 so we set it 229 * to 1 when EL2 is present. 230 */ 231 if (is_armv8_6_feat_amuv1p1_present() && 232 (el_implemented(2) != EL_IMPL_NONE)) { 233 scr_el3 |= SCR_AMVOFFEN_BIT; 234 } 235 236 /* 237 * Initialise SCTLR_EL1 to the reset value corresponding to the target 238 * execution state setting all fields rather than relying of the hw. 239 * Some fields have architecturally UNKNOWN reset values and these are 240 * set to zero. 241 * 242 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 243 * 244 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 245 * required by PSCI specification) 246 */ 247 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0U; 248 if (GET_RW(ep->spsr) == MODE_RW_64) 249 sctlr_elx |= SCTLR_EL1_RES1; 250 else { 251 /* 252 * If the target execution state is AArch32 then the following 253 * fields need to be set. 254 * 255 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 256 * instructions are not trapped to EL1. 257 * 258 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 259 * instructions are not trapped to EL1. 260 * 261 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 262 * CP15DMB, CP15DSB, and CP15ISB instructions. 263 */ 264 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 265 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 266 } 267 268 #if ERRATA_A75_764081 269 /* 270 * If workaround of errata 764081 for Cortex-A75 is used then set 271 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 272 */ 273 sctlr_elx |= SCTLR_IESB_BIT; 274 #endif 275 276 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 277 if (is_armv8_6_twed_present()) { 278 uint32_t delay = plat_arm_set_twedel_scr_el3(); 279 280 if (delay != TWED_DISABLED) { 281 /* Make sure delay value fits */ 282 assert((delay & ~SCR_TWEDEL_MASK) == 0U); 283 284 /* Set delay in SCR_EL3 */ 285 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 286 scr_el3 |= ((delay & SCR_TWEDEL_MASK) 287 << SCR_TWEDEL_SHIFT); 288 289 /* Enable WFE delay */ 290 scr_el3 |= SCR_TWEDEn_BIT; 291 } 292 } 293 294 /* 295 * Store the initialised SCTLR_EL1 value in the cpu_context - SCTLR_EL2 296 * and other EL2 registers are set up by cm_prepare_el3_exit() as they 297 * are not part of the stored cpu_context. 298 */ 299 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); 300 301 /* 302 * Base the context ACTLR_EL1 on the current value, as it is 303 * implementation defined. The context restore process will write 304 * the value from the context to the actual register and can cause 305 * problems for processor cores that don't expect certain bits to 306 * be zero. 307 */ 308 actlr_elx = read_actlr_el1(); 309 write_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx)); 310 311 /* 312 * Populate EL3 state so that we've the right context 313 * before doing ERET 314 */ 315 state = get_el3state_ctx(ctx); 316 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 317 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 318 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 319 320 /* 321 * Store the X0-X7 value from the entrypoint into the context 322 * Use memcpy as we are in control of the layout of the structures 323 */ 324 gp_regs = get_gpregs_ctx(ctx); 325 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 326 } 327 328 /******************************************************************************* 329 * Enable architecture extensions on first entry to Non-secure world. 330 * When EL2 is implemented but unused `el2_unused` is non-zero, otherwise 331 * it is zero. 332 ******************************************************************************/ 333 static void enable_extensions_nonsecure(bool el2_unused, cpu_context_t *ctx) 334 { 335 #if IMAGE_BL31 336 #if ENABLE_SPE_FOR_LOWER_ELS 337 spe_enable(el2_unused); 338 #endif 339 340 #if ENABLE_AMU 341 amu_enable(el2_unused, ctx); 342 #endif 343 344 #if ENABLE_SVE_FOR_NS 345 sve_enable(ctx); 346 #endif 347 348 #if ENABLE_MPAM_FOR_LOWER_ELS 349 mpam_enable(el2_unused); 350 #endif 351 #endif 352 } 353 354 /******************************************************************************* 355 * Enable architecture extensions on first entry to Secure world. 356 ******************************************************************************/ 357 static void enable_extensions_secure(cpu_context_t *ctx) 358 { 359 #if IMAGE_BL31 360 #if ENABLE_SVE_FOR_SWD 361 sve_enable(ctx); 362 #endif 363 #endif 364 } 365 366 /******************************************************************************* 367 * The following function initializes the cpu_context for a CPU specified by 368 * its `cpu_idx` for first use, and sets the initial entrypoint state as 369 * specified by the entry_point_info structure. 370 ******************************************************************************/ 371 void cm_init_context_by_index(unsigned int cpu_idx, 372 const entry_point_info_t *ep) 373 { 374 cpu_context_t *ctx; 375 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 376 cm_setup_context(ctx, ep); 377 } 378 379 /******************************************************************************* 380 * The following function initializes the cpu_context for the current CPU 381 * for first use, and sets the initial entrypoint state as specified by the 382 * entry_point_info structure. 383 ******************************************************************************/ 384 void cm_init_my_context(const entry_point_info_t *ep) 385 { 386 cpu_context_t *ctx; 387 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 388 cm_setup_context(ctx, ep); 389 } 390 391 /******************************************************************************* 392 * Prepare the CPU system registers for first entry into secure or normal world 393 * 394 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 395 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 396 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 397 * For all entries, the EL1 registers are initialized from the cpu_context 398 ******************************************************************************/ 399 void cm_prepare_el3_exit(uint32_t security_state) 400 { 401 u_register_t sctlr_elx, scr_el3, mdcr_el2; 402 cpu_context_t *ctx = cm_get_context(security_state); 403 bool el2_unused = false; 404 uint64_t hcr_el2 = 0U; 405 406 assert(ctx != NULL); 407 408 if (security_state == NON_SECURE) { 409 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 410 CTX_SCR_EL3); 411 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 412 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */ 413 sctlr_elx = read_ctx_reg(get_el1_sysregs_ctx(ctx), 414 CTX_SCTLR_EL1); 415 sctlr_elx &= SCTLR_EE_BIT; 416 sctlr_elx |= SCTLR_EL2_RES1; 417 #if ERRATA_A75_764081 418 /* 419 * If workaround of errata 764081 for Cortex-A75 is used 420 * then set SCTLR_EL2.IESB to enable Implicit Error 421 * Synchronization Barrier. 422 */ 423 sctlr_elx |= SCTLR_IESB_BIT; 424 #endif 425 write_sctlr_el2(sctlr_elx); 426 } else if (el_implemented(2) != EL_IMPL_NONE) { 427 el2_unused = true; 428 429 /* 430 * EL2 present but unused, need to disable safely. 431 * SCTLR_EL2 can be ignored in this case. 432 * 433 * Set EL2 register width appropriately: Set HCR_EL2 434 * field to match SCR_EL3.RW. 435 */ 436 if ((scr_el3 & SCR_RW_BIT) != 0U) 437 hcr_el2 |= HCR_RW_BIT; 438 439 /* 440 * For Armv8.3 pointer authentication feature, disable 441 * traps to EL2 when accessing key registers or using 442 * pointer authentication instructions from lower ELs. 443 */ 444 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 445 446 write_hcr_el2(hcr_el2); 447 448 /* 449 * Initialise CPTR_EL2 setting all fields rather than 450 * relying on the hw. All fields have architecturally 451 * UNKNOWN reset values. 452 * 453 * CPTR_EL2.TCPAC: Set to zero so that Non-secure EL1 454 * accesses to the CPACR_EL1 or CPACR from both 455 * Execution states do not trap to EL2. 456 * 457 * CPTR_EL2.TTA: Set to zero so that Non-secure System 458 * register accesses to the trace registers from both 459 * Execution states do not trap to EL2. 460 * 461 * CPTR_EL2.TFP: Set to zero so that Non-secure accesses 462 * to SIMD and floating-point functionality from both 463 * Execution states do not trap to EL2. 464 */ 465 write_cptr_el2(CPTR_EL2_RESET_VAL & 466 ~(CPTR_EL2_TCPAC_BIT | CPTR_EL2_TTA_BIT 467 | CPTR_EL2_TFP_BIT)); 468 469 /* 470 * Initialise CNTHCTL_EL2. All fields are 471 * architecturally UNKNOWN on reset and are set to zero 472 * except for field(s) listed below. 473 * 474 * CNTHCTL_EL2.EL1PCEN: Set to one to disable traps to 475 * Hyp mode of Non-secure EL0 and EL1 accesses to the 476 * physical timer registers. 477 * 478 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to 479 * Hyp mode of Non-secure EL0 and EL1 accesses to the 480 * physical counter registers. 481 */ 482 write_cnthctl_el2(CNTHCTL_RESET_VAL | 483 EL1PCEN_BIT | EL1PCTEN_BIT); 484 485 /* 486 * Initialise CNTVOFF_EL2 to zero as it resets to an 487 * architecturally UNKNOWN value. 488 */ 489 write_cntvoff_el2(0); 490 491 /* 492 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and 493 * MPIDR_EL1 respectively. 494 */ 495 write_vpidr_el2(read_midr_el1()); 496 write_vmpidr_el2(read_mpidr_el1()); 497 498 /* 499 * Initialise VTTBR_EL2. All fields are architecturally 500 * UNKNOWN on reset. 501 * 502 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 503 * 2 address translation is disabled, cache maintenance 504 * operations depend on the VMID. 505 * 506 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address 507 * translation is disabled. 508 */ 509 write_vttbr_el2(VTTBR_RESET_VAL & 510 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) 511 | (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 512 513 /* 514 * Initialise MDCR_EL2, setting all fields rather than 515 * relying on hw. Some fields are architecturally 516 * UNKNOWN on reset. 517 * 518 * MDCR_EL2.HLP: Set to one so that event counter 519 * overflow, that is recorded in PMOVSCLR_EL0[0-30], 520 * occurs on the increment that changes 521 * PMEVCNTR<n>_EL0[63] from 1 to 0, when ARMv8.5-PMU is 522 * implemented. This bit is RES0 in versions of the 523 * architecture earlier than ARMv8.5, setting it to 1 524 * doesn't have any effect on them. 525 * 526 * MDCR_EL2.TTRF: Set to zero so that access to Trace 527 * Filter Control register TRFCR_EL1 at EL1 is not 528 * trapped to EL2. This bit is RES0 in versions of 529 * the architecture earlier than ARMv8.4. 530 * 531 * MDCR_EL2.HPMD: Set to one so that event counting is 532 * prohibited at EL2. This bit is RES0 in versions of 533 * the architecture earlier than ARMv8.1, setting it 534 * to 1 doesn't have any effect on them. 535 * 536 * MDCR_EL2.TPMS: Set to zero so that accesses to 537 * Statistical Profiling control registers from EL1 538 * do not trap to EL2. This bit is RES0 when SPE is 539 * not implemented. 540 * 541 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and 542 * EL1 System register accesses to the Debug ROM 543 * registers are not trapped to EL2. 544 * 545 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 546 * System register accesses to the powerdown debug 547 * registers are not trapped to EL2. 548 * 549 * MDCR_EL2.TDA: Set to zero so that System register 550 * accesses to the debug registers do not trap to EL2. 551 * 552 * MDCR_EL2.TDE: Set to zero so that debug exceptions 553 * are not routed to EL2. 554 * 555 * MDCR_EL2.HPME: Set to zero to disable EL2 Performance 556 * Monitors. 557 * 558 * MDCR_EL2.TPM: Set to zero so that Non-secure EL0 and 559 * EL1 accesses to all Performance Monitors registers 560 * are not trapped to EL2. 561 * 562 * MDCR_EL2.TPMCR: Set to zero so that Non-secure EL0 563 * and EL1 accesses to the PMCR_EL0 or PMCR are not 564 * trapped to EL2. 565 * 566 * MDCR_EL2.HPMN: Set to value of PMCR_EL0.N which is the 567 * architecturally-defined reset value. 568 */ 569 mdcr_el2 = ((MDCR_EL2_RESET_VAL | MDCR_EL2_HLP | 570 MDCR_EL2_HPMD) | 571 ((read_pmcr_el0() & PMCR_EL0_N_BITS) 572 >> PMCR_EL0_N_SHIFT)) & 573 ~(MDCR_EL2_TTRF | MDCR_EL2_TPMS | 574 MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | 575 MDCR_EL2_TDA_BIT | MDCR_EL2_TDE_BIT | 576 MDCR_EL2_HPME_BIT | MDCR_EL2_TPM_BIT | 577 MDCR_EL2_TPMCR_BIT); 578 579 write_mdcr_el2(mdcr_el2); 580 581 /* 582 * Initialise HSTR_EL2. All fields are architecturally 583 * UNKNOWN on reset. 584 * 585 * HSTR_EL2.T<n>: Set all these fields to zero so that 586 * Non-secure EL0 or EL1 accesses to System registers 587 * do not trap to EL2. 588 */ 589 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 590 /* 591 * Initialise CNTHP_CTL_EL2. All fields are 592 * architecturally UNKNOWN on reset. 593 * 594 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 595 * physical timer and prevent timer interrupts. 596 */ 597 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & 598 ~(CNTHP_CTL_ENABLE_BIT)); 599 } 600 enable_extensions_nonsecure(el2_unused, ctx); 601 } 602 603 cm_el1_sysregs_context_restore(security_state); 604 cm_set_next_eret_context(security_state); 605 } 606 607 #if CTX_INCLUDE_EL2_REGS 608 /******************************************************************************* 609 * Save EL2 sysreg context 610 ******************************************************************************/ 611 void cm_el2_sysregs_context_save(uint32_t security_state) 612 { 613 u_register_t scr_el3 = read_scr(); 614 615 /* 616 * Always save the non-secure EL2 context, only save the 617 * S-EL2 context if S-EL2 is enabled. 618 */ 619 if ((security_state == NON_SECURE) || 620 ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) { 621 cpu_context_t *ctx; 622 623 ctx = cm_get_context(security_state); 624 assert(ctx != NULL); 625 626 el2_sysregs_context_save(get_el2_sysregs_ctx(ctx)); 627 } 628 } 629 630 /******************************************************************************* 631 * Restore EL2 sysreg context 632 ******************************************************************************/ 633 void cm_el2_sysregs_context_restore(uint32_t security_state) 634 { 635 u_register_t scr_el3 = read_scr(); 636 637 /* 638 * Always restore the non-secure EL2 context, only restore the 639 * S-EL2 context if S-EL2 is enabled. 640 */ 641 if ((security_state == NON_SECURE) || 642 ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) { 643 cpu_context_t *ctx; 644 645 ctx = cm_get_context(security_state); 646 assert(ctx != NULL); 647 648 el2_sysregs_context_restore(get_el2_sysregs_ctx(ctx)); 649 } 650 } 651 #endif /* CTX_INCLUDE_EL2_REGS */ 652 653 /******************************************************************************* 654 * The next four functions are used by runtime services to save and restore 655 * EL1 context on the 'cpu_context' structure for the specified security 656 * state. 657 ******************************************************************************/ 658 void cm_el1_sysregs_context_save(uint32_t security_state) 659 { 660 cpu_context_t *ctx; 661 662 ctx = cm_get_context(security_state); 663 assert(ctx != NULL); 664 665 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 666 667 #if IMAGE_BL31 668 if (security_state == SECURE) 669 PUBLISH_EVENT(cm_exited_secure_world); 670 else 671 PUBLISH_EVENT(cm_exited_normal_world); 672 #endif 673 } 674 675 void cm_el1_sysregs_context_restore(uint32_t security_state) 676 { 677 cpu_context_t *ctx; 678 679 ctx = cm_get_context(security_state); 680 assert(ctx != NULL); 681 682 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 683 684 #if IMAGE_BL31 685 if (security_state == SECURE) 686 PUBLISH_EVENT(cm_entering_secure_world); 687 else 688 PUBLISH_EVENT(cm_entering_normal_world); 689 #endif 690 } 691 692 /******************************************************************************* 693 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 694 * given security state with the given entrypoint 695 ******************************************************************************/ 696 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 697 { 698 cpu_context_t *ctx; 699 el3_state_t *state; 700 701 ctx = cm_get_context(security_state); 702 assert(ctx != NULL); 703 704 /* Populate EL3 state so that ERET jumps to the correct entry */ 705 state = get_el3state_ctx(ctx); 706 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 707 } 708 709 /******************************************************************************* 710 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 711 * pertaining to the given security state 712 ******************************************************************************/ 713 void cm_set_elr_spsr_el3(uint32_t security_state, 714 uintptr_t entrypoint, uint32_t spsr) 715 { 716 cpu_context_t *ctx; 717 el3_state_t *state; 718 719 ctx = cm_get_context(security_state); 720 assert(ctx != NULL); 721 722 /* Populate EL3 state so that ERET jumps to the correct entry */ 723 state = get_el3state_ctx(ctx); 724 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 725 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 726 } 727 728 /******************************************************************************* 729 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 730 * pertaining to the given security state using the value and bit position 731 * specified in the parameters. It preserves all other bits. 732 ******************************************************************************/ 733 void cm_write_scr_el3_bit(uint32_t security_state, 734 uint32_t bit_pos, 735 uint32_t value) 736 { 737 cpu_context_t *ctx; 738 el3_state_t *state; 739 u_register_t scr_el3; 740 741 ctx = cm_get_context(security_state); 742 assert(ctx != NULL); 743 744 /* Ensure that the bit position is a valid one */ 745 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 746 747 /* Ensure that the 'value' is only a bit wide */ 748 assert(value <= 1U); 749 750 /* 751 * Get the SCR_EL3 value from the cpu context, clear the desired bit 752 * and set it to its new value. 753 */ 754 state = get_el3state_ctx(ctx); 755 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 756 scr_el3 &= ~(1UL << bit_pos); 757 scr_el3 |= (u_register_t)value << bit_pos; 758 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 759 } 760 761 /******************************************************************************* 762 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 763 * given security state. 764 ******************************************************************************/ 765 u_register_t cm_get_scr_el3(uint32_t security_state) 766 { 767 cpu_context_t *ctx; 768 el3_state_t *state; 769 770 ctx = cm_get_context(security_state); 771 assert(ctx != NULL); 772 773 /* Populate EL3 state so that ERET jumps to the correct entry */ 774 state = get_el3state_ctx(ctx); 775 return read_ctx_reg(state, CTX_SCR_EL3); 776 } 777 778 /******************************************************************************* 779 * This function is used to program the context that's used for exception 780 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 781 * the required security state 782 ******************************************************************************/ 783 void cm_set_next_eret_context(uint32_t security_state) 784 { 785 cpu_context_t *ctx; 786 787 ctx = cm_get_context(security_state); 788 assert(ctx != NULL); 789 790 cm_set_next_context(ctx); 791 } 792