1/* 2 * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <assert_macros.S> 10#include <context.h> 11#include <el3_common_macros.S> 12#include <platform_def.h> 13 14#if CTX_INCLUDE_FPREGS 15 .global fpregs_context_save 16 .global fpregs_context_restore 17#endif /* CTX_INCLUDE_FPREGS */ 18 19#if CTX_INCLUDE_SVE_REGS 20 .global sve_context_save 21 .global sve_context_restore 22#endif /* CTX_INCLUDE_SVE_REGS */ 23 24#if ERRATA_SPECULATIVE_AT 25 .global save_and_update_ptw_el1_sys_regs 26#endif /* ERRATA_SPECULATIVE_AT */ 27 28 .global prepare_el3_entry 29 .global restore_gp_pmcr_pauth_regs 30 .global el3_exit 31 32/* Following macros will be used if any of CTX_INCLUDE_FPREGS or CTX_INCLUDE_SVE_REGS is enabled */ 33#if CTX_INCLUDE_FPREGS || CTX_INCLUDE_SVE_REGS 34.macro fpregs_state_save base:req hold:req 35 mrs \hold, fpsr 36 str \hold, [\base, #CTX_SIMD_FPSR] 37 38 mrs \hold, fpcr 39 str \hold, [\base, #CTX_SIMD_FPCR] 40 41#if CTX_INCLUDE_AARCH32_REGS && CTX_INCLUDE_FPREGS 42 mrs \hold, fpexc32_el2 43 str \hold, [\base, #CTX_SIMD_FPEXC32] 44#endif 45.endm 46 47.macro fpregs_state_restore base:req hold:req 48 ldr \hold, [\base, #CTX_SIMD_FPSR] 49 msr fpsr, \hold 50 51 ldr \hold, [\base, #CTX_SIMD_FPCR] 52 msr fpcr, \hold 53 54#if CTX_INCLUDE_AARCH32_REGS && CTX_INCLUDE_FPREGS 55 ldr \hold, [\base, #CTX_SIMD_FPEXC32] 56 msr fpexc32_el2, \hold 57#endif 58.endm 59 60#endif /* CTX_INCLUDE_FPREGS || CTX_INCLUDE_SVE_REGS */ 61 62/* ------------------------------------------------------------------ 63 * The following function follows the aapcs_64 strictly to use 64 * x9-x17 (temporary caller-saved registers according to AArch64 PCS) 65 * to save floating point register context. It assumes that 'x0' is 66 * pointing to a 'fp_regs' structure where the register context will 67 * be saved. 68 * 69 * Access to VFP registers will trap if CPTR_EL3.TFP is set. 70 * However currently we don't use VFP registers nor set traps in 71 * Trusted Firmware, and assume it's cleared. 72 * 73 * TODO: Revisit when VFP is used in secure world 74 * ------------------------------------------------------------------ 75 */ 76#if CTX_INCLUDE_FPREGS 77func fpregs_context_save 78 stp q0, q1, [x0], #32 79 stp q2, q3, [x0], #32 80 stp q4, q5, [x0], #32 81 stp q6, q7, [x0], #32 82 stp q8, q9, [x0], #32 83 stp q10, q11, [x0], #32 84 stp q12, q13, [x0], #32 85 stp q14, q15, [x0], #32 86 stp q16, q17, [x0], #32 87 stp q18, q19, [x0], #32 88 stp q20, q21, [x0], #32 89 stp q22, q23, [x0], #32 90 stp q24, q25, [x0], #32 91 stp q26, q27, [x0], #32 92 stp q28, q29, [x0], #32 93 stp q30, q31, [x0], #32 94 95 fpregs_state_save x0, x9 96 97 ret 98endfunc fpregs_context_save 99 100/* ------------------------------------------------------------------ 101 * The following function follows the aapcs_64 strictly to use x9-x17 102 * (temporary caller-saved registers according to AArch64 PCS) to 103 * restore floating point register context. It assumes that 'x0' is 104 * pointing to a 'fp_regs' structure from where the register context 105 * will be restored. 106 * 107 * Access to VFP registers will trap if CPTR_EL3.TFP is set. 108 * However currently we don't use VFP registers nor set traps in 109 * Trusted Firmware, and assume it's cleared. 110 * 111 * TODO: Revisit when VFP is used in secure world 112 * ------------------------------------------------------------------ 113 */ 114func fpregs_context_restore 115 ldp q0, q1, [x0], #32 116 ldp q2, q3, [x0], #32 117 ldp q4, q5, [x0], #32 118 ldp q6, q7, [x0], #32 119 ldp q8, q9, [x0], #32 120 ldp q10, q11, [x0], #32 121 ldp q12, q13, [x0], #32 122 ldp q14, q15, [x0], #32 123 ldp q16, q17, [x0], #32 124 ldp q18, q19, [x0], #32 125 ldp q20, q21, [x0], #32 126 ldp q22, q23, [x0], #32 127 ldp q24, q25, [x0], #32 128 ldp q26, q27, [x0], #32 129 ldp q28, q29, [x0], #32 130 ldp q30, q31, [x0], #32 131 132 fpregs_state_restore x0, x9 133 134 ret 135endfunc fpregs_context_restore 136#endif /* CTX_INCLUDE_FPREGS */ 137 138#if CTX_INCLUDE_SVE_REGS 139/* 140 * Helper macros for SVE predicates save/restore operations. 141 */ 142.macro sve_predicate_op op:req reg:req 143 \op p0, [\reg, #0, MUL VL] 144 \op p1, [\reg, #1, MUL VL] 145 \op p2, [\reg, #2, MUL VL] 146 \op p3, [\reg, #3, MUL VL] 147 \op p4, [\reg, #4, MUL VL] 148 \op p5, [\reg, #5, MUL VL] 149 \op p6, [\reg, #6, MUL VL] 150 \op p7, [\reg, #7, MUL VL] 151 \op p8, [\reg, #8, MUL VL] 152 \op p9, [\reg, #9, MUL VL] 153 \op p10, [\reg, #10, MUL VL] 154 \op p11, [\reg, #11, MUL VL] 155 \op p12, [\reg, #12, MUL VL] 156 \op p13, [\reg, #13, MUL VL] 157 \op p14, [\reg, #14, MUL VL] 158 \op p15, [\reg, #15, MUL VL] 159.endm 160 161.macro sve_vectors_op op:req reg:req 162 \op z0, [\reg, #0, MUL VL] 163 \op z1, [\reg, #1, MUL VL] 164 \op z2, [\reg, #2, MUL VL] 165 \op z3, [\reg, #3, MUL VL] 166 \op z4, [\reg, #4, MUL VL] 167 \op z5, [\reg, #5, MUL VL] 168 \op z6, [\reg, #6, MUL VL] 169 \op z7, [\reg, #7, MUL VL] 170 \op z8, [\reg, #8, MUL VL] 171 \op z9, [\reg, #9, MUL VL] 172 \op z10, [\reg, #10, MUL VL] 173 \op z11, [\reg, #11, MUL VL] 174 \op z12, [\reg, #12, MUL VL] 175 \op z13, [\reg, #13, MUL VL] 176 \op z14, [\reg, #14, MUL VL] 177 \op z15, [\reg, #15, MUL VL] 178 \op z16, [\reg, #16, MUL VL] 179 \op z17, [\reg, #17, MUL VL] 180 \op z18, [\reg, #18, MUL VL] 181 \op z19, [\reg, #19, MUL VL] 182 \op z20, [\reg, #20, MUL VL] 183 \op z21, [\reg, #21, MUL VL] 184 \op z22, [\reg, #22, MUL VL] 185 \op z23, [\reg, #23, MUL VL] 186 \op z24, [\reg, #24, MUL VL] 187 \op z25, [\reg, #25, MUL VL] 188 \op z26, [\reg, #26, MUL VL] 189 \op z27, [\reg, #27, MUL VL] 190 \op z28, [\reg, #28, MUL VL] 191 \op z29, [\reg, #29, MUL VL] 192 \op z30, [\reg, #30, MUL VL] 193 \op z31, [\reg, #31, MUL VL] 194.endm 195 196/* ------------------------------------------------------------------ 197 * The following function follows the aapcs_64 strictly to use x9-x17 198 * (temporary caller-saved registers according to AArch64 PCS) to 199 * restore SVE register context. It assumes that 'x0' is 200 * pointing to a 'sve_regs_t' structure to which the register context 201 * will be saved. 202 * ------------------------------------------------------------------ 203 */ 204func sve_context_save 205.arch_extension sve 206 /* Temporarily enable SVE */ 207 mrs x10, cptr_el3 208 orr x11, x10, #CPTR_EZ_BIT 209 bic x11, x11, #TFP_BIT 210 msr cptr_el3, x11 211 isb 212 213 /* zcr_el3 */ 214 mrs x12, S3_6_C1_C2_0 215 mov x13, #((SVE_VECTOR_LEN >> 7) - 1) 216 msr S3_6_C1_C2_0, x13 217 isb 218 219 /* Predicate registers */ 220 mov x13, #CTX_SIMD_PREDICATES 221 add x9, x0, x13 222 sve_predicate_op str, x9 223 224 /* Save FFR after predicates */ 225 mov x13, #CTX_SIMD_FFR 226 add x9, x0, x13 227 rdffr p0.b 228 str p0, [x9] 229 230 /* Save vector registers */ 231 mov x13, #CTX_SIMD_VECTORS 232 add x9, x0, x13 233 sve_vectors_op str, x9 234 235 /* Restore SVE enablement */ 236 msr S3_6_C1_C2_0, x12 /* zcr_el3 */ 237 msr cptr_el3, x10 238 isb 239.arch_extension nosve 240 241 /* Save FPSR, FPCR and FPEXC32 */ 242 fpregs_state_save x0, x9 243 244 ret 245endfunc sve_context_save 246 247/* ------------------------------------------------------------------ 248 * The following function follows the aapcs_64 strictly to use x9-x17 249 * (temporary caller-saved registers according to AArch64 PCS) to 250 * restore SVE register context. It assumes that 'x0' is pointing to 251 * a 'sve_regs_t' structure from where the register context will be 252 * restored. 253 * ------------------------------------------------------------------ 254 */ 255func sve_context_restore 256.arch_extension sve 257 /* Temporarily enable SVE for EL3 */ 258 mrs x10, cptr_el3 259 orr x11, x10, #CPTR_EZ_BIT 260 bic x11, x11, #TFP_BIT 261 msr cptr_el3, x11 262 isb 263 264 /* zcr_el3 */ 265 mrs x12, S3_6_C1_C2_0 266 mov x13, #((SVE_VECTOR_LEN >> 7) - 1) 267 msr S3_6_C1_C2_0, x13 268 isb 269 270 /* Restore FFR register before predicates */ 271 mov x13, #CTX_SIMD_FFR 272 add x9, x0, x13 273 ldr p0, [x9] 274 wrffr p0.b 275 276 /* Restore predicate registers */ 277 mov x13, #CTX_SIMD_PREDICATES 278 add x9, x0, x13 279 sve_predicate_op ldr, x9 280 281 /* Restore vector registers */ 282 mov x13, #CTX_SIMD_VECTORS 283 add x9, x0, x13 284 sve_vectors_op ldr, x9 285 286 /* Restore SVE enablement */ 287 msr S3_6_C1_C2_0, x12 /* zcr_el3 */ 288 msr cptr_el3, x10 289 isb 290.arch_extension nosve 291 292 /* Restore FPSR, FPCR and FPEXC32 */ 293 fpregs_state_restore x0, x9 294 ret 295endfunc sve_context_restore 296#endif /* CTX_INCLUDE_SVE_REGS */ 297 298 /* 299 * Set SCR_EL3.EA bit to enable SErrors at EL3 300 */ 301 .macro enable_serror_at_el3 302 mrs x8, scr_el3 303 orr x8, x8, #SCR_EA_BIT 304 msr scr_el3, x8 305 .endm 306 307 /* 308 * Set the PSTATE bits not set when the exception was taken as 309 * described in the AArch64.TakeException() pseudocode function 310 * in ARM DDI 0487F.c page J1-7635 to a default value. 311 */ 312 .macro set_unset_pstate_bits 313 /* 314 * If Data Independent Timing (DIT) functionality is implemented, 315 * always enable DIT in EL3 316 */ 317#if ENABLE_FEAT_DIT 318#if ENABLE_FEAT_DIT == 2 319 mrs x8, id_aa64pfr0_el1 320 and x8, x8, #(ID_AA64PFR0_DIT_MASK << ID_AA64PFR0_DIT_SHIFT) 321 cbz x8, 1f 322#endif 323 mov x8, #DIT_BIT 324 msr DIT, x8 3251: 326#endif /* ENABLE_FEAT_DIT */ 327 .endm /* set_unset_pstate_bits */ 328 329/*------------------------------------------------------------------------- 330 * This macro checks the ENABLE_FEAT_MPAM state, performs ID register 331 * check to see if the platform supports MPAM extension and restores MPAM3 332 * register value if it is FEAT_STATE_ENABLED/FEAT_STATE_CHECKED. 333 * 334 * This is particularly more complicated because we can't check 335 * if the platform supports MPAM by looking for status of a particular bit 336 * in the MDCR_EL3 or CPTR_EL3 register like other extensions. 337 * ------------------------------------------------------------------------ 338 */ 339 340 .macro restore_mpam3_el3 341#if ENABLE_FEAT_MPAM 342#if ENABLE_FEAT_MPAM == 2 343 344 mrs x8, id_aa64pfr0_el1 345 lsr x8, x8, #(ID_AA64PFR0_MPAM_SHIFT) 346 and x8, x8, #(ID_AA64PFR0_MPAM_MASK) 347 mrs x7, id_aa64pfr1_el1 348 lsr x7, x7, #(ID_AA64PFR1_MPAM_FRAC_SHIFT) 349 and x7, x7, #(ID_AA64PFR1_MPAM_FRAC_MASK) 350 orr x7, x7, x8 351 cbz x7, no_mpam 352#endif 353 /* ----------------------------------------------------------- 354 * Restore MPAM3_EL3 register as per context state 355 * Currently we only enable MPAM for NS world and trap to EL3 356 * for MPAM access in lower ELs of Secure and Realm world 357 * x9 holds address of the per_world context 358 * ----------------------------------------------------------- 359 */ 360 361 ldr x17, [x9, #CTX_MPAM3_EL3] 362 msr S3_6_C10_C5_0, x17 /* mpam3_el3 */ 363 364no_mpam: 365#endif 366 .endm /* restore_mpam3_el3 */ 367 368/* ------------------------------------------------------------------ 369 * The following macro is used to save and restore all the general 370 * purpose and ARMv8.3-PAuth (if enabled) registers. 371 * It also checks if the Secure Cycle Counter (PMCCNTR_EL0) 372 * is disabled in EL3/Secure (ARMv8.5-PMU), wherein PMCCNTR_EL0 373 * needs not to be saved/restored during world switch. 374 * 375 * Ideally we would only save and restore the callee saved registers 376 * when a world switch occurs but that type of implementation is more 377 * complex. So currently we will always save and restore these 378 * registers on entry and exit of EL3. 379 * clobbers: x18 380 * ------------------------------------------------------------------ 381 */ 382 .macro save_gp_pmcr_pauth_regs 383 stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] 384 stp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2] 385 stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] 386 stp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6] 387 stp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8] 388 stp x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10] 389 stp x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12] 390 stp x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14] 391 stp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16] 392 stp x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18] 393 stp x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20] 394 stp x22, x23, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X22] 395 stp x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24] 396 stp x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26] 397 stp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28] 398 mrs x18, sp_el0 399 str x18, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_SP_EL0] 400 401 /* PMUv3 is presumed to be always present */ 402 mrs x9, pmcr_el0 403 str x9, [sp, #CTX_EL3STATE_OFFSET + CTX_PMCR_EL0] 404 /* Disable cycle counter when event counting is prohibited */ 405 orr x9, x9, #PMCR_EL0_DP_BIT 406 msr pmcr_el0, x9 407 isb 408#if CTX_INCLUDE_PAUTH_REGS 409 /* ---------------------------------------------------------- 410 * Save the ARMv8.3-PAuth keys as they are not banked 411 * by exception level 412 * ---------------------------------------------------------- 413 */ 414 add x19, sp, #CTX_PAUTH_REGS_OFFSET 415 416 mrs x20, APIAKeyLo_EL1 /* x21:x20 = APIAKey */ 417 mrs x21, APIAKeyHi_EL1 418 mrs x22, APIBKeyLo_EL1 /* x23:x22 = APIBKey */ 419 mrs x23, APIBKeyHi_EL1 420 mrs x24, APDAKeyLo_EL1 /* x25:x24 = APDAKey */ 421 mrs x25, APDAKeyHi_EL1 422 mrs x26, APDBKeyLo_EL1 /* x27:x26 = APDBKey */ 423 mrs x27, APDBKeyHi_EL1 424 mrs x28, APGAKeyLo_EL1 /* x29:x28 = APGAKey */ 425 mrs x29, APGAKeyHi_EL1 426 427 stp x20, x21, [x19, #CTX_PACIAKEY_LO] 428 stp x22, x23, [x19, #CTX_PACIBKEY_LO] 429 stp x24, x25, [x19, #CTX_PACDAKEY_LO] 430 stp x26, x27, [x19, #CTX_PACDBKEY_LO] 431 stp x28, x29, [x19, #CTX_PACGAKEY_LO] 432#endif /* CTX_INCLUDE_PAUTH_REGS */ 433 .endm /* save_gp_pmcr_pauth_regs */ 434 435/* ----------------------------------------------------------------- 436 * This function saves the context and sets the PSTATE to a known 437 * state, preparing entry to el3. 438 * Save all the general purpose and ARMv8.3-PAuth (if enabled) 439 * registers. 440 * Then set any of the PSTATE bits that are not set by hardware 441 * according to the Aarch64.TakeException pseudocode in the Arm 442 * Architecture Reference Manual to a default value for EL3. 443 * clobbers: x17 444 * ----------------------------------------------------------------- 445 */ 446func prepare_el3_entry 447 save_gp_pmcr_pauth_regs 448 enable_serror_at_el3 449 /* 450 * Set the PSTATE bits not described in the Aarch64.TakeException 451 * pseudocode to their default values. 452 */ 453 set_unset_pstate_bits 454 ret 455endfunc prepare_el3_entry 456 457/* ------------------------------------------------------------------ 458 * This function restores ARMv8.3-PAuth (if enabled) and all general 459 * purpose registers except x30 from the CPU context. 460 * x30 register must be explicitly restored by the caller. 461 * ------------------------------------------------------------------ 462 */ 463func restore_gp_pmcr_pauth_regs 464#if CTX_INCLUDE_PAUTH_REGS 465 /* Restore the ARMv8.3 PAuth keys */ 466 add x10, sp, #CTX_PAUTH_REGS_OFFSET 467 468 ldp x0, x1, [x10, #CTX_PACIAKEY_LO] /* x1:x0 = APIAKey */ 469 ldp x2, x3, [x10, #CTX_PACIBKEY_LO] /* x3:x2 = APIBKey */ 470 ldp x4, x5, [x10, #CTX_PACDAKEY_LO] /* x5:x4 = APDAKey */ 471 ldp x6, x7, [x10, #CTX_PACDBKEY_LO] /* x7:x6 = APDBKey */ 472 ldp x8, x9, [x10, #CTX_PACGAKEY_LO] /* x9:x8 = APGAKey */ 473 474 msr APIAKeyLo_EL1, x0 475 msr APIAKeyHi_EL1, x1 476 msr APIBKeyLo_EL1, x2 477 msr APIBKeyHi_EL1, x3 478 msr APDAKeyLo_EL1, x4 479 msr APDAKeyHi_EL1, x5 480 msr APDBKeyLo_EL1, x6 481 msr APDBKeyHi_EL1, x7 482 msr APGAKeyLo_EL1, x8 483 msr APGAKeyHi_EL1, x9 484#endif /* CTX_INCLUDE_PAUTH_REGS */ 485 486 /* PMUv3 is presumed to be always present */ 487 ldr x0, [sp, #CTX_EL3STATE_OFFSET + CTX_PMCR_EL0] 488 msr pmcr_el0, x0 489 ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] 490 ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2] 491 ldp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] 492 ldp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6] 493 ldp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8] 494 ldp x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10] 495 ldp x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12] 496 ldp x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14] 497 ldp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16] 498 ldp x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18] 499 ldp x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20] 500 ldp x22, x23, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X22] 501 ldp x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24] 502 ldp x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26] 503 ldr x28, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_SP_EL0] 504 msr sp_el0, x28 505 ldp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28] 506 ret 507endfunc restore_gp_pmcr_pauth_regs 508 509#if ERRATA_SPECULATIVE_AT 510/* -------------------------------------------------------------------- 511 * In case of ERRATA_SPECULATIVE_AT, save SCTLR_EL1 and TCR_EL1 512 * registers and update EL1 registers to disable stage1 and stage2 513 * page table walk. 514 * -------------------------------------------------------------------- 515 */ 516func save_and_update_ptw_el1_sys_regs 517 /* ---------------------------------------------------------- 518 * Save only sctlr_el1 and tcr_el1 registers 519 * ---------------------------------------------------------- 520 */ 521 mrs x29, sctlr_el1 522 str x29, [sp, #(CTX_ERRATA_SPEC_AT_OFFSET + CTX_ERRATA_SPEC_AT_SCTLR_EL1)] 523 mrs x29, tcr_el1 524 str x29, [sp, #(CTX_ERRATA_SPEC_AT_OFFSET + CTX_ERRATA_SPEC_AT_TCR_EL1)] 525 526 /* ------------------------------------------------------------ 527 * Must follow below order in order to disable page table 528 * walk for lower ELs (EL1 and EL0). First step ensures that 529 * page table walk is disabled for stage1 and second step 530 * ensures that page table walker should use TCR_EL1.EPDx 531 * bits to perform address translation. ISB ensures that CPU 532 * does these 2 steps in order. 533 * 534 * 1. Update TCR_EL1.EPDx bits to disable page table walk by 535 * stage1. 536 * 2. Enable MMU bit to avoid identity mapping via stage2 537 * and force TCR_EL1.EPDx to be used by the page table 538 * walker. 539 * ------------------------------------------------------------ 540 */ 541 orr x29, x29, #(TCR_EPD0_BIT) 542 orr x29, x29, #(TCR_EPD1_BIT) 543 msr tcr_el1, x29 544 isb 545 mrs x29, sctlr_el1 546 orr x29, x29, #SCTLR_M_BIT 547 msr sctlr_el1, x29 548 isb 549 ret 550endfunc save_and_update_ptw_el1_sys_regs 551 552#endif /* ERRATA_SPECULATIVE_AT */ 553 554/* ----------------------------------------------------------------- 555* The below macro returns the address of the per_world context for 556* the security state, retrieved through "get_security_state" macro. 557* The per_world context address is returned in the register argument. 558* Clobbers: x9, x10 559* ------------------------------------------------------------------ 560*/ 561 562.macro get_per_world_context _reg:req 563 ldr x10, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3] 564 get_security_state x9, x10 565 mov_imm x10, (CTX_PERWORLD_EL3STATE_END - CTX_CPTR_EL3) 566 mul x9, x9, x10 567 adrp x10, per_world_context 568 add x10, x10, :lo12:per_world_context 569 add x9, x9, x10 570 mov \_reg, x9 571.endm 572 573/* ------------------------------------------------------------------ 574 * This routine assumes that the SP_EL3 is pointing to a valid 575 * context structure from where the gp regs and other special 576 * registers can be retrieved. 577 * ------------------------------------------------------------------ 578 */ 579func el3_exit 580#if ENABLE_ASSERTIONS 581 /* el3_exit assumes SP_EL0 on entry */ 582 mrs x17, spsel 583 cmp x17, #MODE_SP_EL0 584 ASM_ASSERT(eq) 585#endif /* ENABLE_ASSERTIONS */ 586 587 /* ---------------------------------------------------------- 588 * Save the current SP_EL0 i.e. the EL3 runtime stack which 589 * will be used for handling the next SMC. 590 * Then switch to SP_EL3. 591 * ---------------------------------------------------------- 592 */ 593 mov x17, sp 594 msr spsel, #MODE_SP_ELX 595 str x17, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] 596 597 /* ---------------------------------------------------------- 598 * Restore CPTR_EL3. 599 * ZCR is only restored if SVE is supported and enabled. 600 * Synchronization is required before zcr_el3 is addressed. 601 * ---------------------------------------------------------- 602 */ 603 604 /* The address of the per_world context is stored in x9 */ 605 get_per_world_context x9 606 607 ldp x19, x20, [x9, #CTX_CPTR_EL3] 608 msr cptr_el3, x19 609 610#if IMAGE_BL31 611 ands x19, x19, #CPTR_EZ_BIT 612 beq sve_not_enabled 613 614 isb 615 msr S3_6_C1_C2_0, x20 /* zcr_el3 */ 616sve_not_enabled: 617 618 restore_mpam3_el3 619 620#endif /* IMAGE_BL31 */ 621 622#if IMAGE_BL31 && DYNAMIC_WORKAROUND_CVE_2018_3639 623 /* ---------------------------------------------------------- 624 * Restore mitigation state as it was on entry to EL3 625 * ---------------------------------------------------------- 626 */ 627 ldr x17, [sp, #CTX_CVE_2018_3639_OFFSET + CTX_CVE_2018_3639_DISABLE] 628 cbz x17, 1f 629 blr x17 6301: 631#endif /* IMAGE_BL31 && DYNAMIC_WORKAROUND_CVE_2018_3639 */ 632 633#if IMAGE_BL31 634 synchronize_errors 635#endif /* IMAGE_BL31 */ 636 637 /* -------------------------------------------------------------- 638 * Restore MDCR_EL3, SPSR_EL3, ELR_EL3 and SCR_EL3 prior to ERET 639 * -------------------------------------------------------------- 640 */ 641 ldp x16, x17, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] 642 ldr x18, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3] 643 ldr x19, [sp, #CTX_EL3STATE_OFFSET + CTX_MDCR_EL3] 644 msr spsr_el3, x16 645 msr elr_el3, x17 646 msr scr_el3, x18 647 msr mdcr_el3, x19 648 649 restore_ptw_el1_sys_regs 650 651 /* ---------------------------------------------------------- 652 * Restore general purpose (including x30), PMCR_EL0 and 653 * ARMv8.3-PAuth registers. 654 * Exit EL3 via ERET to a lower exception level. 655 * ---------------------------------------------------------- 656 */ 657 bl restore_gp_pmcr_pauth_regs 658 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 659 660#ifdef IMAGE_BL31 661 /* Clear the EL3 flag as we are exiting el3 */ 662 str xzr, [sp, #CTX_EL3STATE_OFFSET + CTX_NESTED_EA_FLAG] 663#endif /* IMAGE_BL31 */ 664 665 exception_return 666 667endfunc el3_exit 668