1 /* 2 * Copyright (c) 2024-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 /* Runtime C routines for errata workarounds and common routines */ 8 9 #include <assert.h> 10 11 #include <arch.h> 12 #include <arch_helpers.h> 13 #include <cortex_a75.h> 14 #include <cortex_a510.h> 15 #include <cortex_a520.h> 16 #include <cortex_a710.h> 17 #include <cortex_a715.h> 18 #include <cortex_a720.h> 19 #include <cortex_a720_ae.h> 20 #include <cortex_a725.h> 21 #include <cortex_x2.h> 22 #include <cortex_x3.h> 23 #include <cortex_x4.h> 24 #include <cortex_x925.h> 25 #include <lib/cpus/cpu_ops.h> 26 #include <lib/cpus/errata.h> 27 #include <neoverse_n2.h> 28 #include <neoverse_n3.h> 29 #include <neoverse_v3.h> 30 31 struct erratum_entry *find_erratum_entry(uint32_t errata_id) 32 { 33 struct cpu_ops *cpu_ops; 34 struct erratum_entry *entry, *end; 35 36 cpu_ops = get_cpu_ops_ptr(); 37 assert(cpu_ops != NULL); 38 39 entry = cpu_ops->errata_list_start; 40 assert(entry != NULL); 41 42 end = cpu_ops->errata_list_end; 43 assert(end != NULL); 44 45 end--; /* point to the last erratum entry of the queried cpu */ 46 47 while ((entry <= end)) { 48 if (entry->id == errata_id) { 49 return entry; 50 } 51 entry += 1; 52 } 53 return NULL; 54 } 55 56 bool check_if_trbe_disable_affected_core(void) 57 { 58 switch (EXTRACT_PARTNUM(read_midr())) { 59 #if ERRATA_A520_2938996 60 case EXTRACT_PARTNUM(CORTEX_A520_MIDR): 61 return check_erratum_cortex_a520_2938996(cpu_get_rev_var()) == ERRATA_APPLIES; 62 #endif 63 #if ERRATA_X4_2726228 64 case EXTRACT_PARTNUM(CORTEX_X4_MIDR): 65 return check_erratum_cortex_x4_2726228(cpu_get_rev_var()) == ERRATA_APPLIES; 66 #endif 67 #if ERRATA_A510_2971420 68 case EXTRACT_PARTNUM(CORTEX_A510_MIDR): 69 return check_erratum_cortex_a510_2971420(cpu_get_rev_var()) == ERRATA_APPLIES; 70 #endif 71 default: 72 break; 73 } 74 return false; 75 } 76 77 #if ERRATA_A75_764081 78 bool errata_a75_764081_applies(void) 79 { 80 long rev_var = cpu_get_rev_var(); 81 if (check_erratum_cortex_a75_764081(rev_var) == ERRATA_APPLIES) { 82 return true; 83 } 84 return false; 85 } 86 #endif /* ERRATA_A75_764081 */ 87 88 bool errata_ich_vmcr_el2_applies(void) 89 { 90 switch (EXTRACT_PARTNUM(read_midr())) { 91 #if ERRATA_A710_3701772 92 case EXTRACT_PARTNUM(CORTEX_A710_MIDR): 93 if (check_erratum_cortex_a710_3701772(cpu_get_rev_var()) == ERRATA_APPLIES) 94 return true; 95 break; 96 #endif /* ERRATA_A710_3701772 */ 97 98 #if ERRATA_A715_3699560 99 case EXTRACT_PARTNUM(CORTEX_A715_MIDR): 100 if (check_erratum_cortex_a715_3699560(cpu_get_rev_var()) == ERRATA_APPLIES) 101 return true; 102 break; 103 #endif /* ERRATA_A715_3699560 */ 104 105 #if ERRATA_A720_3699561 106 case EXTRACT_PARTNUM(CORTEX_A720_MIDR): 107 if (check_erratum_cortex_a720_3699561(cpu_get_rev_var()) == ERRATA_APPLIES) 108 return true;; 109 break; 110 #endif /* ERRATA_A720_3699561 */ 111 112 #if ERRATA_A720_AE_3699562 113 case EXTRACT_PARTNUM(CORTEX_A720_AE_MIDR): 114 if (check_erratum_cortex_a720_ae_3699562(cpu_get_rev_var()) == ERRATA_APPLIES) 115 return true; 116 break; 117 #endif /* ERRATA_A720_AE_3699562 */ 118 119 #if ERRATA_A725_3699564 120 case EXTRACT_PARTNUM(CORTEX_A725_MIDR): 121 if (check_erratum_cortex_a725_3699564(cpu_get_rev_var()) == ERRATA_APPLIES) 122 return true; 123 break; 124 #endif /* ERRATA_A725_3699564 */ 125 126 #if ERRATA_X2_3701772 127 case EXTRACT_PARTNUM(CORTEX_X2_MIDR): 128 if (check_erratum_cortex_x2_3701772(cpu_get_rev_var()) == ERRATA_APPLIES) 129 return true; 130 break; 131 #endif /* ERRATA_X2_3701772 */ 132 133 #if ERRATA_X3_3701769 134 case EXTRACT_PARTNUM(CORTEX_X3_MIDR): 135 if (check_erratum_cortex_x3_3701769(cpu_get_rev_var()) == ERRATA_APPLIES) 136 return true; 137 break; 138 #endif /* ERRATA_X3_3701769 */ 139 140 #if ERRATA_X4_3701758 141 case EXTRACT_PARTNUM(CORTEX_X4_MIDR): 142 if (check_erratum_cortex_x4_3701758(cpu_get_rev_var()) == ERRATA_APPLIES) 143 return true; 144 break; 145 #endif /* ERRATA_X4_3701758 */ 146 147 #if ERRATA_X925_3701747 148 case EXTRACT_PARTNUM(CORTEX_X925_MIDR): 149 if (check_erratum_cortex_x925_3701747(cpu_get_rev_var()) == ERRATA_APPLIES) 150 return true; 151 break; 152 #endif /* ERRATA_X925_3701747 */ 153 154 #if ERRATA_N2_3701773 155 case EXTRACT_PARTNUM(NEOVERSE_N2_MIDR): 156 if (check_erratum_neoverse_n2_3701773(cpu_get_rev_var()) == ERRATA_APPLIES) 157 return true; 158 break; 159 #endif /* ERRATA_N2_3701773 */ 160 161 #if ERRATA_N3_3699563 162 case EXTRACT_PARTNUM(NEOVERSE_N3_MIDR): 163 if (check_erratum_neoverse_n3_3699563(cpu_get_rev_var()) == ERRATA_APPLIES) 164 return true; 165 break; 166 #endif /* ERRATA_N3_3699563 */ 167 168 #if ERRATA_V3_3701767 169 case EXTRACT_PARTNUM(NEOVERSE_V3_MIDR): 170 if (check_erratum_neoverse_v3_3701767(cpu_get_rev_var()) == ERRATA_APPLIES) 171 return true; 172 break; 173 #endif /* ERRATA_V3_3701767 */ 174 175 default: 176 break; 177 } 178 179 return false; 180 } 181 182 int check_erratum_applies(uint32_t cve, int errata_id) 183 { 184 struct erratum_entry *entry; 185 long rev_var; 186 187 rev_var = cpu_get_rev_var(); 188 189 entry = find_erratum_entry(errata_id); 190 191 if (entry == NULL) { 192 return ERRATA_NOT_APPLIES; 193 } 194 195 assert(entry->cve == cve); 196 197 return entry->check_func(rev_var); 198 } 199