xref: /rk3399_ARM-atf/lib/cpus/cpu-ops.mk (revision 0b77197baf9a22625f91112cf009c9209f4279e8)
15541bb3fSSoby Mathew#
254035fc4SSandrine Bailleux# Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
35541bb3fSSoby Mathew#
45541bb3fSSoby Mathew# Redistribution and use in source and binary forms, with or without
55541bb3fSSoby Mathew# modification, are permitted provided that the following conditions are met:
65541bb3fSSoby Mathew#
75541bb3fSSoby Mathew# Redistributions of source code must retain the above copyright notice, this
85541bb3fSSoby Mathew# list of conditions and the following disclaimer.
95541bb3fSSoby Mathew#
105541bb3fSSoby Mathew# Redistributions in binary form must reproduce the above copyright notice,
115541bb3fSSoby Mathew# this list of conditions and the following disclaimer in the documentation
125541bb3fSSoby Mathew# and/or other materials provided with the distribution.
135541bb3fSSoby Mathew#
145541bb3fSSoby Mathew# Neither the name of ARM nor the names of its contributors may be used
155541bb3fSSoby Mathew# to endorse or promote products derived from this software without specific
165541bb3fSSoby Mathew# prior written permission.
175541bb3fSSoby Mathew#
185541bb3fSSoby Mathew# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
195541bb3fSSoby Mathew# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
205541bb3fSSoby Mathew# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
215541bb3fSSoby Mathew# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
225541bb3fSSoby Mathew# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
235541bb3fSSoby Mathew# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
245541bb3fSSoby Mathew# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
255541bb3fSSoby Mathew# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
265541bb3fSSoby Mathew# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
275541bb3fSSoby Mathew# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
285541bb3fSSoby Mathew# POSSIBILITY OF SUCH DAMAGE.
295541bb3fSSoby Mathew#
305541bb3fSSoby Mathew
315541bb3fSSoby Mathew# Cortex A57 specific optimisation to skip L1 cache flush when
325541bb3fSSoby Mathew# cluster is powered down.
335541bb3fSSoby MathewSKIP_A57_L1_FLUSH_PWR_DWN	?=0
345541bb3fSSoby Mathew
3554035fc4SSandrine Bailleux# Flag to disable the cache non-temporal hint.
3654035fc4SSandrine Bailleux# It is enabled by default.
3754035fc4SSandrine BailleuxA53_DISABLE_NON_TEMPORAL_HINT	?=1
3854035fc4SSandrine Bailleux
3954035fc4SSandrine Bailleux# Flag to disable the cache non-temporal hint.
4054035fc4SSandrine Bailleux# It is enabled by default.
4154035fc4SSandrine BailleuxA57_DISABLE_NON_TEMPORAL_HINT	?=1
4254035fc4SSandrine Bailleux
435541bb3fSSoby Mathew# Process SKIP_A57_L1_FLUSH_PWR_DWN flag
445541bb3fSSoby Mathew$(eval $(call assert_boolean,SKIP_A57_L1_FLUSH_PWR_DWN))
455541bb3fSSoby Mathew$(eval $(call add_define,SKIP_A57_L1_FLUSH_PWR_DWN))
465541bb3fSSoby Mathew
4754035fc4SSandrine Bailleux# Process A53_DISABLE_NON_TEMPORAL_HINT flag
4854035fc4SSandrine Bailleux$(eval $(call assert_boolean,A53_DISABLE_NON_TEMPORAL_HINT))
4954035fc4SSandrine Bailleux$(eval $(call add_define,A53_DISABLE_NON_TEMPORAL_HINT))
5054035fc4SSandrine Bailleux
5154035fc4SSandrine Bailleux# Process A57_DISABLE_NON_TEMPORAL_HINT flag
5254035fc4SSandrine Bailleux$(eval $(call assert_boolean,A57_DISABLE_NON_TEMPORAL_HINT))
5354035fc4SSandrine Bailleux$(eval $(call add_define,A57_DISABLE_NON_TEMPORAL_HINT))
5454035fc4SSandrine Bailleux
555541bb3fSSoby Mathew
56097b787aSSandrine Bailleux# CPU Errata Build flags.
57097b787aSSandrine Bailleux# These should be enabled by the platform if the erratum workaround needs to be
58097b787aSSandrine Bailleux# applied.
595541bb3fSSoby Mathew
60097b787aSSandrine Bailleux# Flag to apply erratum 826319 workaround during reset. This erratum applies
61097b787aSSandrine Bailleux# only to revision <= r0p2 of the Cortex A53 cpu.
626b0d97b2SJimmy HuangERRATA_A53_826319	?=0
636b0d97b2SJimmy Huang
64097b787aSSandrine Bailleux# Flag to apply erratum 836870 workaround during reset. This erratum applies
65097b787aSSandrine Bailleux# only to revision <= r0p3 of the Cortex A53 cpu. From r0p4 and onwards, this
66097b787aSSandrine Bailleux# erratum workaround is enabled by default.
676b0d97b2SJimmy HuangERRATA_A53_836870	?=0
686b0d97b2SJimmy Huang
69097b787aSSandrine Bailleux# Flag to apply erratum 806969 workaround during reset. This erratum applies
70097b787aSSandrine Bailleux# only to revision r0p0 of the Cortex A57 cpu.
715541bb3fSSoby MathewERRATA_A57_806969	?=0
725541bb3fSSoby Mathew
73097b787aSSandrine Bailleux# Flag to apply erratum 813420  workaround during reset. This erratum applies
74097b787aSSandrine Bailleux# only to revision r0p0 of the Cortex A57 cpu.
755541bb3fSSoby MathewERRATA_A57_813420	?=0
765541bb3fSSoby Mathew
77df22d602SSandrine Bailleux# Flag to apply erratum 826974 workaround during reset. This erratum applies
78df22d602SSandrine Bailleux# only to revision <= r1p1 of the Cortex A57 cpu.
79df22d602SSandrine BailleuxERRATA_A57_826974	?=0
80df22d602SSandrine Bailleux
81a8b1c769SSandrine Bailleux# Flag to apply erratum 828024 workaround during reset. This erratum applies
82a8b1c769SSandrine Bailleux# only to revision <= r1p1 of the Cortex A57 cpu.
83a8b1c769SSandrine BailleuxERRATA_A57_828024	?=0
84a8b1c769SSandrine Bailleux
85*0b77197bSSandrine Bailleux# Flag to apply erratum 829520 workaround during reset. This erratum applies
86*0b77197bSSandrine Bailleux# only to revision <= r1p2 of the Cortex A57 cpu.
87*0b77197bSSandrine BailleuxERRATA_A57_829520	?=0
88*0b77197bSSandrine Bailleux
896b0d97b2SJimmy Huang# Process ERRATA_A53_826319 flag
906b0d97b2SJimmy Huang$(eval $(call assert_boolean,ERRATA_A53_826319))
916b0d97b2SJimmy Huang$(eval $(call add_define,ERRATA_A53_826319))
926b0d97b2SJimmy Huang
936b0d97b2SJimmy Huang# Process ERRATA_A53_836870 flag
946b0d97b2SJimmy Huang$(eval $(call assert_boolean,ERRATA_A53_836870))
956b0d97b2SJimmy Huang$(eval $(call add_define,ERRATA_A53_836870))
966b0d97b2SJimmy Huang
975541bb3fSSoby Mathew# Process ERRATA_A57_806969 flag
985541bb3fSSoby Mathew$(eval $(call assert_boolean,ERRATA_A57_806969))
995541bb3fSSoby Mathew$(eval $(call add_define,ERRATA_A57_806969))
1005541bb3fSSoby Mathew
1015541bb3fSSoby Mathew# Process ERRATA_A57_813420 flag
1025541bb3fSSoby Mathew$(eval $(call assert_boolean,ERRATA_A57_813420))
1035541bb3fSSoby Mathew$(eval $(call add_define,ERRATA_A57_813420))
104df22d602SSandrine Bailleux
105df22d602SSandrine Bailleux# Process ERRATA_A57_826974 flag
106df22d602SSandrine Bailleux$(eval $(call assert_boolean,ERRATA_A57_826974))
107df22d602SSandrine Bailleux$(eval $(call add_define,ERRATA_A57_826974))
108a8b1c769SSandrine Bailleux
109a8b1c769SSandrine Bailleux# Process ERRATA_A57_828024 flag
110a8b1c769SSandrine Bailleux$(eval $(call assert_boolean,ERRATA_A57_828024))
111a8b1c769SSandrine Bailleux$(eval $(call add_define,ERRATA_A57_828024))
112*0b77197bSSandrine Bailleux
113*0b77197bSSandrine Bailleux# Process ERRATA_A57_829520 flag
114*0b77197bSSandrine Bailleux$(eval $(call assert_boolean,ERRATA_A57_829520))
115*0b77197bSSandrine Bailleux$(eval $(call add_define,ERRATA_A57_829520))
116