1/* 2 * Copyright (c) 2020-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <context.h> 10#include <cpu_macros.S> 11#include <cpuamu.h> 12#include <rainier.h> 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "Rainier CPU must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19/* 64-bit only core */ 20#if CTX_INCLUDE_AARCH32_REGS == 1 21#error "Rainier CPU supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22#endif 23 24cpu_reset_prologue rainier 25 26/* -------------------------------------------------- 27 * Disable speculative loads if Rainier supports 28 * SSBS. 29 * 30 * Shall clobber: x0. 31 * -------------------------------------------------- 32 */ 33func rainier_disable_speculative_loads 34 /* Check if the PE implements SSBS */ 35 mrs x0, id_aa64pfr1_el1 36 tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT) 37 b.eq 1f 38 39 /* Disable speculative loads */ 40 msr SSBS, xzr 41 421: 43 ret 44endfunc rainier_disable_speculative_loads 45 46 /* Rainier R0P0 is based on Neoverse N1 R4P0. */ 47workaround_reset_start rainier, ERRATUM(1868343), ERRATA_N1_1868343 48 sysreg_bit_set RAINIER_CPUACTLR_EL1, RAINIER_CPUACTLR_EL1_BIT_13 49workaround_reset_end rainier, ERRATUM(1868343) 50 51check_erratum_ls rainier, ERRATUM(1868343), CPU_REV(0, 0) 52 53cpu_reset_func_start rainier 54 bl rainier_disable_speculative_loads 55 /* Forces all cacheable atomic instructions to be near */ 56 sysreg_bit_set RAINIER_CPUACTLR2_EL1, RAINIER_CPUACTLR2_EL1_BIT_2 57 58#if ENABLE_FEAT_AMU 59 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 60 sysreg_bit_set actlr_el3, RAINIER_ACTLR_AMEN_BIT 61 62 /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ 63 sysreg_bit_set actlr_el2, RAINIER_ACTLR_AMEN_BIT 64 65 /* Enable group0 counters */ 66 mov x0, #RAINIER_AMU_GROUP0_MASK 67 msr CPUAMCNTENSET_EL0, x0 68#endif 69cpu_reset_func_end rainier 70 71 /* --------------------------------------------- 72 * HW will do the cache maintenance while powering down 73 * --------------------------------------------- 74 */ 75func rainier_core_pwr_dwn 76 /* --------------------------------------------- 77 * Enable CPU power down bit in power control register 78 * --------------------------------------------- 79 */ 80 sysreg_bit_set RAINIER_CPUPWRCTLR_EL1, RAINIER_CORE_PWRDN_EN_MASK 81 isb 82 ret 83endfunc rainier_core_pwr_dwn 84 85 /* --------------------------------------------- 86 * This function provides Rainier specific 87 * register information for crash reporting. 88 * It needs to return with x6 pointing to 89 * a list of register names in ascii and 90 * x8 - x15 having values of registers to be 91 * reported. 92 * --------------------------------------------- 93 */ 94.section .rodata.rainier_regs, "aS" 95rainier_regs: /* The ascii list of register names to be reported */ 96 .asciz "cpuectlr_el1", "" 97 98func rainier_cpu_reg_dump 99 adr x6, rainier_regs 100 mrs x8, RAINIER_CPUECTLR_EL1 101 ret 102endfunc rainier_cpu_reg_dump 103 104declare_cpu_ops rainier, RAINIER_MIDR, \ 105 rainier_reset_func, \ 106 rainier_core_pwr_dwn 107