12b357c31SManoj Kumar/* 22b357c31SManoj Kumar * Copyright (c) 2020, Arm Limited. All rights reserved. 32b357c31SManoj Kumar * 42b357c31SManoj Kumar * SPDX-License-Identifier: BSD-3-Clause 52b357c31SManoj Kumar */ 62b357c31SManoj Kumar 72b357c31SManoj Kumar#include <arch.h> 82b357c31SManoj Kumar#include <asm_macros.S> 92b357c31SManoj Kumar#include <context.h> 102b357c31SManoj Kumar#include <cpu_macros.S> 112b357c31SManoj Kumar#include <cpuamu.h> 122b357c31SManoj Kumar#include <rainier.h> 132b357c31SManoj Kumar 142b357c31SManoj Kumar/* Hardware handled coherency */ 152b357c31SManoj Kumar#if HW_ASSISTED_COHERENCY == 0 162b357c31SManoj Kumar#error "Rainier CPU must be compiled with HW_ASSISTED_COHERENCY enabled" 172b357c31SManoj Kumar#endif 182b357c31SManoj Kumar 192b357c31SManoj Kumar/* 64-bit only core */ 202b357c31SManoj Kumar#if CTX_INCLUDE_AARCH32_REGS == 1 212b357c31SManoj Kumar#error "Rainier CPU supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 222b357c31SManoj Kumar#endif 232b357c31SManoj Kumar 242b357c31SManoj Kumar/* -------------------------------------------------- 252b357c31SManoj Kumar * Disable speculative loads if Rainier supports 262b357c31SManoj Kumar * SSBS. 272b357c31SManoj Kumar * 282b357c31SManoj Kumar * Shall clobber: x0. 292b357c31SManoj Kumar * -------------------------------------------------- 302b357c31SManoj Kumar */ 312b357c31SManoj Kumarfunc rainier_disable_speculative_loads 322b357c31SManoj Kumar /* Check if the PE implements SSBS */ 332b357c31SManoj Kumar mrs x0, id_aa64pfr1_el1 342b357c31SManoj Kumar tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT) 352b357c31SManoj Kumar b.eq 1f 362b357c31SManoj Kumar 372b357c31SManoj Kumar /* Disable speculative loads */ 382b357c31SManoj Kumar msr SSBS, xzr 392b357c31SManoj Kumar 402b357c31SManoj Kumar1: 412b357c31SManoj Kumar ret 422b357c31SManoj Kumarendfunc rainier_disable_speculative_loads 432b357c31SManoj Kumar 442b357c31SManoj Kumarfunc rainier_reset_func 452b357c31SManoj Kumar mov x19, x30 462b357c31SManoj Kumar 472b357c31SManoj Kumar bl rainier_disable_speculative_loads 482b357c31SManoj Kumar 492b357c31SManoj Kumar /* Forces all cacheable atomic instructions to be near */ 502b357c31SManoj Kumar mrs x0, RAINIER_CPUACTLR2_EL1 512b357c31SManoj Kumar orr x0, x0, #RAINIER_CPUACTLR2_EL1_BIT_2 522b357c31SManoj Kumar msr RAINIER_CPUACTLR2_EL1, x0 532b357c31SManoj Kumar isb 542b357c31SManoj Kumar 552b357c31SManoj Kumar bl cpu_get_rev_var 562b357c31SManoj Kumar mov x18, x0 572b357c31SManoj Kumar 582b357c31SManoj Kumar#if ENABLE_AMU 592b357c31SManoj Kumar /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 602b357c31SManoj Kumar mrs x0, actlr_el3 612b357c31SManoj Kumar orr x0, x0, #RAINIER_ACTLR_AMEN_BIT 622b357c31SManoj Kumar msr actlr_el3, x0 632b357c31SManoj Kumar 642b357c31SManoj Kumar /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ 652b357c31SManoj Kumar mrs x0, actlr_el2 662b357c31SManoj Kumar orr x0, x0, #RAINIER_ACTLR_AMEN_BIT 672b357c31SManoj Kumar msr actlr_el2, x0 682b357c31SManoj Kumar 692b357c31SManoj Kumar /* Enable group0 counters */ 702b357c31SManoj Kumar mov x0, #RAINIER_AMU_GROUP0_MASK 712b357c31SManoj Kumar msr CPUAMCNTENSET_EL0, x0 722b357c31SManoj Kumar#endif 732b357c31SManoj Kumar 742b357c31SManoj Kumar isb 752b357c31SManoj Kumar ret x19 762b357c31SManoj Kumarendfunc rainier_reset_func 772b357c31SManoj Kumar 782b357c31SManoj Kumar /* --------------------------------------------- 792b357c31SManoj Kumar * HW will do the cache maintenance while powering down 802b357c31SManoj Kumar * --------------------------------------------- 812b357c31SManoj Kumar */ 822b357c31SManoj Kumarfunc rainier_core_pwr_dwn 832b357c31SManoj Kumar /* --------------------------------------------- 842b357c31SManoj Kumar * Enable CPU power down bit in power control register 852b357c31SManoj Kumar * --------------------------------------------- 862b357c31SManoj Kumar */ 872b357c31SManoj Kumar mrs x0, RAINIER_CPUPWRCTLR_EL1 882b357c31SManoj Kumar orr x0, x0, #RAINIER_CORE_PWRDN_EN_MASK 892b357c31SManoj Kumar msr RAINIER_CPUPWRCTLR_EL1, x0 902b357c31SManoj Kumar isb 912b357c31SManoj Kumar ret 922b357c31SManoj Kumarendfunc rainier_core_pwr_dwn 932b357c31SManoj Kumar 942b357c31SManoj Kumar#if REPORT_ERRATA 952b357c31SManoj Kumar/* 962b357c31SManoj Kumar * Errata printing function for Rainier. Must follow AAPCS. 972b357c31SManoj Kumar */ 982b357c31SManoj Kumarfunc rainier_errata_report 992b357c31SManoj Kumar stp x8, x30, [sp, #-16]! 1002b357c31SManoj Kumar 1012b357c31SManoj Kumar bl cpu_get_rev_var 1022b357c31SManoj Kumar mov x8, x0 1032b357c31SManoj Kumar 1042b357c31SManoj Kumar ldp x8, x30, [sp], #16 1052b357c31SManoj Kumar ret 1062b357c31SManoj Kumarendfunc rainier_errata_report 1072b357c31SManoj Kumar#endif 1082b357c31SManoj Kumar 1092b357c31SManoj Kumar /* --------------------------------------------- 1102b357c31SManoj Kumar * This function provides Rainier specific 1112b357c31SManoj Kumar * register information for crash reporting. 1122b357c31SManoj Kumar * It needs to return with x6 pointing to 1132b357c31SManoj Kumar * a list of register names in ascii and 1142b357c31SManoj Kumar * x8 - x15 having values of registers to be 1152b357c31SManoj Kumar * reported. 1162b357c31SManoj Kumar * --------------------------------------------- 1172b357c31SManoj Kumar */ 1182b357c31SManoj Kumar.section .rodata.rainier_regs, "aS" 1192b357c31SManoj Kumarrainier_regs: /* The ascii list of register names to be reported */ 1202b357c31SManoj Kumar .asciz "cpuectlr_el1", "" 1212b357c31SManoj Kumar 1222b357c31SManoj Kumarfunc rainier_cpu_reg_dump 1232b357c31SManoj Kumar adr x6, rainier_regs 1242b357c31SManoj Kumar mrs x8, RAINIER_CPUECTLR_EL1 1252b357c31SManoj Kumar ret 1262b357c31SManoj Kumarendfunc rainier_cpu_reg_dump 1272b357c31SManoj Kumar 128*041d7c7bSManoj Kumardeclare_cpu_ops rainier, RAINIER_MIDR, \ 1292b357c31SManoj Kumar rainier_reset_func, \ 1302b357c31SManoj Kumar rainier_core_pwr_dwn 131