1*5d764e05SLeif Lindholm/* 2*5d764e05SLeif Lindholm * Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved. 3*5d764e05SLeif Lindholm * 4*5d764e05SLeif Lindholm * SPDX-License-Identifier: BSD-3-Clause 5*5d764e05SLeif Lindholm */ 6*5d764e05SLeif Lindholm#include <arch.h> 7*5d764e05SLeif Lindholm#include <asm_macros.S> 8*5d764e05SLeif Lindholm#include <cpu_macros.S> 9*5d764e05SLeif Lindholm#include <qemu_max.h> 10*5d764e05SLeif Lindholm 11*5d764e05SLeif Lindholmfunc qemu_max_core_pwr_dwn 12*5d764e05SLeif Lindholm /* --------------------------------------------- 13*5d764e05SLeif Lindholm * Disable the Data Cache. 14*5d764e05SLeif Lindholm * --------------------------------------------- 15*5d764e05SLeif Lindholm */ 16*5d764e05SLeif Lindholm mrs x1, sctlr_el3 17*5d764e05SLeif Lindholm bic x1, x1, #SCTLR_C_BIT 18*5d764e05SLeif Lindholm msr sctlr_el3, x1 19*5d764e05SLeif Lindholm isb 20*5d764e05SLeif Lindholm 21*5d764e05SLeif Lindholm /* --------------------------------------------- 22*5d764e05SLeif Lindholm * Flush L1 cache to L2. 23*5d764e05SLeif Lindholm * --------------------------------------------- 24*5d764e05SLeif Lindholm */ 25*5d764e05SLeif Lindholm mov x18, lr 26*5d764e05SLeif Lindholm mov x0, #DCCISW 27*5d764e05SLeif Lindholm bl dcsw_op_level1 28*5d764e05SLeif Lindholm mov lr, x18 29*5d764e05SLeif Lindholm ret 30*5d764e05SLeif Lindholmendfunc qemu_max_core_pwr_dwn 31*5d764e05SLeif Lindholm 32*5d764e05SLeif Lindholmfunc qemu_max_cluster_pwr_dwn 33*5d764e05SLeif Lindholm /* --------------------------------------------- 34*5d764e05SLeif Lindholm * Disable the Data Cache. 35*5d764e05SLeif Lindholm * --------------------------------------------- 36*5d764e05SLeif Lindholm */ 37*5d764e05SLeif Lindholm mrs x1, sctlr_el3 38*5d764e05SLeif Lindholm bic x1, x1, #SCTLR_C_BIT 39*5d764e05SLeif Lindholm msr sctlr_el3, x1 40*5d764e05SLeif Lindholm isb 41*5d764e05SLeif Lindholm 42*5d764e05SLeif Lindholm /* --------------------------------------------- 43*5d764e05SLeif Lindholm * Flush all caches to PoC. 44*5d764e05SLeif Lindholm * --------------------------------------------- 45*5d764e05SLeif Lindholm */ 46*5d764e05SLeif Lindholm mov x0, #DCCISW 47*5d764e05SLeif Lindholm b dcsw_op_all 48*5d764e05SLeif Lindholmendfunc qemu_max_cluster_pwr_dwn 49*5d764e05SLeif Lindholm 50*5d764e05SLeif Lindholm#if REPORT_ERRATA 51*5d764e05SLeif Lindholm/* 52*5d764e05SLeif Lindholm * Errata printing function for QEMU "max". Must follow AAPCS. 53*5d764e05SLeif Lindholm */ 54*5d764e05SLeif Lindholmfunc qemu_max_errata_report 55*5d764e05SLeif Lindholm ret 56*5d764e05SLeif Lindholmendfunc qemu_max_errata_report 57*5d764e05SLeif Lindholm#endif 58*5d764e05SLeif Lindholm 59*5d764e05SLeif Lindholm /* --------------------------------------------- 60*5d764e05SLeif Lindholm * This function provides cpu specific 61*5d764e05SLeif Lindholm * register information for crash reporting. 62*5d764e05SLeif Lindholm * It needs to return with x6 pointing to 63*5d764e05SLeif Lindholm * a list of register names in ascii and 64*5d764e05SLeif Lindholm * x8 - x15 having values of registers to be 65*5d764e05SLeif Lindholm * reported. 66*5d764e05SLeif Lindholm * --------------------------------------------- 67*5d764e05SLeif Lindholm */ 68*5d764e05SLeif Lindholm.section .rodata.qemu_max_regs, "aS" 69*5d764e05SLeif Lindholmqemu_max_regs: /* The ascii list of register names to be reported */ 70*5d764e05SLeif Lindholm .asciz "" /* no registers to report */ 71*5d764e05SLeif Lindholm 72*5d764e05SLeif Lindholmfunc qemu_max_cpu_reg_dump 73*5d764e05SLeif Lindholm adr x6, qemu_max_regs 74*5d764e05SLeif Lindholm ret 75*5d764e05SLeif Lindholmendfunc qemu_max_cpu_reg_dump 76*5d764e05SLeif Lindholm 77*5d764e05SLeif Lindholm 78*5d764e05SLeif Lindholm/* cpu_ops for QEMU MAX */ 79*5d764e05SLeif Lindholmdeclare_cpu_ops qemu_max, QEMU_MAX_MIDR, CPU_NO_RESET_FUNC, \ 80*5d764e05SLeif Lindholm qemu_max_core_pwr_dwn, \ 81*5d764e05SLeif Lindholm qemu_max_cluster_pwr_dwn 82