1/* 2 * Copyright (c) 2022-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <neoverse_v3.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Neoverse V3 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Neoverse V3 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25cpu_reset_prologue neoverse_v3 26 27.global check_erratum_neoverse_v3_3701767 28 29workaround_reset_start neoverse_v3, ERRATUM(2970647), ERRATA_V3_2970647 30 /* Add ISB before MRS reads of MPIDR_EL1/MIDR_EL1 */ 31 ldr x0, =0x1 32 msr S3_6_c15_c8_0, x0 /* msr CPUPSELR_EL3, X0 */ 33 ldr x0, =0xd5380000 34 msr S3_6_c15_c8_2, x0 /* msr CPUPOR_EL3, X0 */ 35 ldr x0, =0xFFFFFF40 36 msr S3_6_c15_c8_3,x0 /* msr CPUPMR_EL3, X0 */ 37 ldr x0, =0x000080010033f 38 msr S3_6_c15_c8_1, x0 /* msr CPUPCR_EL3, X0 */ 39 isb 40workaround_reset_end neoverse_v3, ERRATUM(2970647) 41 42check_erratum_ls neoverse_v3, ERRATUM(2970647), CPU_REV(0, 0) 43 44add_erratum_entry neoverse_v3, ERRATUM(3701767), ERRATA_V3_3701767 45 46check_erratum_ls neoverse_v3, ERRATUM(3701767), CPU_REV(0, 2) 47 48/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 49workaround_reset_start neoverse_v3, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 50 sysreg_bit_set NEOVERSE_V3_CPUECTLR_EL1, BIT(46) 51workaround_reset_end neoverse_v3, CVE(2024, 5660) 52 53check_erratum_ls neoverse_v3, CVE(2024, 5660), CPU_REV(0, 1) 54 55workaround_reset_start neoverse_v3, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 56 /* --------------------------------- 57 * Sets BIT41 of CPUACTLR6_EL1 which 58 * disables L1 Data cache prefetcher 59 * --------------------------------- 60 */ 61 sysreg_bit_set NEOVERSE_V3_CPUACTLR6_EL1, BIT(41) 62workaround_reset_end neoverse_v3, CVE(2024, 7881) 63 64check_erratum_chosen neoverse_v3, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 65 66 /* --------------------------------------------- 67 * HW will do the cache maintenance while powering down 68 * --------------------------------------------- 69 */ 70func neoverse_v3_core_pwr_dwn 71 /* --------------------------------------------- 72 * Enable CPU power down bit in power control register 73 * --------------------------------------------- 74 */ 75 sysreg_bit_set NEOVERSE_V3_CPUPWRCTLR_EL1, \ 76 NEOVERSE_V3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 77 78 isb 79 ret 80endfunc neoverse_v3_core_pwr_dwn 81 82cpu_reset_func_start neoverse_v3 83 /* Disable speculative loads */ 84 msr SSBS, xzr 85cpu_reset_func_end neoverse_v3 86 87 /* --------------------------------------------- 88 * This function provides Neoverse V3 specific 89 * register information for crash reporting. 90 * It needs to return with x6 pointing to 91 * a list of register names in ascii and 92 * x8 - x15 having values of registers to be 93 * reported. 94 * --------------------------------------------- 95 */ 96.section .rodata.neoverse_v3_regs, "aS" 97neoverse_v3_regs: /* The ascii list of register names to be reported */ 98 .asciz "cpuectlr_el1", "" 99 100func neoverse_v3_cpu_reg_dump 101 adr x6, neoverse_v3_regs 102 mrs x8, NEOVERSE_V3_CPUECTLR_EL1 103 ret 104endfunc neoverse_v3_cpu_reg_dump 105 106declare_cpu_ops neoverse_v3, NEOVERSE_V3_VNAE_MIDR, \ 107 neoverse_v3_reset_func, \ 108 neoverse_v3_core_pwr_dwn 109 110declare_cpu_ops neoverse_v3, NEOVERSE_V3_MIDR, \ 111 neoverse_v3_reset_func, \ 112 neoverse_v3_core_pwr_dwn 113