1/* 2 * Copyright (c) 2022-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <neoverse_v3.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Neoverse V3 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Neoverse V3 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25#if WORKAROUND_CVE_2022_23960 26 wa_cve_2022_23960_bhb_vector_table NEOVERSE_V3_BHB_LOOP_COUNT, neoverse_v3 27#endif /* WORKAROUND_CVE_2022_23960 */ 28 29/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 30workaround_reset_start neoverse_v3, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 31 sysreg_bit_set NEOVERSE_V3_CPUECTLR_EL1, BIT(46) 32workaround_reset_end neoverse_v3, CVE(2024, 5660) 33 34check_erratum_ls neoverse_v3, CVE(2024, 5660), CPU_REV(0, 1) 35 36workaround_reset_start neoverse_v3, CVE(2022,23960), WORKAROUND_CVE_2022_23960 37#if IMAGE_BL31 38 /* 39 * The Neoverse V3 generic vectors are overridden to apply errata 40 * mitigation on exception entry from lower ELs. 41 */ 42 override_vector_table wa_cve_vbar_neoverse_v3 43 44#endif /* IMAGE_BL31 */ 45workaround_reset_end neoverse_v3, CVE(2022,23960) 46 47check_erratum_chosen neoverse_v3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 48 49 /* --------------------------------------------- 50 * HW will do the cache maintenance while powering down 51 * --------------------------------------------- 52 */ 53func neoverse_v3_core_pwr_dwn 54 /* --------------------------------------------- 55 * Enable CPU power down bit in power control register 56 * --------------------------------------------- 57 */ 58 sysreg_bit_set NEOVERSE_V3_CPUPWRCTLR_EL1, \ 59 NEOVERSE_V3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 60 61 isb 62 ret 63endfunc neoverse_v3_core_pwr_dwn 64 65cpu_reset_func_start neoverse_v3 66 /* Disable speculative loads */ 67 msr SSBS, xzr 68cpu_reset_func_end neoverse_v3 69 70 /* --------------------------------------------- 71 * This function provides Neoverse V3 specific 72 * register information for crash reporting. 73 * It needs to return with x6 pointing to 74 * a list of register names in ascii and 75 * x8 - x15 having values of registers to be 76 * reported. 77 * --------------------------------------------- 78 */ 79.section .rodata.neoverse_v3_regs, "aS" 80neoverse_v3_regs: /* The ascii list of register names to be reported */ 81 .asciz "cpuectlr_el1", "" 82 83func neoverse_v3_cpu_reg_dump 84 adr x6, neoverse_v3_regs 85 mrs x8, NEOVERSE_V3_CPUECTLR_EL1 86 ret 87endfunc neoverse_v3_cpu_reg_dump 88 89declare_cpu_ops neoverse_v3, NEOVERSE_V3_VNAE_MIDR, \ 90 neoverse_v3_reset_func, \ 91 neoverse_v3_core_pwr_dwn 92 93declare_cpu_ops neoverse_v3, NEOVERSE_V3_MIDR, \ 94 neoverse_v3_reset_func, \ 95 neoverse_v3_core_pwr_dwn 96