1328d304dSSona Mathew/* 2037a15f5SArvind Ram Prakash * Copyright (c) 2022-2025, Arm Limited. All rights reserved. 3328d304dSSona Mathew * 4328d304dSSona Mathew * SPDX-License-Identifier: BSD-3-Clause 5328d304dSSona Mathew */ 6328d304dSSona Mathew 7328d304dSSona Mathew#include <arch.h> 8328d304dSSona Mathew#include <asm_macros.S> 9328d304dSSona Mathew#include <common/bl_common.h> 10328d304dSSona Mathew#include <neoverse_v3.h> 11328d304dSSona Mathew#include <cpu_macros.S> 12328d304dSSona Mathew#include <plat_macros.S> 13328d304dSSona Mathew#include "wa_cve_2022_23960_bhb_vector.S" 14328d304dSSona Mathew 15328d304dSSona Mathew/* Hardware handled coherency */ 16328d304dSSona Mathew#if HW_ASSISTED_COHERENCY == 0 17328d304dSSona Mathew#error "Neoverse V3 must be compiled with HW_ASSISTED_COHERENCY enabled" 18328d304dSSona Mathew#endif 19328d304dSSona Mathew 20328d304dSSona Mathew/* 64-bit only core */ 21328d304dSSona Mathew#if CTX_INCLUDE_AARCH32_REGS == 1 22328d304dSSona Mathew#error "Neoverse V3 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23328d304dSSona Mathew#endif 24328d304dSSona Mathew 25328d304dSSona Mathew#if WORKAROUND_CVE_2022_23960 26328d304dSSona Mathew wa_cve_2022_23960_bhb_vector_table NEOVERSE_V3_BHB_LOOP_COUNT, neoverse_v3 27328d304dSSona Mathew#endif /* WORKAROUND_CVE_2022_23960 */ 28328d304dSSona Mathew 29ad3da019SSona Mathew/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 30ad3da019SSona Mathewworkaround_reset_start neoverse_v3, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 31ad3da019SSona Mathew sysreg_bit_set NEOVERSE_V3_CPUECTLR_EL1, BIT(46) 32ad3da019SSona Mathewworkaround_reset_end neoverse_v3, CVE(2024, 5660) 33ad3da019SSona Mathew 34ad3da019SSona Mathewcheck_erratum_ls neoverse_v3, CVE(2024, 5660), CPU_REV(0, 1) 35ad3da019SSona Mathew 36328d304dSSona Mathewworkaround_reset_start neoverse_v3, CVE(2022,23960), WORKAROUND_CVE_2022_23960 37328d304dSSona Mathew#if IMAGE_BL31 38328d304dSSona Mathew /* 39328d304dSSona Mathew * The Neoverse V3 generic vectors are overridden to apply errata 40328d304dSSona Mathew * mitigation on exception entry from lower ELs. 41328d304dSSona Mathew */ 42328d304dSSona Mathew override_vector_table wa_cve_vbar_neoverse_v3 43328d304dSSona Mathew 44328d304dSSona Mathew#endif /* IMAGE_BL31 */ 45328d304dSSona Mathewworkaround_reset_end neoverse_v3, CVE(2022,23960) 46328d304dSSona Mathew 47328d304dSSona Mathewcheck_erratum_chosen neoverse_v3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 48328d304dSSona Mathew 49037a15f5SArvind Ram Prakashworkaround_reset_start neoverse_v3, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 50037a15f5SArvind Ram Prakash /* --------------------------------- 51037a15f5SArvind Ram Prakash * Sets BIT41 of CPUACTLR6_EL1 which 52037a15f5SArvind Ram Prakash * disables L1 Data cache prefetcher 53037a15f5SArvind Ram Prakash * --------------------------------- 54037a15f5SArvind Ram Prakash */ 55037a15f5SArvind Ram Prakash sysreg_bit_set NEOVERSE_V3_CPUACTLR6_EL1, BIT(41) 56037a15f5SArvind Ram Prakashworkaround_reset_end neoverse_v3, CVE(2024, 7881) 57037a15f5SArvind Ram Prakash 58037a15f5SArvind Ram Prakashcheck_erratum_chosen neoverse_v3, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 59037a15f5SArvind Ram Prakash 60328d304dSSona Mathew /* --------------------------------------------- 61328d304dSSona Mathew * HW will do the cache maintenance while powering down 62328d304dSSona Mathew * --------------------------------------------- 63328d304dSSona Mathew */ 64328d304dSSona Mathewfunc neoverse_v3_core_pwr_dwn 65328d304dSSona Mathew /* --------------------------------------------- 66328d304dSSona Mathew * Enable CPU power down bit in power control register 67328d304dSSona Mathew * --------------------------------------------- 68328d304dSSona Mathew */ 69328d304dSSona Mathew sysreg_bit_set NEOVERSE_V3_CPUPWRCTLR_EL1, \ 70328d304dSSona Mathew NEOVERSE_V3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 71328d304dSSona Mathew 72328d304dSSona Mathew isb 73328d304dSSona Mathew ret 74328d304dSSona Mathewendfunc neoverse_v3_core_pwr_dwn 75328d304dSSona Mathew 76328d304dSSona Mathewcpu_reset_func_start neoverse_v3 77328d304dSSona Mathew /* Disable speculative loads */ 78328d304dSSona Mathew msr SSBS, xzr 79328d304dSSona Mathewcpu_reset_func_end neoverse_v3 80328d304dSSona Mathew 81328d304dSSona Mathew /* --------------------------------------------- 82328d304dSSona Mathew * This function provides Neoverse V3 specific 83328d304dSSona Mathew * register information for crash reporting. 84328d304dSSona Mathew * It needs to return with x6 pointing to 85328d304dSSona Mathew * a list of register names in ascii and 86328d304dSSona Mathew * x8 - x15 having values of registers to be 87328d304dSSona Mathew * reported. 88328d304dSSona Mathew * --------------------------------------------- 89328d304dSSona Mathew */ 90328d304dSSona Mathew.section .rodata.neoverse_v3_regs, "aS" 91328d304dSSona Mathewneoverse_v3_regs: /* The ascii list of register names to be reported */ 92328d304dSSona Mathew .asciz "cpuectlr_el1", "" 93328d304dSSona Mathew 94328d304dSSona Mathewfunc neoverse_v3_cpu_reg_dump 95328d304dSSona Mathew adr x6, neoverse_v3_regs 96328d304dSSona Mathew mrs x8, NEOVERSE_V3_CPUECTLR_EL1 97328d304dSSona Mathew ret 98328d304dSSona Mathewendfunc neoverse_v3_cpu_reg_dump 99328d304dSSona Mathew 100328d304dSSona Mathewdeclare_cpu_ops neoverse_v3, NEOVERSE_V3_VNAE_MIDR, \ 101328d304dSSona Mathew neoverse_v3_reset_func, \ 102328d304dSSona Mathew neoverse_v3_core_pwr_dwn 103328d304dSSona Mathew 104*8ae6b1adSArvind Ram Prakashdeclare_cpu_ops_wa_4 neoverse_v3, NEOVERSE_V3_MIDR, \ 105328d304dSSona Mathew neoverse_v3_reset_func, \ 106*8ae6b1adSArvind Ram Prakash CPU_NO_EXTRA1_FUNC, \ 107*8ae6b1adSArvind Ram Prakash CPU_NO_EXTRA2_FUNC, \ 108*8ae6b1adSArvind Ram Prakash CPU_NO_EXTRA3_FUNC, \ 109*8ae6b1adSArvind Ram Prakash check_erratum_neoverse_v3_7881, \ 110328d304dSSona Mathew neoverse_v3_core_pwr_dwn 111