1*328d304dSSona Mathew/* 2*328d304dSSona Mathew * Copyright (c) 2022-2024, Arm Limited. All rights reserved. 3*328d304dSSona Mathew * 4*328d304dSSona Mathew * SPDX-License-Identifier: BSD-3-Clause 5*328d304dSSona Mathew */ 6*328d304dSSona Mathew 7*328d304dSSona Mathew#include <arch.h> 8*328d304dSSona Mathew#include <asm_macros.S> 9*328d304dSSona Mathew#include <common/bl_common.h> 10*328d304dSSona Mathew#include <neoverse_v3.h> 11*328d304dSSona Mathew#include <cpu_macros.S> 12*328d304dSSona Mathew#include <plat_macros.S> 13*328d304dSSona Mathew#include "wa_cve_2022_23960_bhb_vector.S" 14*328d304dSSona Mathew 15*328d304dSSona Mathew/* Hardware handled coherency */ 16*328d304dSSona Mathew#if HW_ASSISTED_COHERENCY == 0 17*328d304dSSona Mathew#error "Neoverse V3 must be compiled with HW_ASSISTED_COHERENCY enabled" 18*328d304dSSona Mathew#endif 19*328d304dSSona Mathew 20*328d304dSSona Mathew/* 64-bit only core */ 21*328d304dSSona Mathew#if CTX_INCLUDE_AARCH32_REGS == 1 22*328d304dSSona Mathew#error "Neoverse V3 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23*328d304dSSona Mathew#endif 24*328d304dSSona Mathew 25*328d304dSSona Mathew#if WORKAROUND_CVE_2022_23960 26*328d304dSSona Mathew wa_cve_2022_23960_bhb_vector_table NEOVERSE_V3_BHB_LOOP_COUNT, neoverse_v3 27*328d304dSSona Mathew#endif /* WORKAROUND_CVE_2022_23960 */ 28*328d304dSSona Mathew 29*328d304dSSona Mathewworkaround_reset_start neoverse_v3, CVE(2022,23960), WORKAROUND_CVE_2022_23960 30*328d304dSSona Mathew#if IMAGE_BL31 31*328d304dSSona Mathew /* 32*328d304dSSona Mathew * The Neoverse V3 generic vectors are overridden to apply errata 33*328d304dSSona Mathew * mitigation on exception entry from lower ELs. 34*328d304dSSona Mathew */ 35*328d304dSSona Mathew override_vector_table wa_cve_vbar_neoverse_v3 36*328d304dSSona Mathew 37*328d304dSSona Mathew#endif /* IMAGE_BL31 */ 38*328d304dSSona Mathewworkaround_reset_end neoverse_v3, CVE(2022,23960) 39*328d304dSSona Mathew 40*328d304dSSona Mathewcheck_erratum_chosen neoverse_v3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 41*328d304dSSona Mathew 42*328d304dSSona Mathew /* --------------------------------------------- 43*328d304dSSona Mathew * HW will do the cache maintenance while powering down 44*328d304dSSona Mathew * --------------------------------------------- 45*328d304dSSona Mathew */ 46*328d304dSSona Mathewfunc neoverse_v3_core_pwr_dwn 47*328d304dSSona Mathew /* --------------------------------------------- 48*328d304dSSona Mathew * Enable CPU power down bit in power control register 49*328d304dSSona Mathew * --------------------------------------------- 50*328d304dSSona Mathew */ 51*328d304dSSona Mathew sysreg_bit_set NEOVERSE_V3_CPUPWRCTLR_EL1, \ 52*328d304dSSona Mathew NEOVERSE_V3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 53*328d304dSSona Mathew 54*328d304dSSona Mathew isb 55*328d304dSSona Mathew ret 56*328d304dSSona Mathewendfunc neoverse_v3_core_pwr_dwn 57*328d304dSSona Mathew 58*328d304dSSona Mathewcpu_reset_func_start neoverse_v3 59*328d304dSSona Mathew /* Disable speculative loads */ 60*328d304dSSona Mathew msr SSBS, xzr 61*328d304dSSona Mathewcpu_reset_func_end neoverse_v3 62*328d304dSSona Mathew 63*328d304dSSona Mathewerrata_report_shim neoverse_v3 64*328d304dSSona Mathew 65*328d304dSSona Mathew /* --------------------------------------------- 66*328d304dSSona Mathew * This function provides Neoverse V3 specific 67*328d304dSSona Mathew * register information for crash reporting. 68*328d304dSSona Mathew * It needs to return with x6 pointing to 69*328d304dSSona Mathew * a list of register names in ascii and 70*328d304dSSona Mathew * x8 - x15 having values of registers to be 71*328d304dSSona Mathew * reported. 72*328d304dSSona Mathew * --------------------------------------------- 73*328d304dSSona Mathew */ 74*328d304dSSona Mathew.section .rodata.neoverse_v3_regs, "aS" 75*328d304dSSona Mathewneoverse_v3_regs: /* The ascii list of register names to be reported */ 76*328d304dSSona Mathew .asciz "cpuectlr_el1", "" 77*328d304dSSona Mathew 78*328d304dSSona Mathewfunc neoverse_v3_cpu_reg_dump 79*328d304dSSona Mathew adr x6, neoverse_v3_regs 80*328d304dSSona Mathew mrs x8, NEOVERSE_V3_CPUECTLR_EL1 81*328d304dSSona Mathew ret 82*328d304dSSona Mathewendfunc neoverse_v3_cpu_reg_dump 83*328d304dSSona Mathew 84*328d304dSSona Mathewdeclare_cpu_ops neoverse_v3, NEOVERSE_V3_VNAE_MIDR, \ 85*328d304dSSona Mathew neoverse_v3_reset_func, \ 86*328d304dSSona Mathew neoverse_v3_core_pwr_dwn 87*328d304dSSona Mathew 88*328d304dSSona Mathewdeclare_cpu_ops neoverse_v3, NEOVERSE_V3_MIDR, \ 89*328d304dSSona Mathew neoverse_v3_reset_func, \ 90*328d304dSSona Mathew neoverse_v3_core_pwr_dwn 91