1/* 2 * Copyright (c) 2021-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <neoverse_v2.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Neoverse V2 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Neoverse V2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 26workaround_reset_start neoverse_v2, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 27 sysreg_bit_set NEOVERSE_V2_CPUECTLR_EL1, BIT(46) 28workaround_reset_end neoverse_v2, CVE(2024, 5660) 29 30check_erratum_ls neoverse_v2, CVE(2024, 5660), CPU_REV(0, 2) 31 32workaround_reset_start neoverse_v2, ERRATUM(2331132), ERRATA_V2_2331132 33 sysreg_bitfield_insert NEOVERSE_V2_CPUECTLR2_EL1, NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_CNSRV, \ 34 NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_LSB, NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_WIDTH 35workaround_reset_end neoverse_v2, ERRATUM(2331132) 36 37check_erratum_ls neoverse_v2, ERRATUM(2331132), CPU_REV(0, 2) 38 39workaround_reset_start neoverse_v2, ERRATUM(2618597), ERRATA_V2_2618597 40 /* Disable retention control for WFI and WFE. */ 41 mrs x0, NEOVERSE_V2_CPUPWRCTLR_EL1 42 bfi x0, xzr, #NEOVERSE_V2_CPUPWRCTLR_EL1_WFI_RET_CTRL_SHIFT, \ 43 #NEOVERSE_V2_CPUPWRCTLR_EL1_WFI_RET_CTRL_WIDTH 44 bfi x0, xzr, #NEOVERSE_V2_CPUPWRCTLR_EL1_WFE_RET_CTRL_SHIFT, \ 45 #NEOVERSE_V2_CPUPWRCTLR_EL1_WFE_RET_CTRL_WIDTH 46 msr NEOVERSE_V2_CPUPWRCTLR_EL1, x0 47workaround_reset_end neoverse_v2, ERRATUM(2618597) 48 49check_erratum_ls neoverse_v2, ERRATUM(2618597), CPU_REV(0, 1) 50 51workaround_reset_start neoverse_v2, ERRATUM(2662553), ERRATA_V2_2662553 52 sysreg_bitfield_insert NEOVERSE_V2_CPUECTLR2_EL1, NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_STATIC_FULL, \ 53 NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_LSB, NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_WIDTH 54workaround_reset_end neoverse_v2, ERRATUM(2662553) 55 56check_erratum_ls neoverse_v2, ERRATUM(2662553), CPU_REV(0, 1) 57 58workaround_reset_start neoverse_v2, ERRATUM(2719105), ERRATA_V2_2719105 59 sysreg_bit_set NEOVERSE_V2_CPUACTLR2_EL1, NEOVERSE_V2_CPUACTLR2_EL1_BIT_0 60workaround_reset_end neoverse_v2, ERRATUM(2719105) 61 62check_erratum_ls neoverse_v2, ERRATUM(2719105), CPU_REV(0, 1) 63 64workaround_reset_start neoverse_v2, ERRATUM(2743011), ERRATA_V2_2743011 65 sysreg_bit_set NEOVERSE_V2_CPUACTLR5_EL1, NEOVERSE_V2_CPUACTLR5_EL1_BIT_55 66 sysreg_bit_clear NEOVERSE_V2_CPUACTLR5_EL1, NEOVERSE_V2_CPUACTLR5_EL1_BIT_56 67workaround_reset_end neoverse_v2, ERRATUM(2743011) 68 69check_erratum_ls neoverse_v2, ERRATUM(2743011), CPU_REV(0, 1) 70 71workaround_reset_start neoverse_v2, ERRATUM(2779510), ERRATA_V2_2779510 72 sysreg_bit_set NEOVERSE_V2_CPUACTLR3_EL1, NEOVERSE_V2_CPUACTLR3_EL1_BIT_47 73workaround_reset_end neoverse_v2, ERRATUM(2779510) 74 75check_erratum_ls neoverse_v2, ERRATUM(2779510), CPU_REV(0, 1) 76 77workaround_runtime_start neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372 78 /* dsb before isb of power down sequence */ 79 dsb sy 80workaround_runtime_end neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372 81 82check_erratum_ls neoverse_v2, ERRATUM(2801372), CPU_REV(0, 1) 83 84workaround_reset_start neoverse_v2, CVE(2022,23960), WORKAROUND_CVE_2022_23960 85#if IMAGE_BL31 86 /* 87 * The Neoverse-V2 generic vectors are overridden to apply errata 88 * mitigation on exception entry from lower ELs. 89 */ 90 override_vector_table wa_cve_vbar_neoverse_v2 91#endif /* IMAGE_BL31 */ 92workaround_reset_end neoverse_v2, CVE(2022,23960) 93 94check_erratum_chosen neoverse_v2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 95 96#if WORKAROUND_CVE_2022_23960 97 wa_cve_2022_23960_bhb_vector_table NEOVERSE_V2_BHB_LOOP_COUNT, neoverse_v2 98#endif /* WORKAROUND_CVE_2022_23960 */ 99 100workaround_reset_start neoverse_v2, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 101 /* --------------------------------- 102 * Sets BIT41 of CPUACTLR6_EL1 which 103 * disables L1 Data cache prefetcher 104 * --------------------------------- 105 */ 106 sysreg_bit_set NEOVERSE_V2_CPUACTLR6_EL1, BIT(41) 107workaround_reset_end neoverse_v2, CVE(2024, 7881) 108 109check_erratum_chosen neoverse_v2, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 110 111 /* ---------------------------------------------------- 112 * HW will do the cache maintenance while powering down 113 * ---------------------------------------------------- 114 */ 115func neoverse_v2_core_pwr_dwn 116 /* --------------------------------------------------- 117 * Enable CPU power down bit in power control register 118 * --------------------------------------------------- 119 */ 120 sysreg_bit_set NEOVERSE_V2_CPUPWRCTLR_EL1, NEOVERSE_V2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 121 apply_erratum neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372, NO_GET_CPU_REV 122 123 isb 124 ret 125endfunc neoverse_v2_core_pwr_dwn 126 127cpu_reset_func_start neoverse_v2 128 /* Disable speculative loads */ 129 msr SSBS, xzr 130 131#if NEOVERSE_Vx_EXTERNAL_LLC 132 /* Some systems may have External LLC, core needs to be made aware */ 133 sysreg_bit_set NEOVERSE_V2_CPUECTLR_EL1, NEOVERSE_V2_CPUECTLR_EL1_EXTLLC_BIT 134#endif 135cpu_reset_func_end neoverse_v2 136 137 /* --------------------------------------------- 138 * This function provides Neoverse V2- 139 * specific register information for crash 140 * reporting. It needs to return with x6 141 * pointing to a list of register names in ascii 142 * and x8 - x15 having values of registers to be 143 * reported. 144 * --------------------------------------------- 145 */ 146.section .rodata.neoverse_v2_regs, "aS" 147neoverse_v2_regs: /* The ascii list of register names to be reported */ 148 .asciz "cpuectlr_el1", "" 149 150func neoverse_v2_cpu_reg_dump 151 adr x6, neoverse_v2_regs 152 mrs x8, NEOVERSE_V2_CPUECTLR_EL1 153 ret 154endfunc neoverse_v2_cpu_reg_dump 155 156declare_cpu_ops_wa_4 neoverse_v2, NEOVERSE_V2_MIDR, \ 157 neoverse_v2_reset_func, \ 158 CPU_NO_EXTRA1_FUNC, \ 159 CPU_NO_EXTRA2_FUNC, \ 160 CPU_NO_EXTRA3_FUNC, \ 161 check_erratum_neoverse_v2_7881, \ 162 neoverse_v2_core_pwr_dwn 163