1/* 2 * Copyright (c) 2021-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <neoverse_v2.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Neoverse V2 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Neoverse V2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25cpu_reset_prologue neoverse_v2 26 27/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 28workaround_reset_start neoverse_v2, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 29 sysreg_bit_set NEOVERSE_V2_CPUECTLR_EL1, BIT(46) 30workaround_reset_end neoverse_v2, CVE(2024, 5660) 31 32check_erratum_ls neoverse_v2, CVE(2024, 5660), CPU_REV(0, 2) 33 34workaround_reset_start neoverse_v2, ERRATUM(2331132), ERRATA_V2_2331132 35 sysreg_bitfield_insert NEOVERSE_V2_CPUECTLR2_EL1, NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_CNSRV, \ 36 NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_LSB, NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_WIDTH 37workaround_reset_end neoverse_v2, ERRATUM(2331132) 38 39check_erratum_ls neoverse_v2, ERRATUM(2331132), CPU_REV(0, 2) 40 41workaround_reset_start neoverse_v2, ERRATUM(2618597), ERRATA_V2_2618597 42 /* Disable retention control for WFI and WFE. */ 43 mrs x0, NEOVERSE_V2_CPUPWRCTLR_EL1 44 bfi x0, xzr, #NEOVERSE_V2_CPUPWRCTLR_EL1_WFI_RET_CTRL_SHIFT, \ 45 #NEOVERSE_V2_CPUPWRCTLR_EL1_WFI_RET_CTRL_WIDTH 46 bfi x0, xzr, #NEOVERSE_V2_CPUPWRCTLR_EL1_WFE_RET_CTRL_SHIFT, \ 47 #NEOVERSE_V2_CPUPWRCTLR_EL1_WFE_RET_CTRL_WIDTH 48 msr NEOVERSE_V2_CPUPWRCTLR_EL1, x0 49workaround_reset_end neoverse_v2, ERRATUM(2618597) 50 51check_erratum_ls neoverse_v2, ERRATUM(2618597), CPU_REV(0, 1) 52 53workaround_reset_start neoverse_v2, ERRATUM(2662553), ERRATA_V2_2662553 54 sysreg_bitfield_insert NEOVERSE_V2_CPUECTLR2_EL1, NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_STATIC_FULL, \ 55 NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_LSB, NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_WIDTH 56workaround_reset_end neoverse_v2, ERRATUM(2662553) 57 58check_erratum_ls neoverse_v2, ERRATUM(2662553), CPU_REV(0, 1) 59 60workaround_reset_start neoverse_v2, ERRATUM(2719105), ERRATA_V2_2719105 61 sysreg_bit_set NEOVERSE_V2_CPUACTLR2_EL1, NEOVERSE_V2_CPUACTLR2_EL1_BIT_0 62workaround_reset_end neoverse_v2, ERRATUM(2719105) 63 64check_erratum_ls neoverse_v2, ERRATUM(2719105), CPU_REV(0, 1) 65 66workaround_reset_start neoverse_v2, ERRATUM(2743011), ERRATA_V2_2743011 67 sysreg_bit_set NEOVERSE_V2_CPUACTLR5_EL1, NEOVERSE_V2_CPUACTLR5_EL1_BIT_55 68 sysreg_bit_clear NEOVERSE_V2_CPUACTLR5_EL1, NEOVERSE_V2_CPUACTLR5_EL1_BIT_56 69workaround_reset_end neoverse_v2, ERRATUM(2743011) 70 71check_erratum_ls neoverse_v2, ERRATUM(2743011), CPU_REV(0, 1) 72 73workaround_reset_start neoverse_v2, ERRATUM(2779510), ERRATA_V2_2779510 74 sysreg_bit_set NEOVERSE_V2_CPUACTLR3_EL1, NEOVERSE_V2_CPUACTLR3_EL1_BIT_47 75workaround_reset_end neoverse_v2, ERRATUM(2779510) 76 77check_erratum_ls neoverse_v2, ERRATUM(2779510), CPU_REV(0, 1) 78 79workaround_runtime_start neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372 80 /* dsb before isb of power down sequence */ 81 dsb sy 82workaround_runtime_end neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372 83 84check_erratum_ls neoverse_v2, ERRATUM(2801372), CPU_REV(0, 1) 85 86workaround_reset_start neoverse_v2, CVE(2022,23960), WORKAROUND_CVE_2022_23960 87#if IMAGE_BL31 88 /* 89 * The Neoverse-V2 generic vectors are overridden to apply errata 90 * mitigation on exception entry from lower ELs. 91 */ 92 override_vector_table wa_cve_vbar_neoverse_v2 93#endif /* IMAGE_BL31 */ 94workaround_reset_end neoverse_v2, CVE(2022,23960) 95 96check_erratum_chosen neoverse_v2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 97 98#if WORKAROUND_CVE_2022_23960 99 wa_cve_2022_23960_bhb_vector_table NEOVERSE_V2_BHB_LOOP_COUNT, neoverse_v2 100#endif /* WORKAROUND_CVE_2022_23960 */ 101 102workaround_reset_start neoverse_v2, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 103 /* --------------------------------- 104 * Sets BIT41 of CPUACTLR6_EL1 which 105 * disables L1 Data cache prefetcher 106 * --------------------------------- 107 */ 108 sysreg_bit_set NEOVERSE_V2_CPUACTLR6_EL1, BIT(41) 109workaround_reset_end neoverse_v2, CVE(2024, 7881) 110 111check_erratum_chosen neoverse_v2, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 112 113 /* ---------------------------------------------------- 114 * HW will do the cache maintenance while powering down 115 * ---------------------------------------------------- 116 */ 117func neoverse_v2_core_pwr_dwn 118 /* --------------------------------------------------- 119 * Enable CPU power down bit in power control register 120 * --------------------------------------------------- 121 */ 122 sysreg_bit_set NEOVERSE_V2_CPUPWRCTLR_EL1, NEOVERSE_V2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 123 apply_erratum neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372, NO_GET_CPU_REV 124 125 isb 126 ret 127endfunc neoverse_v2_core_pwr_dwn 128 129cpu_reset_func_start neoverse_v2 130 /* Disable speculative loads */ 131 msr SSBS, xzr 132 133#if NEOVERSE_Vx_EXTERNAL_LLC 134 /* Some systems may have External LLC, core needs to be made aware */ 135 sysreg_bit_set NEOVERSE_V2_CPUECTLR_EL1, NEOVERSE_V2_CPUECTLR_EL1_EXTLLC_BIT 136#endif 137cpu_reset_func_end neoverse_v2 138 139 /* --------------------------------------------- 140 * This function provides Neoverse V2- 141 * specific register information for crash 142 * reporting. It needs to return with x6 143 * pointing to a list of register names in ascii 144 * and x8 - x15 having values of registers to be 145 * reported. 146 * --------------------------------------------- 147 */ 148.section .rodata.neoverse_v2_regs, "aS" 149neoverse_v2_regs: /* The ascii list of register names to be reported */ 150 .asciz "cpuectlr_el1", "" 151 152func neoverse_v2_cpu_reg_dump 153 adr x6, neoverse_v2_regs 154 mrs x8, NEOVERSE_V2_CPUECTLR_EL1 155 ret 156endfunc neoverse_v2_cpu_reg_dump 157 158declare_cpu_ops_wa_4 neoverse_v2, NEOVERSE_V2_MIDR, \ 159 neoverse_v2_reset_func, \ 160 CPU_NO_EXTRA1_FUNC, \ 161 CPU_NO_EXTRA2_FUNC, \ 162 CPU_NO_EXTRA3_FUNC, \ 163 check_erratum_neoverse_v2_7881, \ 164 neoverse_v2_core_pwr_dwn 165