1/* 2 * Copyright (c) 2021-2023, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <neoverse_v2.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Neoverse V2 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Neoverse V2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25workaround_reset_start neoverse_v2, ERRATUM(2331132), ERRATA_V2_2331132 26 sysreg_bitfield_insert NEOVERSE_V2_CPUECTLR2_EL1, NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_CNSRV, \ 27 NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_LSB, NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_WIDTH 28workaround_reset_end neoverse_v2, ERRATUM(2331132) 29 30check_erratum_ls neoverse_v2, ERRATUM(2331132), CPU_REV(0, 2) 31 32workaround_reset_start neoverse_v2, ERRATUM(2719105), ERRATA_V2_2719105 33 sysreg_bit_set NEOVERSE_V2_CPUACTLR2_EL1, NEOVERSE_V2_CPUACTLR2_EL1_BIT_0 34workaround_reset_end neoverse_v2, ERRATUM(2719105) 35 36check_erratum_ls neoverse_v2, ERRATUM(2719105), CPU_REV(0, 1) 37 38workaround_reset_start neoverse_v2, ERRATUM(2743011), ERRATA_V2_2743011 39 sysreg_bit_set NEOVERSE_V2_CPUACTLR5_EL1, NEOVERSE_V2_CPUACTLR5_EL1_BIT_55 40 sysreg_bit_clear NEOVERSE_V2_CPUACTLR5_EL1, NEOVERSE_V2_CPUACTLR5_EL1_BIT_56 41workaround_reset_end neoverse_v2, ERRATUM(2743011) 42 43check_erratum_ls neoverse_v2, ERRATUM(2743011), CPU_REV(0, 1) 44 45workaround_reset_start neoverse_v2, ERRATUM(2779510), ERRATA_V2_2779510 46 sysreg_bit_set NEOVERSE_V2_CPUACTLR3_EL1, NEOVERSE_V2_CPUACTLR3_EL1_BIT_47 47workaround_reset_end neoverse_v2, ERRATUM(2779510) 48 49check_erratum_ls neoverse_v2, ERRATUM(2779510), CPU_REV(0, 1) 50 51workaround_runtime_start neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372 52 /* dsb before isb of power down sequence */ 53 dsb sy 54workaround_runtime_end neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372 55 56check_erratum_ls neoverse_v2, ERRATUM(2801372), CPU_REV(0, 1) 57 58workaround_reset_start neoverse_v2, CVE(2022,23960), WORKAROUND_CVE_2022_23960 59#if IMAGE_BL31 60 /* 61 * The Neoverse-V2 generic vectors are overridden to apply errata 62 * mitigation on exception entry from lower ELs. 63 */ 64 override_vector_table wa_cve_vbar_neoverse_v2 65#endif /* IMAGE_BL31 */ 66workaround_reset_end neoverse_v2, CVE(2022,23960) 67 68check_erratum_chosen neoverse_v2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 69 70#if WORKAROUND_CVE_2022_23960 71 wa_cve_2022_23960_bhb_vector_table NEOVERSE_V2_BHB_LOOP_COUNT, neoverse_v2 72#endif /* WORKAROUND_CVE_2022_23960 */ 73 74 /* ---------------------------------------------------- 75 * HW will do the cache maintenance while powering down 76 * ---------------------------------------------------- 77 */ 78func neoverse_v2_core_pwr_dwn 79 /* --------------------------------------------------- 80 * Enable CPU power down bit in power control register 81 * --------------------------------------------------- 82 */ 83 sysreg_bit_set NEOVERSE_V2_CPUPWRCTLR_EL1, NEOVERSE_V2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 84 apply_erratum neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372 85 86 isb 87 ret 88endfunc neoverse_v2_core_pwr_dwn 89 90cpu_reset_func_start neoverse_v2 91 /* Disable speculative loads */ 92 msr SSBS, xzr 93cpu_reset_func_end neoverse_v2 94 95errata_report_shim neoverse_v2 96 /* --------------------------------------------- 97 * This function provides Neoverse V2- 98 * specific register information for crash 99 * reporting. It needs to return with x6 100 * pointing to a list of register names in ascii 101 * and x8 - x15 having values of registers to be 102 * reported. 103 * --------------------------------------------- 104 */ 105.section .rodata.neoverse_v2_regs, "aS" 106neoverse_v2_regs: /* The ascii list of register names to be reported */ 107 .asciz "cpuectlr_el1", "" 108 109func neoverse_v2_cpu_reg_dump 110 adr x6, neoverse_v2_regs 111 mrs x8, NEOVERSE_V2_CPUECTLR_EL1 112 ret 113endfunc neoverse_v2_cpu_reg_dump 114 115declare_cpu_ops neoverse_v2, NEOVERSE_V2_MIDR, \ 116 neoverse_v2_reset_func, \ 117 neoverse_v2_core_pwr_dwn 118