1*bd063a73SJoel Goddard/* 2*bd063a73SJoel Goddard * Copyright (c) 2021-2022, Arm Limited. All rights reserved. 3*bd063a73SJoel Goddard * 4*bd063a73SJoel Goddard * SPDX-License-Identifier: BSD-3-Clause 5*bd063a73SJoel Goddard */ 6*bd063a73SJoel Goddard 7*bd063a73SJoel Goddard#include <arch.h> 8*bd063a73SJoel Goddard#include <asm_macros.S> 9*bd063a73SJoel Goddard#include <common/bl_common.h> 10*bd063a73SJoel Goddard#include <neoverse_v2.h> 11*bd063a73SJoel Goddard#include <cpu_macros.S> 12*bd063a73SJoel Goddard#include <plat_macros.S> 13*bd063a73SJoel Goddard#include "wa_cve_2022_23960_bhb_vector.S" 14*bd063a73SJoel Goddard 15*bd063a73SJoel Goddard/* Hardware handled coherency */ 16*bd063a73SJoel Goddard#if HW_ASSISTED_COHERENCY == 0 17*bd063a73SJoel Goddard#error "Neoverse V2 must be compiled with HW_ASSISTED_COHERENCY enabled" 18*bd063a73SJoel Goddard#endif 19*bd063a73SJoel Goddard 20*bd063a73SJoel Goddard/* 64-bit only core */ 21*bd063a73SJoel Goddard#if CTX_INCLUDE_AARCH32_REGS == 1 22*bd063a73SJoel Goddard#error "Neoverse V2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23*bd063a73SJoel Goddard#endif 24*bd063a73SJoel Goddard 25*bd063a73SJoel Goddard#if WORKAROUND_CVE_2022_23960 26*bd063a73SJoel Goddard wa_cve_2022_23960_bhb_vector_table NEOVERSE_V2_BHB_LOOP_COUNT, neoverse_v2 27*bd063a73SJoel Goddard#endif /* WORKAROUND_CVE_2022_23960 */ 28*bd063a73SJoel Goddard 29*bd063a73SJoel Goddard /* ---------------------------------------------------- 30*bd063a73SJoel Goddard * HW will do the cache maintenance while powering down 31*bd063a73SJoel Goddard * ---------------------------------------------------- 32*bd063a73SJoel Goddard */ 33*bd063a73SJoel Goddardfunc neoverse_v2_core_pwr_dwn 34*bd063a73SJoel Goddard /* --------------------------------------------------- 35*bd063a73SJoel Goddard * Enable CPU power down bit in power control register 36*bd063a73SJoel Goddard * --------------------------------------------------- 37*bd063a73SJoel Goddard */ 38*bd063a73SJoel Goddard mrs x0, NEOVERSE_V2_CPUPWRCTLR_EL1 39*bd063a73SJoel Goddard orr x0, x0, #NEOVERSE_V2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 40*bd063a73SJoel Goddard msr NEOVERSE_V2_CPUPWRCTLR_EL1, x0 41*bd063a73SJoel Goddard isb 42*bd063a73SJoel Goddard ret 43*bd063a73SJoel Goddardendfunc neoverse_v2_core_pwr_dwn 44*bd063a73SJoel Goddard 45*bd063a73SJoel Goddardfunc check_errata_cve_2022_23960 46*bd063a73SJoel Goddard#if WORKAROUND_CVE_2022_23960 47*bd063a73SJoel Goddard mov x0, #ERRATA_APPLIES 48*bd063a73SJoel Goddard#else 49*bd063a73SJoel Goddard mov x0, #ERRATA_MISSING 50*bd063a73SJoel Goddard#endif 51*bd063a73SJoel Goddard ret 52*bd063a73SJoel Goddardendfunc check_errata_cve_2022_23960 53*bd063a73SJoel Goddard 54*bd063a73SJoel Goddardfunc neoverse_v2_reset_func 55*bd063a73SJoel Goddard /* Disable speculative loads */ 56*bd063a73SJoel Goddard msr SSBS, xzr 57*bd063a73SJoel Goddard 58*bd063a73SJoel Goddard#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 59*bd063a73SJoel Goddard /* 60*bd063a73SJoel Goddard * The Neoverse V2 vectors are overridden to apply 61*bd063a73SJoel Goddard * errata mitigation on exception entry from lower ELs. 62*bd063a73SJoel Goddard */ 63*bd063a73SJoel Goddard adr x0, wa_cve_vbar_neoverse_v2 64*bd063a73SJoel Goddard msr vbar_el3, x0 65*bd063a73SJoel Goddard#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ 66*bd063a73SJoel Goddard isb 67*bd063a73SJoel Goddard ret 68*bd063a73SJoel Goddardendfunc neoverse_v2_reset_func 69*bd063a73SJoel Goddard 70*bd063a73SJoel Goddard#if REPORT_ERRATA 71*bd063a73SJoel Goddard/* 72*bd063a73SJoel Goddard * Errata printing function for Neoverse V2. Must follow AAPCS. 73*bd063a73SJoel Goddard */ 74*bd063a73SJoel Goddardfunc neoverse_v2_errata_report 75*bd063a73SJoel Goddard stp x8, x30, [sp, #-16]! 76*bd063a73SJoel Goddard 77*bd063a73SJoel Goddard bl cpu_get_rev_var 78*bd063a73SJoel Goddard mov x8, x0 79*bd063a73SJoel Goddard 80*bd063a73SJoel Goddard /* 81*bd063a73SJoel Goddard * Report all errata. The revision-variant information is passed to 82*bd063a73SJoel Goddard * checking functions of each errata. 83*bd063a73SJoel Goddard */ 84*bd063a73SJoel Goddard report_errata WORKAROUND_CVE_2022_23960, neoverse_v2, cve_2022_23960 85*bd063a73SJoel Goddard 86*bd063a73SJoel Goddard ldp x8, x30, [sp], #16 87*bd063a73SJoel Goddard ret 88*bd063a73SJoel Goddardendfunc neoverse_v2_errata_report 89*bd063a73SJoel Goddard#endif 90*bd063a73SJoel Goddard 91*bd063a73SJoel Goddard /* --------------------------------------------- 92*bd063a73SJoel Goddard * This function provides Neoverse V2- 93*bd063a73SJoel Goddard * specific register information for crash 94*bd063a73SJoel Goddard * reporting. It needs to return with x6 95*bd063a73SJoel Goddard * pointing to a list of register names in ascii 96*bd063a73SJoel Goddard * and x8 - x15 having values of registers to be 97*bd063a73SJoel Goddard * reported. 98*bd063a73SJoel Goddard * --------------------------------------------- 99*bd063a73SJoel Goddard */ 100*bd063a73SJoel Goddard.section .rodata.neoverse_v2_regs, "aS" 101*bd063a73SJoel Goddardneoverse_v2_regs: /* The ascii list of register names to be reported */ 102*bd063a73SJoel Goddard .asciz "cpuectlr_el1", "" 103*bd063a73SJoel Goddard 104*bd063a73SJoel Goddardfunc neoverse_v2_cpu_reg_dump 105*bd063a73SJoel Goddard adr x6, neoverse_v2_regs 106*bd063a73SJoel Goddard mrs x8, NEOVERSE_V2_CPUECTLR_EL1 107*bd063a73SJoel Goddard ret 108*bd063a73SJoel Goddardendfunc neoverse_v2_cpu_reg_dump 109*bd063a73SJoel Goddard 110*bd063a73SJoel Goddarddeclare_cpu_ops neoverse_v2, NEOVERSE_V2_MIDR, \ 111*bd063a73SJoel Goddard neoverse_v2_reset_func, \ 112*bd063a73SJoel Goddard neoverse_v2_core_pwr_dwn 113