1bd063a73SJoel Goddard/* 2*31a3da83SMoritz Fischer * Copyright (c) 2021-2023, Arm Limited. All rights reserved. 3bd063a73SJoel Goddard * 4bd063a73SJoel Goddard * SPDX-License-Identifier: BSD-3-Clause 5bd063a73SJoel Goddard */ 6bd063a73SJoel Goddard 7bd063a73SJoel Goddard#include <arch.h> 8bd063a73SJoel Goddard#include <asm_macros.S> 9bd063a73SJoel Goddard#include <common/bl_common.h> 10bd063a73SJoel Goddard#include <neoverse_v2.h> 11bd063a73SJoel Goddard#include <cpu_macros.S> 12bd063a73SJoel Goddard#include <plat_macros.S> 13bd063a73SJoel Goddard#include "wa_cve_2022_23960_bhb_vector.S" 14bd063a73SJoel Goddard 15bd063a73SJoel Goddard/* Hardware handled coherency */ 16bd063a73SJoel Goddard#if HW_ASSISTED_COHERENCY == 0 17bd063a73SJoel Goddard#error "Neoverse V2 must be compiled with HW_ASSISTED_COHERENCY enabled" 18bd063a73SJoel Goddard#endif 19bd063a73SJoel Goddard 20bd063a73SJoel Goddard/* 64-bit only core */ 21bd063a73SJoel Goddard#if CTX_INCLUDE_AARCH32_REGS == 1 22bd063a73SJoel Goddard#error "Neoverse V2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23bd063a73SJoel Goddard#endif 24bd063a73SJoel Goddard 25*31a3da83SMoritz Fischerworkaround_runtime_start neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372 26*31a3da83SMoritz Fischer /* dsb before isb of power down sequence */ 27*31a3da83SMoritz Fischer dsb sy 28*31a3da83SMoritz Fischerworkaround_runtime_end neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372 29*31a3da83SMoritz Fischer 30*31a3da83SMoritz Fischercheck_erratum_ls neoverse_v2, ERRATUM(2801372), CPU_REV(0, 1) 31*31a3da83SMoritz Fischer 32*31a3da83SMoritz Fischerworkaround_reset_start neoverse_v2, CVE(2022,23960), WORKAROUND_CVE_2022_23960 33*31a3da83SMoritz Fischer#if IMAGE_BL31 34*31a3da83SMoritz Fischer /* 35*31a3da83SMoritz Fischer * The Neoverse-V2 generic vectors are overridden to apply errata 36*31a3da83SMoritz Fischer * mitigation on exception entry from lower ELs. 37*31a3da83SMoritz Fischer */ 38*31a3da83SMoritz Fischer adr x0, wa_cve_vbar_neoverse_v2 39*31a3da83SMoritz Fischer msr vbar_el3, x0 40*31a3da83SMoritz Fischer#endif /* IMAGE_BL31 */ 41*31a3da83SMoritz Fischerworkaround_reset_end neoverse_v2, CVE(2022,23960) 42*31a3da83SMoritz Fischer 43*31a3da83SMoritz Fischercheck_erratum_chosen neoverse_v2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 44*31a3da83SMoritz Fischer 45bd063a73SJoel Goddard#if WORKAROUND_CVE_2022_23960 46bd063a73SJoel Goddard wa_cve_2022_23960_bhb_vector_table NEOVERSE_V2_BHB_LOOP_COUNT, neoverse_v2 47bd063a73SJoel Goddard#endif /* WORKAROUND_CVE_2022_23960 */ 48bd063a73SJoel Goddard 49bd063a73SJoel Goddard /* ---------------------------------------------------- 50bd063a73SJoel Goddard * HW will do the cache maintenance while powering down 51bd063a73SJoel Goddard * ---------------------------------------------------- 52bd063a73SJoel Goddard */ 53bd063a73SJoel Goddardfunc neoverse_v2_core_pwr_dwn 54bd063a73SJoel Goddard /* --------------------------------------------------- 55bd063a73SJoel Goddard * Enable CPU power down bit in power control register 56bd063a73SJoel Goddard * --------------------------------------------------- 57bd063a73SJoel Goddard */ 58bd063a73SJoel Goddard mrs x0, NEOVERSE_V2_CPUPWRCTLR_EL1 59bd063a73SJoel Goddard orr x0, x0, #NEOVERSE_V2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 60bd063a73SJoel Goddard msr NEOVERSE_V2_CPUPWRCTLR_EL1, x0 61*31a3da83SMoritz Fischer 62*31a3da83SMoritz Fischer apply_erratum neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372 63*31a3da83SMoritz Fischer 64bd063a73SJoel Goddard isb 65bd063a73SJoel Goddard ret 66bd063a73SJoel Goddardendfunc neoverse_v2_core_pwr_dwn 67bd063a73SJoel Goddard 68*31a3da83SMoritz Fischercpu_reset_func_start neoverse_v2 69bd063a73SJoel Goddard /* Disable speculative loads */ 70bd063a73SJoel Goddard msr SSBS, xzr 71*31a3da83SMoritz Fischercpu_reset_func_end neoverse_v2 72bd063a73SJoel Goddard 73*31a3da83SMoritz Fischererrata_report_shim neoverse_v2 74bd063a73SJoel Goddard /* --------------------------------------------- 75bd063a73SJoel Goddard * This function provides Neoverse V2- 76bd063a73SJoel Goddard * specific register information for crash 77bd063a73SJoel Goddard * reporting. It needs to return with x6 78bd063a73SJoel Goddard * pointing to a list of register names in ascii 79bd063a73SJoel Goddard * and x8 - x15 having values of registers to be 80bd063a73SJoel Goddard * reported. 81bd063a73SJoel Goddard * --------------------------------------------- 82bd063a73SJoel Goddard */ 83bd063a73SJoel Goddard.section .rodata.neoverse_v2_regs, "aS" 84bd063a73SJoel Goddardneoverse_v2_regs: /* The ascii list of register names to be reported */ 85bd063a73SJoel Goddard .asciz "cpuectlr_el1", "" 86bd063a73SJoel Goddard 87bd063a73SJoel Goddardfunc neoverse_v2_cpu_reg_dump 88bd063a73SJoel Goddard adr x6, neoverse_v2_regs 89bd063a73SJoel Goddard mrs x8, NEOVERSE_V2_CPUECTLR_EL1 90bd063a73SJoel Goddard ret 91bd063a73SJoel Goddardendfunc neoverse_v2_cpu_reg_dump 92bd063a73SJoel Goddard 93bd063a73SJoel Goddarddeclare_cpu_ops neoverse_v2, NEOVERSE_V2_MIDR, \ 94bd063a73SJoel Goddard neoverse_v2_reset_func, \ 95bd063a73SJoel Goddard neoverse_v2_core_pwr_dwn 96